CN111082669B

CN111082669B - Method for generating complementary drive signals for a converter and oscillator

Info

Publication number: CN111082669B
Application number: CN201811231551.3A
Authority: CN
Inventors: 崔能伟
Original assignee: Suzhou Yuante Semiconductor Technology Co ltd
Current assignee: Suzhou Yuante Semiconductor Technology Co ltd
Priority date: 2018-10-22
Filing date: 2018-10-22
Publication date: 2023-04-21
Anticipated expiration: 2038-10-22
Also published as: CN111082669A

Abstract

The invention provides a method for generating a complementary driving signal of an inverter and an oscillator, wherein a driving process of a power tube is used as a part of cyclic oscillation of the oscillator, a driving voltage detection module detects and judges that dead time is generated after the power tube is turned off, and pulse width signals are generated after next oscillation is performed, and the whole process is closed-loop, so that the phenomenon of large dead time error caused by the driving delay of the power tube can be effectively avoided.

Description

Method for generating complementary drive signals for a converter and oscillator

Technical Field

The present invention relates to a method for generating a complementary driving signal of a converter and an oscillator thereof, and more particularly, to a method for generating a complementary driving signal of a converter and an oscillator thereof.

Background

As shown in fig. 1, the self-excited push-pull converter in the prior art is widely applied to the DCDC isolation converter of the micropower module due to the characteristics of simple structure, high magnetic flux utilization rate and small volume. However, due to some inherent defects of self-excited push-pull and rapid development of integrated circuit technology in recent years, the self-excited push-pull of the integrated circuit is gradually replaced by the self-excited push-pull of the integrated circuit, because the integrated circuit has better device matching property and detection and control of signals, the consistency and reliability of the converter can be greatly improved, for example, the low-noise push-pull controller SN6501 pushed by TI.

As shown in fig. 2, the push-pull controller SN6501, the oscillator OSC generates two complementary logic signals S and c via a frequency divider freq

Then two paths of complementary signals G with certain dead time are generated through a BBM Logic module ₂ And G ₁ . The complementary driving signal is generated by frequency division, and then the width of the two signals is the same, the duty cycle is 50%, so the symmetry is extremely high, and the symmetry is independent of the parameters of the oscillator OSC, and only affects the oscillation period, i.e. the width of the two signals. The high symmetry of the driving is required by push-pull and full-bridge power supply topological structures, and the parameters of the MOS tube Q1 and the MOS tube Q2 can also meet the high consistency, so that the magnetic bias phenomenon of the power supply can be effectively reduced. The BBM Logic module generates dead time for two paths of signals, and because the MOS transistor Q1 and the MOS transistor Q2 cannot be simultaneously turned on, one MOS transistor is turned off and then another MOS transistor is turned on for a short time, as shown in fig. 3, t _BBM Is the dead time of the drive.

The polarity of the voltage applied by the transformer when MOS transistor Q1 is on is indicated in FIG. 2, and the primary current from VIn enters winding N _P2 And MOS transistor Q1 to ground, secondary side current from passing through winding N _S1 And forward biased diode D1 to capacitor C _O And the MOS tube Q2 and the diode D2 are in a reverse bias cut-off state after being charged. When the MOS transistor Q2 is turned on, energy is transferred from VIn through the primary winding and the secondary winding of the transformer and stored in the output capacitor C through the forward-biased rectifier diode D2 _O In the MOS transistor Q1 and the MOS transistor Q2 are alternately switched repeatedly, and energy is transmitted from the primary side VIn to the secondary side V of the isolation transformer _OUT The load side that needs to be isolated can obtain the required energy from there.

As shown in fig. 4, an oscillator provides driving timing for two power transistors Q1 and Q2 of a push-pull converter, the oscillator includes: the pulse width generation module 101, the frequency division module 102, the two driving modules 103 and the delay circuit 105. The frequency dividing module 102 separates the CLK signal output by the pulse width generating module 101 into two complementary signals S and

the two driving modules 103 drive the power tubes according to complementary time sequences under the action of two paths of complementary signals. The CLK signal is input to the circuit through the NOT gate NOT and the NAND gate NAND, and the NOT gate NOT and the NAND gate NAND perform two times of 'NOT' operation on the CLK signal, which is logically the same as the CLK signal directly connected to the input end Ldi of the delay circuit 105, and the NAND gate NAND is specially added for strong contrast, so that the time interval of generating two paths of complementary driving signals, that is, the dead time is generated.

As shown in fig. 5, the clock CLK with a set low level width generated by the oscillator is divided to generate two paths of selection signals, and two paths of complementary control signals S and are separated by two and gates

Rising edge of S and->

Or S and +.>

The time width between the rising edges of (2) is also the dead time width, i.e. t2 to t3 in the figure,t4 to t5, t6 to t7. According to S and->

The provided timing, the driving circuit turns on the two power transistors Q1 and Q2, respectively, at the active high level, resulting in gate voltage waveforms G2 and G1, respectively. At time t 2S becomes low level, the voltage of G2 begins to drop after a short period of time until the voltage at time t23 is smaller than the threshold voltage of the power tube Q2 and is actually turned off, and then the voltage is +.>

When the voltage goes high, the gate voltage G1 of the power transistor Q1 reaches a threshold voltage at time t3 and turns on. It can be seen that the voltage of the gate is gradually reduced and the power tube is actually turned off at the time t23, so that the time t 23-t 2 is eaten up between t 2-t 3 due to the existence of the driving delay, and the real dead time is approximately equal to t3 minus t23. Therefore, due to poor parameter precision or temperature variation of the device, the situations of small dead time and large driving delay are easy to occur, and the phenomenon that two power tubes are conducted simultaneously can be caused.

As shown in fig. 6, the gate voltage G2 of the power transistor Q2 does not drop below the threshold voltage between the dead times t2' to t3', and is not actually turned off until t23', so that the two power transistors Q1 and Q2 are common during the time t3' to t32 '.

Whether the oscillator generating the complementary signal is designed by adopting the traditional scheme or the push-pull controller SN6501, the common characteristic is that the complementary driving signal is generated by the oscillator to generate two paths of complementary control signals, and then the two paths of complementary control signals are transmitted to the driving module for driving the power tube, and the process is open-loop, so that the defect of poor consistency exists in practical application. The reason is as follows:

first, dead time is required to exist in driving the two power tubes of the push-pull converter, otherwise, a phenomenon that the two power tubes are common occurs, and therefore performance problems such as efficiency, EMI and noise exist.

Second, in order to reduce switching noise and EMI of the push-pull converter, the output of the driving circuit is to increase a circuit similar to a resistor to reduce the driving speed of the power tube, and the driving delay is relatively large, especially like the low noise characteristic of a chip of TI company.

Third, the dead time of the complementary control signal is generated by a separate circuit, independent of the drive circuit.

Fourth, although the matching performance between devices inside the integrated circuit can be well made, the absolute value of the parameter is inaccurate, the precision of the resistor and the capacitor is about +/-20%, and the resistor has a larger temperature coefficient. Therefore, the dead time of the complementary control signal and the delay generated by the power tube driving circuit are inaccurate, the difference value between the dead time and the delay is the real dead time tBBM of the driving voltage of the two power tubes, and if the dead time of the control signal is smaller, the driving delay of the power tubes is larger, so that the common use is easily caused.

Fifth, if the dead time of the control signal is increased, the dead time may be increased, and the dead time is increased, so that the actual duty ratio of the power tube is decreased, and there are problems such as decreased output voltage and increased ripple.

Moreover, the higher the switching frequency of the converter, the more pronounced the above-mentioned drawbacks.

Disclosure of Invention

In order to solve the above-mentioned problems, the present invention provides a method and an oscillator for generating complementary driving signals of a converter. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

The invention adopts the following technical scheme:

in some illustrative embodiments, the present invention provides a method for generating complementary drive signals for a converter, comprising: the driving voltage detection module detects the driving voltage of the power tube which is turned on currently, and when the driving voltage is detected to be reduced to a set value, the power tube which is turned on currently is judged to be turned off from an on state; and when the dead time is finished, the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width again so as to drive the other power tube to enter the on state.

Wherein the method for generating the complementary driving signal of the converter further comprises: the time sequence pulse width generating circuit module generates logic signals for driving time sequence pulse widths, and the two power tubes are driven in a crossing mode within the effective time of the pulse widths.

The dead time is generated by the driving voltage detection module or by a falling edge single-side delay circuit; the output of the driving voltage detection module and the falling edge single-side delay circuit is used as the input of the time sequence pulse width generation circuit module.

In some illustrative embodiments, the present invention also provides an oscillator for generating a complementary drive signal for a transducer, comprising: the time sequence pulse width generating circuit module and the frequency divider module further comprise: two driving voltage detection modules for respectively detecting the on/off states of the first power tube Q1 and the second power tube Q2; the input ports of the two driving voltage detection modules are respectively connected with the grid electrodes of the first power tube Q1 and the second power tube Q2, the output ports are respectively connected to the two input ends of the NAND gate, and the output end of the NAND gate is connected with the input end of the time sequence pulse width generation circuit module; the output end of the time sequence pulse width generation circuit module is connected with the input end of the frequency divider module, and the first output end and the second output end of the frequency divider module are respectively connected with the input end of the first driving circuit and the input end of the second driving circuit; the output end of the first driving circuit is connected with the grid electrode of the first power tube Q1, and the output end of the second driving circuit is connected with the grid electrode of the second power tube Q2;

the driving voltage detection module detects the driving voltage of the power tube which is turned on currently, and when the driving voltage is detected to be reduced to a set value, the power tube which is turned on currently is judged to be turned off from an on state; and when the dead time is finished, the time sequence pulse width generating circuit module generates a logic signal for driving the time sequence pulse width again so as to drive the other power tube to enter the on state.

Wherein, the driving voltage detection module includes: a common source amplifier and a schmitt trigger; NMOS tube M _test And pull-up resistor R _vdd Forming the common source amplifier, the NMOS tube M _test The gate of the NMOS transistor M is used as an input port of the driving voltage detection module _test The drain electrode of (C) is connected with a pull-up resistor R _vdd Is one end of the NMOS tube M _test The source electrode of the transistor is grounded; the pull-up resistor R _vdd The other end of (2) is input with voltage vdd; and the Schmitt trigger shapes the output voltage of the common source amplifier to output a logic level, and the output logic level is used as the output of the driving voltage detection module.

Wherein, the oscillator for producing the complementary driving signal of the converter further comprises: the output end of the NAND gate is connected with the input end of the falling edge single-side delay circuit, and the output end of the falling edge single-side delay circuit is connected with the input end of the time sequence pulse width generation circuit module.

Wherein, the drive voltage detection module still includes: capacitance Cdelay; one end of the capacitor Cdelay is connected with the input end of the Schmitt trigger, and the other end of the capacitor Cdelay is grounded.

Wherein, the oscillator for producing the complementary driving signal of the converter further comprises: the first P-type power tube P1, the second P-type power tube P2, the first NOT gate, the second NOT gate, the first additional driving unit and the second additional driving unit; the grid electrode of the first P-type power tube P1 is connected with the output end of the first additional driving unit, and the input end of the first additional driving unit is connected with the output end of the first NOT gate; the input end of the first NOT gate is connected with the second output end of the frequency divider module; the drain electrode of the first P-type power tube P1 is connected with the drain electrode of the second power tube Q2; the grid electrode of the second P-type power tube P2 is connected with the output end of the second additional driving unit, and the input end of the second additional driving unit is connected with the output end of the second NOT gate; the input end of the second NOT gate is connected with the first output end of the frequency divider module, and the drain electrode of the second P-type power tube P2 is connected with the drain electrode of the first power tube Q1; the source electrode of the first P-type power tube P1 and the source electrode of the second P-type power tube P2 are input with voltage vdd; the source electrode of the first power tube Q1 and the source electrode of the second power tube Q2 are grounded.

The invention has the beneficial effects that: the driving process of the power tube is used as a part of the cyclic oscillation of the oscillator, the dead time is generated after the power tube is detected and judged to be turned off, and the pulse width signal is generated after the next oscillation is carried out, and the whole process is closed-loop, so that the phenomenon of large dead time error caused by the driving delay of the power tube can be effectively avoided. The time interval for continuously driving the power tube twice is generated after the driving voltage detection module is indeed turned off, so that the time required by the driving circuit to turn off the power tube does not influence the dead time, and the driving process belongs to the whole closed loop of the oscillator. Therefore, in order to reduce the noise in the power switching process, even if the driving capability of the driving circuit is very large and the driving time is long, the common phenomenon is not caused, namely, the power tubes are continuously driven twice without time intervals or even overlapping, so that the overall performance of the oscillator is improved, the oscillator with a simpler structure can be provided, and the cost is reduced.

Drawings

FIG. 1 is a schematic circuit diagram of a prior art self-excited push-pull converter;

fig. 2 is a circuit diagram of an application of push-pull controller SN6501 proposed by TI company;

fig. 3 is a drain waveform of the MOS transistor of the push-pull transformer SN 6501;

FIG. 4 is an oscillator designed to generate complementary signals using a conventional scheme;

FIG. 5 is a signal timing waveform of an oscillator for generating complementary signals in a conventional manner;

FIG. 6 is a signal timing waveform of an oscillator for generating complementary signals in an abnormal situation using a conventional scheme;

fig. 7 is a schematic diagram of an oscillator of the present invention in embodiment 1;

FIG. 8 is a schematic diagram of a falling edge single-side delay circuit of the oscillator in embodiment 1;

FIG. 9 shows the input/output characteristics of the falling edge single-side delay circuit of the oscillator in embodiment 1;

FIG. 10 is a schematic diagram of the driving voltage detection module of the oscillator in embodiment 1;

FIG. 11 is a signal timing waveform of the oscillator of the present invention in embodiment 1;

fig. 12 is a schematic diagram of an oscillator of the present invention in embodiment 2;

FIG. 13 is a schematic diagram of the driving voltage detection module of the oscillator in embodiment 2;

fig. 14 is a schematic diagram of an oscillator of the present invention in embodiment 3;

FIG. 15 is a schematic diagram of the driving circuit and the additional driving unit of the present invention;

fig. 16 is a flow chart of a method of the present invention for generating complementary drive signals for a transducer.

Detailed Description

The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. The scope of embodiments of the invention encompasses the full ambit of the claims, as well as all available equivalents of the claims.

The oscillator provided by the invention generates a time sequence pulse width as a time sequence for driving the power tube, the driving circuit turns on the first power tube Q1 and the second power tube Q2 after the time sequence pulse width is sent out, the driving circuit 203 starts to turn off the power tube when the time sequence pulse width is ended, the power tube is not turned off immediately due to limited driving current provided by the driving circuit 203, at the moment, the driving voltage detection module 204 judges whether the power tube is turned off or not, the oscillator starts to count when the power tube is determined to be turned off, delays a dead time period, then the oscillator generates the time sequence pulse width again, and performs the next power driving, so that oscillation is formed continuously and repeatedly.

Example 1:

as shown in fig. 7, there is provided an oscillator for generating a complementary driving signal of an inverter, comprising: the driving circuit 203 comprises a time sequence pulse width generating circuit module 201, a frequency divider module 202, a driving voltage detecting module 204 and a falling edge single side delay circuit 205.

The timing pulse width generation circuit module 201 includes: oscillator capacitance C _OSC Charging reference current source Iref, comparator CMP, comparison voltage Vref, switch NM, NOT gate NOT2. Oscillator capacitance C _OSC When the voltage is smaller than the comparison voltage Vref, the output CLK of the comparator CMP is high, the switch NM is closed, and the oscillator capacitor C _OSC The capacitor is charged by the current Iref, and when the capacitor is charged to the comparison voltage Vref, the comparator CMP is turned over to enable the switch NM to be opened, so that the charge of the capacitor is discharged to be used as a starting point of the next charging.

The frequency divider module 202 includes: the D flip-flop DFF, NOT1, AND gate AND1 AND AND gate AND2 with falling edge action are used for separating the CLK signal input by the time sequence pulse width generating circuit module 201 into two complementary signals S AND

The number of driving circuits 203 is two, and the two complementary signals S are summed

Under the action of the voltage control circuit, the first power tube Q1 and the second power tube Q2 are respectively driven according to complementary time sequences, a certain driving current is provided for the first power tube Q1 and the second power tube Q2 according to time sequence pulse width, and the control terminal voltage of the first power tube Q1 and the control terminal voltage of the second power tube Q2 are raised or lowered so as to be turned on.

Falling edge single-side delayThe circuit 205 functions as a time interval, i.e., dead time, for generating two complementary drive signals. As shown in fig. 8 and 9, when ldi=0 is input, ldo =0; when the input ldi=1, ldo =1, but the Ldi changes from high to low with a delay time, the low is output, t in fig. 9 _HL1 ～t _HL2 The delay time; ldi is not delayed when changing from low to high, t in FIG. 9 _LH There is no delay in changing from low to high time.

The driving voltage detection modules 204 are two, and detect the on/off states of the first power transistor Q1 and the second power transistor Q2 respectively. The input ports of the two driving voltage detection modules 204 are respectively connected with the gates of the first power tube Q1 and the second power tube Q2, the output ports are respectively connected to two input ends of the NAND gate NAND, the output end of the NAND gate NAND is connected with the input end of the falling edge single-side delay circuit 205, and the output of the falling edge single-side delay circuit 205 serves as the input of the time sequence pulse width generation circuit module 201. When the gate voltages of the two power transistors are high and are turned on, a logic high level is output, and a low level is output, so that the two driving voltage detection modules 204 have a logic 'NOT' relationship on the input and output voltages.

As shown in fig. 10, the driving voltage detection module 204 includes: a common source amplifier and a schmitt trigger SMT; NMOS tube M _test And pull-up resistor R _vdd Form a common source amplifier, NMOS tube M _test Is used as the input port V of the driving voltage detection module 204 _GT The method comprises the steps of carrying out a first treatment on the surface of the The schmitt trigger SMT shapes the output voltage of the common source amplifier to output a desired logic level, and the output logic level is used as the output V of the driving voltage detection module 204 _FB . The characteristic of the schmitt trigger SMT is forward, and the output is low when a low level is input, whereas the output is high when a high level is input.

When the gate voltages of the two power transistors are in the NMOS transistor M _test When the threshold value of (2) is not far reduced, the NMOS tube M _test Gradually increasing the drain voltage until V _FB And outputting a high level to indicate that the power tube is completely turned off. With detecting NMOS tube M _test Is sensed by threshold voltage of (2)Whether the power tube is started or not is judged, and the high parameter matching performance is realized, so that the precision is high; and the detection speed is high, and the turn-off time of the power tube is tens to hundreds of nanoseconds, so that the circuit is simple and practical in structure.

As shown in fig. 7, the output logic V of the two-way driving voltage detection module 204 _FB2 And V _FB1 The NAND operation is used as the input of the falling edge single-side delay circuit 205, so that the time sequence pulse width generating circuit module 201, the frequency divider module 202, the driving circuit 203, the driving voltage detecting module 204 and the falling edge single-side delay circuit 205 form the whole closed loop oscillation, and complementary driving signals which are not easily affected by the driving delay and have dead time are generated.

As shown in fig. 11, after the signal S goes low, the input signal Ldi of the falling edge single-side delay circuit 205 does not immediately go low to generate dead time, but goes low as the gate voltage G2 of the second power transistor Q2 drops to the off voltage to generate dead time. Therefore, the dead time is generated when the feedback signal of the power tube is turned off, the method is a closed loop feedback process, if the driving delay is changed, the starting time of the dead time is also changed, but the width of the dead time is not influenced by the driving delay, so that the common phenomenon can be avoided, and the precision of the dead time can be ensured.

Example 2:

as shown in fig. 12 and 13, embodiment 2 differs from embodiment 1 in that embodiment 2 does not have a falling edge single-side delay circuit for generating dead time, but rather implements a delay generating function in the driving voltage detecting module 204, and specifically, the driving voltage detecting module 204 further includes: capacitor C _delay The method comprises the steps of carrying out a first treatment on the surface of the Capacitor C _delay One end is connected with the input end of the Schmitt trigger SMT, and the other end is grounded for generating the required dead time. The output ports of the two driving voltage detection modules are respectively connected to two input ends of the NAND gate, and the output of the NAND gate is used as a time sequence pulse width generation circuitAn input to module 201. When the gate voltage of the power tube is reduced to a certain extent, the NMOS tube M _test Also gradually turn off, then vdd passes through pull-up resistor R _vdd Gradually give capacitance C _delay When the upper threshold voltage of the schmitt trigger SMT is reached, the charging is performed, and the upper level is output after the upper threshold voltage is turned over, and the dead time is generated in the charging process.

The implementation circuit of the embodiment is simple, and the detection function and the dead time generation function of the grid electrode of the power tube are realized. Since the dead time from the turning off of the second power transistor Q2 to the turning on of the first power transistor Q1 and the dead time from the turning off of the first power transistor Q1 to the turning on of the second power transistor Q2 are generated by the two driving voltage detection modules 204, respectively, in practical applications, the two driving voltage detection modules 204 need to be matched on the integrated circuit layout, that is, the layout of the two driving voltage detection modules is close, so that good symmetry is obtained because the circuit parameters are substantially the same. The manner of embodiment 1 is that although the circuit is somewhat more, dead times for two different periods are generated by the same circuit, and thus are identical, and no special processing of the layout is required. Examples 1 and2 are two different ways to achieve highly symmetrical complementary driving.

Example 3:

as shown in fig. 14, in order to describe the principle of application of the oscillator in the present embodiment, fig. 14 shows a circuit composed of a primary winding N _P Secondary winding N _S1 Secondary winding N _S2 Transformer composed of rectifier tube CR1, rectifier tube CR2, secondary side rectifier circuit composed of output capacitor Co, R _L Is the load resistance.

The present embodiment is different from embodiment 1 in that it further includes: the first P-type power tube P1, the second P-type power tube P2 and two additional driving units 206, the two additional driving units 206 are used for driving the first P-type power tube P1 and the second P-type power tube P2 respectively.

The gate of the first P-type power transistor P1 and the output terminal V of one of the additional driving units 206 _O An input Vi end of the additional driving unit 206 is connected with an output end of the first NOT3, and an input end of the first NOT3 is connected with a dividerOne path of the output of the frequency device module 202 is connected, and the drain electrode of the first P-type power tube P1 is connected with the drain electrode of the second power tube Q2.

The gate of the second P-type power transistor P2 and the output terminal V of the other additional driving unit 206 _O The input end Vi of the additional driving unit 206 is connected to the output end of the second NOT gate NOT4, the input end of the second NOT gate NOT4 is connected to the other path of the output of the frequency divider module 202, and the drain of the second P-type power transistor P2 is connected to the drain of the first power transistor Q1.

Because the driving logic of the P-type power tube is opposite to that of the N-type power tube, a first NOT3 and a second NOT4 need to be added, the switch of the second P-type power tube P2 is controlled by a signal S, and the switch of the first P-type power tube P1 is controlled by

And (5) controlling. When s=1, the second power tube Q2 and the second P-type power tube P2 are turned on at the primary side of the transformer, so that current flows from the positive terminal Vdd of the input power supply to the primary winding N of the transformer through the second P-type power tube P2 _P And then flows out from the homonymous end of the main side winding and flows into the negative end of the input power supply through the second power tube Q2, so that an exciting current loop of the main side is formed. On the secondary side of the transformer, current flows from the secondary side winding N _S2 Flows out from the synonym end of (1), flows into the cathode through the anode of the rectifier diode CR2, and flows out to form an output capacitor Co and a load resistor R _L And supplying power to form a rectifying loop of the secondary side. It can be seen that under control of s=1, the energy of the input power source is transferred from the primary and secondary paths to the load side in isolation. From the symmetry of the topology it is easy to deduce when +.>

Simultaneously starting a first power tube Q1 and a first P-type power tube P1, and enabling current to flow in from the same-name end of a main side winding of the transformer to flow out from the different-name end to form another loop of the main side; current flowing from secondary winding N _S1 The same-name end of the capacitor flows out, and the output capacitor Co and the load end are supplied with power after passing through the rectifier diode CR1, so that the other rectifier circuit of the secondary side is formed. S=1, < >>

The alternating action forms complementary control to form the drive of the full bridge inverter.

The full-bridge converter has the greatest advantage that only one winding is needed on the primary side of the transformer, so that the design of the converter is simplified, and the size of the converter is reduced. But at the cost of a pair of P-type power transistors and providing complementary driving for them to achieve driving of the transformer windings from two opposite directions, two complementary current loops are formed. As with the push-pull converter, it is necessary to generate a highly symmetrical complementary drive signal with a certain dead time. If the time required for driving the N-type power tube and the P-type power tube is the same or has little difference, as long as the difference is substantially smaller than the dead time, the power N-type power tube, i.e. the gate voltages of the first power tube Q1 and the second power tube Q2, can be detected to form the closed-loop complementary signal oscillator of the invention, and of course, the gate voltages of the two P-type power tubes P1 and P2 can also be detected, or the gate voltages of the N-type power tubes Q1, Q2 and the P-type power tubes P1, P2 can be detected simultaneously to determine the turn-off state of the two power tubes.

As shown in fig. 15, the driving circuits 203 in embodiments 1 to 3 and the additional driving unit 206 in embodiment 3 have the same structure, and are implemented by using a set of not gate plus driving resistors with gradually amplified driving capability in CMOS integrated circuits, where the driving resistors are used to reduce switching noise of the power transistors, and of course, current-type driving is also commonly used to replace the driving resistors in practice.

As shown in fig. 7, 12, 14, 16, there is provided a method for generating complementary drive signals for a transducer, comprising:

s1: the time sequence pulse width generating circuit module generates a logic signal CLK for driving the time sequence pulse width.

Namely, the time sequence pulse width generating circuit module generates a driving time sequence pulse width, and the frequency divider module separates the CLK signal input by the time sequence pulse width generating circuit module into two paths of complementary signals S and S

The time sequence pulse width generating circuit module is enabled to drive the first power tube Q1 and the second power tube Q2 in a crossing way within the effective time of pulse width.

S2: the driving voltage detection module detects the driving voltage of the power tube which is turned on currently, and when the driving voltage is detected to be reduced to a set value, the power tube which is turned on currently is judged to be turned off from the on state.

The number of the driving voltage detection modules is two, and the first power tube Q1 and the second power tube Q2 are detected correspondingly.

S3: and after the current power tube is judged to be turned into the off state, generating dead time.

S4: when the dead time is completed, the time sequence pulse width generating circuit module generates logic signals for driving the time sequence pulse width again so as to drive the other power tube to enter an on state.

The steps S2 to S4 specifically take the pulse width effective time as a premise of selecting to turn on the first power tube Q1, when the driving voltage detection module corresponding to the first power tube Q1 detects that the driving voltage of the first power tube Q1 drops to a set value, it is determined that the first power tube Q1 is turned off from the on state, the dead time is generated after the detection and determination that the first power tube Q1 is turned off, and the next oscillation is performed to generate a pulse width signal, and then the second power tube Q2 is driven to enter the on state.

On the contrary, when the driving voltage detection module corresponding to the second power tube Q2 detects that the driving voltage of the second power tube Q2 drops to the set value, it is determined that the second power tube Q2 is turned from the on state to the off state, and after the detection and determination that the second power tube Q2 is turned off, dead time is generated and next oscillation is performed to generate a pulse width signal, and then the first power tube Q1 is driven to enter the on state.

As shown in fig. 11, the active level of the logic signal CLK is a high level, i.e., at the time of the high level, as a control signal for driving the first power transistor Q1 or the second power transistor Q2. Then separate out two paths of controlSystem signal S

S=1 and->

Alternately, the first power transistor Q1 and the second power transistor Q2 are alternately driven. After the first pulse width s=1 becomes 0, the driving voltage G2 of the second power tube Q2 is reduced from the high voltage until the detected driving voltage at time T2 is smaller than the set value, a dead time is generated from the time of starting to time, and the delay time at time T3 is ended, and the driving pulse width signal is generated again, namely clk=1 again, because the last time is s=1 for driving the second power tube Q2, the next time is selected to drive the first power tube Q1>

Finally, the power tube is continuously circulated to generate a complementary driving signal CLK and alternately drive the two paths of power tubes, so that the detection process of the driving voltage of the power tubes is included in the closed-loop oscillation process of the oscillator, and the adverse effect caused by the driving delay of the power tubes is effectively avoided.

The dead time is generated by a driving voltage detection module or by a falling edge single-side delay circuit; the output of the driving voltage detection module and the falling edge single-side delay circuit is used as the input of the time sequence pulse width generation circuit module. Therefore, the method for generating the complementary driving signal of the converter takes the driving process of the power tube as a part of the cyclic oscillation of the oscillator, and the dead time is generated after the power tube is detected and judged to be turned off and the pulse width signal is generated after the next oscillation is performed, so that the phenomenon of large dead time error caused by the delay of the driving of the power tube can be effectively avoided.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

Claims

1. An oscillator for generating a complementary drive signal for a transducer, comprising: the time sequence pulse width generation circuit module and the frequency divider module are characterized by further comprising: two driving voltage detection modules for respectively detecting the on/off states of the first power tube Q1 and the second power tube Q2; the input ports of the two driving voltage detection modules are respectively connected with the grid electrodes of the first power tube Q1 and the second power tube Q2, the output ports are respectively connected to the two input ends of the NAND gate, and the output end of the NAND gate is connected with the input end of the time sequence pulse width generation circuit module; the output end of the time sequence pulse width generation circuit module is connected with the input end of the frequency divider module, and the first output end and the second output end of the frequency divider module are respectively connected with the input end of the first driving circuit and the input end of the second driving circuit; the output end of the first driving circuit is connected with the grid electrode of the first power tube Q1, and the output end of the second driving circuit is connected with the grid electrode of the second power tube Q2;

2. An oscillator for generating a complementary drive signal for a transducer as claimed in claim 1,the driving voltage detection module includes: a common source amplifier and a schmitt trigger; NMOS tube M _test And pull-up resistor R _vdd Forming the common source amplifier, the NMOS tube M _test The gate of the NMOS transistor M is used as an input port of the driving voltage detection module _test The drain electrode of (C) is connected with a pull-up resistor R _vdd Is one end of the NMOS tube M _test The source electrode of the transistor is grounded; the pull-up resistor R _vdd The other end of (2) is input with voltage vdd; and the Schmitt trigger shapes the output voltage of the common source amplifier to output a logic level, and the output logic level is used as the output of the driving voltage detection module.

3. The oscillator for generating a complementary drive signal for a converter according to claim 1, further comprising: the output end of the NAND gate is connected with the input end of the falling edge single-side delay circuit, and the output end of the falling edge single-side delay circuit is connected with the input end of the time sequence pulse width generation circuit module.

4. The oscillator for generating a complementary drive signal for a converter according to claim 2, wherein the drive voltage detection module further comprises: capacitor C _delay The method comprises the steps of carrying out a first treatment on the surface of the The capacitor C _delay One end is connected with the input end of the Schmitt trigger, and the other end is grounded.

5. The oscillator for generating a complementary drive signal for a converter according to claim 1, further comprising: the first P-type power tube P1, the second P-type power tube P2, the first NOT gate, the second NOT gate, the first additional driving unit and the second additional driving unit; the grid electrode of the first P-type power tube P1 is connected with the output end of the first additional driving unit, and the input end of the first additional driving unit is connected with the output end of the first NOT gate; the input end of the first NOT gate is connected with the second output end of the frequency divider module; the drain electrode of the first P-type power tube P1 is connected with the drain electrode of the second power tube Q2; the grid electrode of the second P-type power tube P2 is connected with the output end of the second additional driving unit, and the input end of the second additional driving unit is connected with the output end of the second NOT gate; the input end of the second NOT gate is connected with the first output end of the frequency divider module, and the drain electrode of the second P-type power tube P2 is connected with the drain electrode of the first power tube Q1; the source electrode of the first P-type power tube P1 and the source electrode of the second P-type power tube P2 are input with voltage vdd; the source electrode of the first power tube Q1 and the source electrode of the second power tube Q2 are grounded.