CN111081787A - Wafer preparation method - Google Patents
Wafer preparation method Download PDFInfo
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- CN111081787A CN111081787A CN201911141891.1A CN201911141891A CN111081787A CN 111081787 A CN111081787 A CN 111081787A CN 201911141891 A CN201911141891 A CN 201911141891A CN 111081787 A CN111081787 A CN 111081787A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 42
- 238000003466 welding Methods 0.000 claims abstract description 28
- 238000001704 evaporation Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 20
- 230000008020 evaporation Effects 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 29
- 229910052709 silver Inorganic materials 0.000 claims description 29
- 239000004332 silver Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 20
- 239000007788 liquid Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 40
- 230000002159 abnormal effect Effects 0.000 description 31
- 230000008569 process Effects 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000012216 screening Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 238000009966 trimming Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910020658 PbSn Inorganic materials 0.000 description 1
- 101150071746 Pbsn gene Proteins 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a wafer preparation method, which comprises the following steps: after the preparation of the N-type substrate, the N-type epitaxial layer and the oxide layer subjected to hole etching is finished, sputtering, photoetching and etching the metal aluminum layer on a wafer; evaporating a welding layer on the cleaned wafer through a welding layer evaporation furnace; corroding the wafer coated with the welding layer by evaporation to remove the metal aluminum layer not covered by the welding layer; and photoetching and etching the welding layer, and finally thinning to form the front electrode.
Description
Technical Field
The invention relates to the technical field of electronic chips, in particular to a wafer preparation method.
Background
Because of the lower forward voltage drop of the Schottky diode, the faster switching speed is widely applied to the fields of communication power supplies, solar cell protection, frequency converters and the like; along with the miniaturization requirement of the power module, the silver surface Schottky diode product suitable for surface mount packaging is more and more widely applied.
The conventional silver-faced schottky diode front structure generally adopts a three-layer structure of Ti (titanium) -AL (aluminum) -Ti (titanium) -Ni (nickel) -Ag (silver) from bottom to top, wherein the uppermost layer of TiNiAg is a layer of three-layer metal, and the implementation steps are mainly as follows: the surface of the Schottky diode is cleaned, Schottky contact metal Ti is sputtered in vacuum, a second layer of metal AL is sputtered, the aluminum layer is mainly used as a buffer layer, the TiNiAg layer is evaporated after the aluminum layer is subjected to photoetching and etching, and finally, photoetching and etching are carried out again to form an electrode window.
The front Ag layer and the Ni layer of the Schottky diode formed by the process and the structure can be well fused with the solder PbSn, and the welded electrode and metal welding surface is terminated on the bottom metal AL. Because metallic aluminum and soldering tin material can not fuse, cause the electrode contact well after schottky diode's aluminium face directly links to each other with the encapsulation electrode easily, easy thermal fatigue, consequently the schottky diode surface need cover the Ag metal level of a layer weldable when carrying out miniaturized paster encapsulation.
When a second TiNiAg metal layer process is carried out after metal aluminum sputtering, photoetching and etching are carried out on the surface of the Schottky diode, an evaporation process is adopted, namely Ti (titanium) -Ni (nickel) -Ag (silver) layers are respectively evaporated in vacuum equipment, vacuum adsorption is adopted differently from the wafer fixing of sputtering equipment, a circular ring is fixedly sleeved at the edge of the surface of the wafer during evaporation, and a region covered by the circular ring of the wafer after evaporation is not covered with a silver layer, as shown in figure 1, a boundary line 1 is a side line of the whole wafer, a boundary line 2 is a boundary line of the silver layer which is not etched after evaporation, a region enclosed by the boundary line 2 is a normal region 4, and a region enclosed by the boundary line 1 and the boundary line 2 is an abnormal region 3 without a silver surface. Generally, a wafer is divided into rectangular grid points with the same size by using a scribing way, each grid is arranged in a crisscross symmetrical mode, and each grid is a chip. The chips are divided into three types according to different areas, as shown in fig. 2, the chips completely in the normal area 4 are normal chips 5, the chips completely in the abnormal area 3 are abnormal chips 6, and the abnormal chips 7 partially fall in the normal area 4 and partially fall in the abnormal area 3.
The normal chip 5 has a complete silver surface to ensure good packaging, and for the abnormal chips 6 and 7, the direct packaging can affect the reliability of the device without a complete silver surface structure. The abnormal chips 6 can be generally tested and screened by removing the edges by a distance of 2-3mm, but the structure of the abnormal chips 7 is troublesome as shown in fig. 3, firstly the abnormal chips 7 have complete aluminum layer structures 14 but abnormal silver layer structures 15, the CP test of the abnormal chips and the normal chips is normal, so that the abnormal chips cannot pass the test and screening, secondly the positions of the abnormal chips 7 on different wafers are different, mainly because the wafer is manually placed when the silver surface is evaporated, and deviation is generated, as shown in fig. 4, the left side 3A is wide, the right side 3B is narrow, but the abnormal chips are not limited to the right side of the boundary line 2, and the normal chips 8 in fig. 2 are changed into the abnormal chips under the standing state. Therefore, the abnormal chips to be screened can be screened out only by increasing the trimming distance, the increased trimming distance is positively correlated with the size of the chips, the yield loss is increased by 4-8 percent, and the screening yield loss is large and influences the market competitiveness of the products.
Disclosure of Invention
Embodiments of the present invention provide a wafer manufacturing method to solve the above problems in the prior art.
The embodiment of the invention provides a wafer preparation method, wherein the wafer is structurally characterized by comprising an N-type substrate at the bottommost layer, an N-type epitaxial layer covering the upper surface of the N-type substrate, an oxide layer covering the periphery of the upper surface of the N-type epitaxial layer, a metal aluminum layer covering the inner side of the oxide layer on the upper surface of the N-type epitaxial layer and the upper surface of the oxide layer, and a welding layer covering the upper surface of the metal aluminum layer and having the same size with the metal aluminum layer, and the method specifically comprises the following steps:
after the preparation of the N-type substrate, the N-type epitaxial layer and the oxide layer subjected to hole etching is finished, sputtering, photoetching and etching the metal aluminum layer on a wafer;
evaporating a welding layer on the cleaned wafer through a welding layer evaporation furnace;
corroding the wafer coated with the welding layer by evaporation to remove the metal aluminum layer not covered by the welding layer;
and photoetching and etching the welding layer, and finally thinning to form a back electrode.
By adopting the embodiment of the invention, the normal aluminum metal structure of the abnormal chip is removed by removing the edge aluminum layer structure, and the pressure-resistant structure of the chip is damaged, so that the abnormal chip can be removed by screening the wafer electrical parameters in the test process of the chip without increasing the trimming distance, the normal chip and the abnormal chip can be effectively distinguished on the premise of not obviously increasing the process cost, and the product yield is effectively improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic view of a wafer after evaporation of a silver layer according to the prior art;
FIG. 2 is a prior art layout of dies on different areas of a wafer;
FIG. 3 is a diagram of an abnormal chip structure in the prior art;
FIG. 4 is a diagram illustrating the effect of wafer placement bias in the prior art;
FIG. 5 is a cross-sectional view of a wafer according to an embodiment of the invention;
FIG. 6 is a diagram of an abnormal chip structure after the second metal layer is deposited and etched according to an embodiment of the present invention;
FIG. 7 is another abnormal chip structure diagram after the second metal layer is deposited and etched according to the embodiment of the present invention;
FIG. 8 is a schematic view of a complete wafer front side structure according to an embodiment of the present invention;
FIG. 9 is a flow chart of a method of wafer preparation according to an embodiment of the present invention;
FIG. 10 is a diagram of a structure after a first metal layer is deposited and etched in accordance with an embodiment of the present invention;
FIG. 11 is a schematic illustration of a manufacturing process practiced by the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
According to an embodiment of the present invention, a method for manufacturing a wafer is provided, which first describes a structure of a wafer in detail: fig. 5 is a schematic cross-sectional view of a wafer according to an embodiment of the invention, as shown in fig. 5, specifically including: the device comprises an N-type substrate 10 at the bottommost layer, an N-type epitaxial layer 12 covering the upper surface of the N-type substrate 10, an oxide layer 13 covering the periphery of the upper surface of the N-type epitaxial layer 12, a metal aluminum layer 14 covering the inner side of the oxide layer 13 on the upper surface of the N-type epitaxial layer and the upper surface of the oxide layer 13, and a welding layer 15 covering the upper surface of the metal aluminum layer 14 and having the same size as the metal aluminum layer 14.
It should be noted that the N-type epitaxial layer 12 is a low-doped N-type epitaxial layer. Further, the solder layer 15 is a metallic silver layer. The front electrode is formed after the metallic silver layer is processed.
Dividing the wafer into rectangular lattice points with the same size by using scribing channels, wherein each lattice is arranged in a # -shaped symmetrical mode, each lattice is each chip, and a normal chip structure 5 is shown in fig. 5, has a complete double-layer metal structure and a complete pressure-resistant metal field plate 16; as shown in fig. 6, the chip structure of the abnormal chip structure 7 located at the silver surface boundary has an incomplete or even removed voltage-resistant metal field plate 16 because the aluminum layer not covered by the silver layer is removed; the chip structure in which the abnormal chip 6 is completely located in the abnormal area 6 in fig. 1 is shown in fig. 7, and the chip is not covered by a metal layer. Finally, as shown in fig. 8, through the barrier effect of the second metal layer, the area of the first metal layer not covered by the second metal layer is selectively etched away, the area of the wafer 3C is not covered by the metal layer, and the area of the first metal aluminum and the area of the second metal silver are only covered by 4.
Fig. 9 is a flowchart of a wafer manufacturing method according to an embodiment of the invention, and as shown in fig. 5, the wafer manufacturing method according to the embodiment of the invention specifically includes:
step 901, after completing the preparation of the N-type substrate, the N-type epitaxial layer and the oxide layer subjected to the hole etching, sputtering, photoetching and etching the metal aluminum layer on a wafer;
step 902, evaporating a welding layer on the cleaned wafer through a welding layer evaporation furnace; specifically, the welding layer is a metal silver layer, and the welding layer evaporation furnace is a silver evaporation furnace.
Step 903, corroding the wafer coated with the welding layer by evaporation, and removing the metal aluminum layer not covered by the welding layer; in the embodiment of the invention, the wafer after the welding layer is evaporated can be corroded by aluminum corrosive liquid or a dry method. The aluminum corrosive liquid is non-reactive with the front metal silver layer or the selection ratio of the aluminum corrosive liquid is larger than a preset value.
And 904, photoetching and etching the welding layer, and finally thinning to form a front electrode.
The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 11 is a schematic diagram of a manufacturing process practiced by the present invention, as shown in FIG. 11, with the specific steps of:
1) after the previous process is finished on the wafer, a metallization process is started, aluminum layer sputtering, photoetching and etching are carried out on the first layer of metal, as shown in fig. 10, 10 is an N-type substrate, 12 is a low-doped N-type epitaxial layer, 13 is an oxide layer, the etching process of holes is finished, 14 is a first layer of metal aluminum layer formed after deposition and etching, and after the process of the layer, the chips on the surface of the wafer are consistent.
2) After cleaning, the wafer is placed in a silver evaporation furnace, a welding layer is evaporated, the area of a silver layer is smaller than that of an aluminum layer due to the limitation of a fixed ring of evaporation equipment, as shown in figure 1, a natural photoetching barrier layer is formed, the evaporated wafer is placed in an aluminum corrosive liquid to be corroded, and the aluminum corrosive liquid has a good selection ratio on the silver layer, so that metal aluminum in a region 3 in figure 1 can be removed.
3) And after removing the aluminum layer at the edge, photoetching and etching the silver layer, and finally thinning to form a back electrode. The normal chip structure 5 is shown in fig. 5, and has a complete double-layer metal structure and a complete voltage-resistant metal field plate 16; as shown in fig. 6, the chip structure of the abnormal chip structure 7 located at the silver surface boundary has an incomplete or even removed voltage-resistant metal field plate 16 because the aluminum layer not covered by the silver layer is removed; the chip structure in which the abnormal chip 6 is completely located in the abnormal area 6 in fig. 1 is shown in fig. 7, and the chip is not covered by a metal layer. Finally, as shown in fig. 8, through the barrier effect of the second metal layer, the area of the first metal layer not covered by the second metal layer is selectively etched away, the area of the wafer 3C is not covered by the metal layer, and the area of the first metal aluminum and the area of the second metal silver are only covered by 4.
By means of the technical scheme of the embodiment of the invention, the normal chip and the abnormal chip can be effectively distinguished on the premise of not obviously increasing the process cost, and the product yield is effectively improved. Through getting rid of marginal aluminium layer structure, got rid of the normal aluminium metal structure of unusual chip, destroyed the withstand voltage structure 16 of chip, the chip can get rid of unusual chip through the screening of wafer electrical parameter like this in the test procedure, and need not increase the distance of trimming, can effectively improve the product yield like this.
In the prior art, the edge is removed by 4-5 mm, yield loss is about 4-8%, abnormal chip particles can be screened out through wafer test by adopting the method for forming multilayer metal on the front surface of the Schottky diode, the abnormal chips can be removed only by removing the edge by 3mm, the yield of the chips is effectively improved, and the complexity of test screening is reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A wafer preparation method is characterized in that the wafer is structurally characterized by comprising an N-type substrate at the bottom, an N-type epitaxial layer covering the upper surface of the N-type substrate, an oxide layer covering the periphery of the upper surface of the N-type epitaxial layer, a metal aluminum layer covering the inner side of the oxide layer on the upper surface of the N-type epitaxial layer and the upper surface of the oxide layer, and a welding layer covering the upper surface of the metal aluminum layer and having the same size as the metal aluminum layer, wherein the method specifically comprises the following steps:
after the preparation of the N-type substrate, the N-type epitaxial layer and the oxide layer subjected to hole etching is finished, sputtering, photoetching and etching the metal aluminum layer on a wafer;
evaporating a welding layer on the cleaned wafer through a welding layer evaporation furnace;
corroding the wafer coated with the welding layer by evaporation to remove the metal aluminum layer not covered by the welding layer;
and photoetching and etching the welding layer, and finally thinning to form the front electrode.
2. The method of claim 1, wherein the solder layer is a metallic silver layer and the solder layer evaporator is a silver evaporator.
3. The method of claim 1, wherein etching the wafer after evaporation of the solder layer comprises:
and corroding the wafer with the evaporated welding layer by using an aluminum corrosive liquid or a dry method.
4. The method of claim 3, wherein the aluminum etchant is an etchant that is non-reactive with the front metallic silver layer or has a selectivity greater than a predetermined value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911141891.1A CN111081787B (en) | 2019-11-20 | 2019-11-20 | Wafer preparation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911141891.1A CN111081787B (en) | 2019-11-20 | 2019-11-20 | Wafer preparation method |
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| CN111081787A true CN111081787A (en) | 2020-04-28 |
| CN111081787B CN111081787B (en) | 2022-10-28 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS642357A (en) * | 1987-06-25 | 1989-01-06 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| CN102593048A (en) * | 2012-02-28 | 2012-07-18 | 上海华力微电子有限公司 | Treatment method of aluminum wire corrosion defects |
| CN105575762A (en) * | 2014-10-14 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating wafer surface defect in wet etching |
| CN105679756A (en) * | 2015-11-25 | 2016-06-15 | 杭州立昂微电子股份有限公司 | Terminal structure of semiconductor device top metal and manufacturing method thereof |
| CN206057797U (en) * | 2016-08-31 | 2017-03-29 | 上海微电子装备有限公司 | Exposure protection device and photoetching equipment |
-
2019
- 2019-11-20 CN CN201911141891.1A patent/CN111081787B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS642357A (en) * | 1987-06-25 | 1989-01-06 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| CN102593048A (en) * | 2012-02-28 | 2012-07-18 | 上海华力微电子有限公司 | Treatment method of aluminum wire corrosion defects |
| CN105575762A (en) * | 2014-10-14 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating wafer surface defect in wet etching |
| CN105679756A (en) * | 2015-11-25 | 2016-06-15 | 杭州立昂微电子股份有限公司 | Terminal structure of semiconductor device top metal and manufacturing method thereof |
| CN206057797U (en) * | 2016-08-31 | 2017-03-29 | 上海微电子装备有限公司 | Exposure protection device and photoetching equipment |
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