CN111081782A - Thin film transistor, preparation method thereof and display device - Google Patents
Thin film transistor, preparation method thereof and display device Download PDFInfo
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- CN111081782A CN111081782A CN201911217754.1A CN201911217754A CN111081782A CN 111081782 A CN111081782 A CN 111081782A CN 201911217754 A CN201911217754 A CN 201911217754A CN 111081782 A CN111081782 A CN 111081782A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a thin film transistor, a preparation method thereof and a display device, wherein the thin film transistor comprises a substrate, a first metal layer, a grid electrode insulating layer, a semiconductor layer, an etching barrier layer and a second metal layer, wherein the etching barrier layer at least comprises titanium oxide and metal of the second metal layer, and the titanium oxide in the etching barrier layer is used for isolating etching liquid to prevent the etching liquid from damaging the semiconductor in the semiconductor layer, so that the normal function of the thin film transistor is ensured; according to the preparation method, the material containing the metal titanium is used for forming the etching barrier layer, and the characteristic that the metal titanium is easy to oxidize to form titanium oxide is utilized, so that the etching barrier layer has good capability of isolating etching liquid, and the semiconductor layer is protected from being damaged.
Description
Technical Field
The invention relates to the technical field of display, in particular to a thin film transistor, a preparation method thereof and a display device.
Background
In the field of display technology, liquid crystal display devices and organic light emitting diode display devices are two mainstream display devices at present, and thin film transistors are widely used as drive control elements in the two display devices.
Common thin film transistors can be classified into amorphous silicon thin film transistors, low temperature polysilicon thin film transistors, and indium gallium zinc oxide thin film transistors according to the channel material of the thin film transistors, wherein the indium gallium zinc oxide thin film transistors are more favored by panel manufacturers because of higher electron mobility and on-state current. At the manufacturing end of the panel, a commonly used manufacturing process of the indium gallium zinc oxide thin film transistor is a Back Channel Etching (BCE) method, and the manufactured thin film transistor is a bottom gate thin film transistor. However, in the back channel etching process, when the source and drain of the thin film transistor are etched by using an acid etching solution, the etching solution may have a large influence on the indium gallium zinc oxide, which causes a reduction in the thickness of the channel region, thereby weakening the function of the thin film transistor or causing a loss of the function of the thin film transistor.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides the thin film transistor, the preparation method thereof and the display device using the thin film transistor.
The present invention provides a thin film transistor, including:
a substrate;
a first metal layer formed on the substrate;
the grid insulation layer is formed on the substrate and covers the first metal layer;
a semiconductor layer formed on the gate insulating layer;
the etching barrier layer is formed on the grid electrode insulating layer and covers the semiconductor layer; and
the second metal layer is formed on the etching barrier layer and comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively and correspondingly arranged at two opposite ends of the semiconductor layer;
wherein the etching barrier layer at least comprises titanium oxide and the metal of the second metal layer.
According to an embodiment of the present invention, the etch stop layer further comprises silicon.
According to an embodiment of the present invention, the etch stop layer includes an electrical connection layer and a semiconductor protection layer, wherein the electrical connection layer includes a metal in the second metal layer, so that the electrical connection layer forms ohmic contacts with a source and a drain of the second metal layer, respectively.
According to an embodiment of the present invention, the semiconductor layer is a metal oxide semiconductor, and the semiconductor protection layer covers the metal oxide semiconductor, wherein the semiconductor protection layer is titanium oxide.
According to an embodiment of the present invention, the thin film transistor further includes:
the passivation layer is formed on the substrate and covers the second metal layer and the etching barrier layer, and the passivation layer comprises a first through hole;
a planarization layer formed on the passivation layer, the planarization layer including a second via;
and the pixel electrode layer is formed on the flat layer and is electrically connected with the second metal layer through the first via hole and the second via hole.
The invention also provides a preparation method of the thin film transistor, which comprises the following steps:
forming a patterned first metal layer on a substrate;
forming a gate insulating layer covering the first metal layer on the substrate;
forming a patterned semiconductor layer on the gate insulating layer;
forming a transition layer containing metal titanium on the gate insulating layer to cover the semiconductor layer;
oxidizing the metal titanium in the transition layer to convert the transition layer into an etching barrier layer;
forming a patterned second metal layer on the etching barrier layer, wherein the second metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively and correspondingly arranged at two opposite ends of the semiconductor layer;
and carrying out heat treatment on the second metal layer to enable the metal in the second metal layer to diffuse into the etching barrier layer, so that an electric connection layer is formed in the etching barrier layer, and the electric connection layer and the second metal layer form ohmic contact.
According to an embodiment of the present invention, the transition layer containing metal titanium is formed of a titanium-silicon alloy.
According to an embodiment of the present invention, the method for manufacturing a thin film transistor further includes the steps of:
forming a passivation layer covering the second metal layer and the etching barrier layer;
forming a first via hole on the passivation layer to partially expose the second metal layer;
forming a planarization layer on the passivation layer to cover the passivation layer;
forming a second via hole on the planarization layer at a position corresponding to the first via hole, so that a part of the second metal layer is exposed through the first via hole and the second via hole;
and forming a pixel electrode layer on the flat layer, and electrically connecting the pixel electrode layer with the second metal layer through the first via hole and the second via hole.
According to an embodiment of the present invention, after the pixel electrode layer is formed, the pixel electrode layer is subjected to heat treatment;
and in the process of carrying out heat treatment on the pixel electrode layer, the metal in the second metal layer diffuses towards the etching barrier layer.
The present invention also provides a display device including:
the thin film transistor as described above; or
A thin film transistor produced by the method for producing a thin film transistor as described above.
The invention has the beneficial effects that: according to the thin film transistor, the preparation method thereof and the display device, the titanium-containing etching barrier layer is arranged on the semiconductor layer of the thin film transistor, the titanium oxide capable of isolating the etching liquid is formed in the etching barrier layer by utilizing the characteristic that metal titanium is easy to oxidize, and the semiconductor in the semiconductor layer can be prevented from being damaged by the etching liquid during the subsequent etching treatment operation, so that the normal function of the thin film transistor is ensured, and the yield and the stability of products are improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 2a is a schematic structural diagram formed after step S1 is completed in the preparation method provided by the embodiment of the invention;
fig. 2b is a schematic structural diagram formed after step S2 is completed in the preparation method provided by the embodiment of the invention;
fig. 2c is a schematic structural diagram formed after step S3 is completed in the preparation method provided by the embodiment of the invention;
fig. 2d is a schematic structural diagram formed after step S4 is completed in the preparation method according to the embodiment of the present invention;
fig. 2e is a schematic structural diagram formed after step S5 is completed in the preparation method provided by the embodiment of the invention;
fig. 2f is a schematic structural diagram formed after step S7 is completed in the preparation method according to the embodiment of the present invention;
fig. 3 is a schematic structural diagram of a thin film transistor manufactured by the manufacturing method according to the embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The embodiment of the invention provides a thin film transistor, wherein a titanium-containing etching barrier layer covering a semiconductor layer is arranged on the semiconductor layer of the thin film transistor, so that when a second metal layer is etched, the semiconductor in the semiconductor layer can be prevented from being damaged by etching liquid, the normal function of the thin film transistor is ensured, and the yield and the stability of products are improved.
As shown in fig. 1, which is a schematic structural diagram of a thin film transistor provided in an embodiment of the present invention, it should be understood that the thin film transistor may be applied to a display device that requires driving control using a thin film transistor, such as a liquid crystal display device, an organic light emitting diode display device, and the like, and in the display device, the thin film transistor may be integrally disposed in a layer structure of the display device without separately disposing the layer structure of the thin film transistor.
The thin film transistor has a layered structure including a substrate 10, a first metal layer 20, a gate insulating layer 30, a semiconductor layer 40, an etch stopper layer 50, and a second metal layer 60.
The first metal layer 20 is disposed on the substrate 10. The substrate 10 may be one of a glass substrate, a quartz substrate, a resin substrate, and the like; the material of the first metal layer 20 may be a conductive metal or metal alloy such as molybdenum, copper, or aluminum. In the preparation process of the first metal layer 20, a metal layer is deposited on the substrate 10 by a physical vapor deposition process, and then patterning is performed on the metal layer to form the first metal layer 20, wherein the patterning includes exposure, development and etching processes performed on the metal layer, and optionally, the thickness of the prepared first metal layer 20 is 2000-5500 angstroms.
The gate insulating layer 30 is formed on the substrate 10 and covers the first metal layer 20. The gate insulating layer 30 may be a silicon oxide layer, a silicon nitride layer, or a composite layer of the two, the gate insulating layer 30 is manufactured by plasma enhanced chemical vapor deposition, and the thickness of the finally formed gate insulating layer 30 covering the first metal layer 20 is 1500-4000 angstroms.
The semiconductor layer 40 is disposed on the gate insulating layer 30, and the material of the semiconductor layer may be a metal oxide semiconductor material such as indium gallium zinc oxide, and preferably indium gallium zinc oxide, because indium gallium zinc oxide has higher electron mobility and on-state current compared to other known metal oxide semiconductor materials, the manufactured thin film transistor has better electrical properties. In the preparation process of the semiconductor layer 40, a uniformly covered semiconductor film layer is formed on the gate insulating layer 30 by using a physical vapor deposition process, and then the semiconductor film layer is subjected to patterning treatment to form the semiconductor layer 40 in which semiconductor materials are regularly distributed, wherein the patterning treatment comprises the processes of exposing, developing and etching the semiconductor film layer, and the thickness of the finally formed semiconductor layer 40 is 300-2000 angstroms. In the preparation process of the semiconductor layer 40, a high temperature annealing process is required to repair defects of the semiconductor material in the semiconductor layer 40 to improve the performance of the semiconductor material.
The etch stopper layer 50 is formed on the gate insulating layer 30 and covers the semiconductor layer 40. The etch stop layer 50 includes an electrical connection layer 501 and a semiconductor protection layer 502, wherein the electrical connection layer 501 includes titanium oxide and the metal of the second metal layer 60, and the semiconductor protection layer 502 includes titanium oxide. Optionally, the etch stop layer 50 may further include silicon, and the thickness of the etch stop layer 50 is 50 to 500 angstroms. It should be noted that the raw material for preparing the etching blocking layer 50 is a material containing metal titanium, for example, the material may be a titanium-silicon alloy, where metal titanium accounts for 5% to 35% of the mass fraction of the titanium-silicon alloy, and the metal titanium may form titanium oxide in the air at normal temperature or by heating, which is a source of titanium oxide in the etching blocking layer 50, and in the etching process of the second metal layer 60, the titanium oxide may well isolate the etching solution, so that the semiconductor layer 40 is not affected by the etching solution; in addition, the electrical connection layer 501 further includes the metal of the second metal layer 60, which is formed by a subsequent thermal treatment process, the metal in the second metal layer 60 is heated to diffuse into the etching barrier layer 50, so as to form the electrical connection layer 501, and the electrical connection layer 501 forms ohmic contacts with the source and the drain of the second metal layer 60, respectively.
The second metal layer 60 is formed on the etch stop layer 50, and the material of the second metal layer 60 may be copper or aluminum. In the process of preparing the second metal layer 60, a metal film layer is formed by physical vapor deposition or droplet sputtering, and then the metal film layer is patterned to form two portions, namely, a source 601 and a drain 602 of the thin film transistor, which are respectively and correspondingly disposed at two opposite ends of the semiconductor layer 40. It should be noted that, a plurality of thin film transistors arranged in a side-by-side array may be included in the display device, and when the second metal layer of these thin film transistors is fabricated, a metal film layer covering all the thin film transistors may be formed first, and then a source electrode and a drain electrode corresponding to each thin film transistor may be formed through patterning. The patterning process comprises the operations of exposing, developing and etching the metal film layer. After the second metal layer 60 is prepared, the metal in the second metal layer 60 may diffuse to the etch stop layer 50 by a heat treatment operation in a subsequent process, so as to form the electrical connection layer 501.
Optionally, the thin film transistor further includes a passivation layer 70 disposed on the substrate 10 and covering the second metal layer 60 and the etching stop layer 50. The passivation layer 70 may be a silicon oxide layer or a silicon nitride layer or a composite layer of the two, and may have a thickness of 1500 to 4000 angstroms. The passivation layer 70 includes a first via 701, and the second metal layer 60 is exposed through the first via 701. In the preparation process of the passivation layer 70, a film layer covering the second metal layer 60 and the etching stop layer 50 is formed by a plasma enhanced chemical vapor deposition process, and then the first via hole 701 is formed at a position corresponding to the second metal layer 60 by a yellow light etching process, so that the second metal layer 60 is exposed.
Optionally, the thin film transistor further includes a planarization layer 80 disposed on the passivation layer 70, a second via hole 801 is disposed on the planarization layer 80, and the first via hole 701 and the second via hole 801 are located in a corresponding position and on a same vertical axis. The material of the planarization layer 80 may be an organic material or an inorganic material, and the planarization layer 80 is used to form a relatively flat upper surface of the thin film transistor, so as to dispose other components on the upper layer. The second via 801 may be formed by a photolithography process.
Optionally, the thin film transistor further includes a pixel electrode layer 90 disposed on the planarization layer 80, and the pixel electrode layer 90 is electrically connected to the second metal layer 60 through the first via hole 701 and the second via hole 801. The pixel electrode layer 90 may be made of a transparent conductive material such as indium tin oxide, and the preparation process includes a physical vapor deposition process and a patterning process, and the thickness of the pixel electrode layer 90 is 300 to 1000 angstroms. After the pixel electrode layer 90 is prepared, a high temperature annealing process is required to promote crystallization of the transparent conductive material therein, and during the high temperature annealing process, the metal of the second metal layer 60 is further diffused into the etch stop layer 50, so as to further promote formation of the electrical connection layer 501.
In summary, in the thin film transistor provided in the embodiment of the present invention, the etching barrier layer is disposed on the semiconductor layer, and the etching barrier layer includes titanium oxide capable of isolating the etching liquid, so that when the second metal layer is etched, the semiconductor in the semiconductor layer is prevented from being damaged by the etching liquid, thereby ensuring the normal function of the thin film transistor, and improving the yield and stability of the product.
In another embodiment of the present invention, as shown in fig. 2, a method for manufacturing a thin film transistor includes the following steps:
step s1. referring to fig. 2a, a patterned first metal layer 20 is formed on a substrate 10.
Specifically, the substrate 10 may be one of a glass substrate, a quartz substrate, a resin substrate, and the like. The method for preparing the first metal layer 20 on the substrate 10 is as follows:
first, a first metal film layer is deposited on the substrate 10 by a physical vapor deposition process or a metal droplet sputtering process, and the material of the first metal film layer may be molybdenum, copper, aluminum or other conductive metals or metal alloys.
Then, a photoresist layer is coated on the first metal film layer, and the first metal layer 20 is formed by a composition process of exposure, development and etching by using a mask plate. It should be understood that the first metal layer 20 serves as a gate electrode of the thin film transistor in the overall structure of the thin film transistor. The thickness of the finally formed first metal layer 20 is 2000 to 5500 angstroms.
Step s2. referring to fig. 2b, a gate insulating layer 30 is formed on the substrate 10 to cover the first metal layer 20.
Specifically, the gate insulating layer 30 may be a silicon oxide layer, a silicon nitride layer, or a composite layer of the two, the gate insulating layer 30 is manufactured by plasma enhanced chemical vapor deposition, and the thickness of the finally formed gate insulating layer 30 covering the first metal layer 20 is 1500 to 4000 angstroms.
Step s3. referring to fig. 2c, a patterned semiconductor layer 40 is formed on the gate insulating layer 30.
Specifically, the semiconductor layer 40 is made of a metal oxide semiconductor material such as indium gallium zinc oxide, and preferably indium gallium zinc oxide, because indium gallium zinc oxide has higher electron mobility and on-state current compared with other known metal oxide semiconductor materials, the thin film transistor manufactured by the method has better electrical properties. The preparation process of the semiconductor layer 40 specifically comprises the following steps:
first, a semiconductor film is formed on the gate insulating layer 30 by a physical vapor deposition process.
And then, carrying out high-temperature annealing treatment on the semiconductor film layer to repair the defects in the semiconductor film layer, wherein the annealing treatment temperature is 200-400 ℃, and the annealing time is 0.5-4 hours.
And finally, coating a photoresist layer on the semiconductor film layer, and forming the semiconductor layer 40 by adopting a mask plate through a composition process of exposure, development and etching, wherein the thickness of the prepared semiconductor layer 40 is 300-2000 angstroms.
Step s4. referring to fig. 2d, a transition layer 50a containing metal titanium is formed on the gate insulating layer 30 to cover the semiconductor layer 40.
Specifically, the transition layer 50a is a titanium-silicon alloy layer, wherein the mass fraction of metal titanium is 5% to 35%. The preparation process of the transition layer 50a is a vapor deposition process, and the thickness of the formed transition layer 50a is 50-500 angstroms.
Step s5, referring to fig. 2d and 2e, oxidizing the metal titanium in the transition layer 50a, so that the transition layer 50a is converted into the etching stop layer 50.
Specifically, since the metal titanium is an active metal and can be oxidized into titanium oxide at normal temperature in air, the method for oxidizing the metal titanium in step S5 may be natural oxidation in air or heating oxidation in air. In the process of converting the transition layer 50a into the etching stop layer 50, the metallic titanium in the transition layer 50a is completely converted into titanium oxide. The titanium oxide can well protect the semiconductor layer 40, and in a subsequent etching process, the titanium oxide in the etching barrier layer 50 can prevent an etching liquid from contacting the semiconductor layer 40, so that the semiconductor layer 40 is protected from the etching liquid.
Step s6, referring to fig. 2f, forming a patterned second metal layer 60 on the etching stop layer 50, where the second metal layer 60 includes two parts separated from each other and respectively disposed at two opposite ends of the semiconductor layer 40.
Specifically, the material of the second metal layer 60 may be copper or aluminum. The method for preparing the second metal layer 60 specifically comprises the following steps:
first, a second metal film layer is formed on the etching barrier layer 50 by physical vapor deposition or droplet sputtering.
Then, a photoresist layer is coated on the second metal film layer, and the second metal layer 60 is formed by a composition process of exposure, development and etching by using a mask plate. The second metal layer 60 includes two portions corresponding to two opposite ends of the semiconductor layer 40, which are the source 601 and the drain 602 of the tft. It should be noted that, in the display device, a plurality of thin film transistors may be included in a side-by-side array, and when the second metal layer of the thin film transistors is manufactured, the second metal film layer covering all the thin film transistors may be formed first, and then the source and the drain corresponding to each thin film transistor may be formed through a patterning process.
Step s7, referring to fig. 2f, performing a heat treatment on the second metal layer 60 to diffuse the metal in the second metal layer 60 into the etching stop layer 50, so as to form an electrical connection layer 501.
Specifically, the temperature for heat treatment of the second metal layer 60 is 200 ℃ to 400 ℃, and the heat treatment process is performed in a high-temperature annealing furnace. The metal in the second metal layer 60 diffuses into the etch stop layer 50 during the heat treatment process, so that a part of the region in the etch stop layer 50 is conductive, and the electrical connection layer 501 is formed, wherein the electrical connection layer 501 forms ohmic contacts with the source electrode 601 and the drain electrode 602 of the second metal layer 60 respectively.
Optionally, as shown in fig. 3, after step S7 is completed, the method for manufacturing a thin film transistor may further include the steps of:
step s301, forming a passivation layer 70 covering the second metal layer 60 and the etching stop layer 50. The passivation layer 70 may be a silicon oxide layer or a silicon nitride layer or a composite layer of the two, and the thickness of the thinnest region thereof may be 1500 to 4000 angstroms. The method of forming the passivation layer 70 is a plasma enhanced chemical vapor deposition method.
Step s302, forming a first via hole 701 on the passivation layer 70, so as to partially expose the second metal layer 60. The method for forming the first via hole 701 is a yellow light etching process, and specifically, a photoresist layer is coated on the passivation layer 70, and the first via hole 701 is formed by a mask plate through a composition process of exposure, development and etching.
Step s303, forming a flat layer 80 covering the passivation layer 70 on the passivation layer 70. The method of forming the planarization layer 80 may be a chemical vapor deposition process or a physical vapor deposition process. The material of the planarization layer 80 may be an organic material or an inorganic material, and the planarization layer 80 is used to form a relatively flat upper surface of the thin film transistor, so as to dispose other components on the upper layer.
Step s304, forming a second via hole 801 on the planarization layer 80 at a position corresponding to the first via hole 701, so that a portion of the second metal layer 60 is exposed through the first via hole 701 and the second via hole 801. The second via hole 801 may be formed by a yellow light etching process, specifically, a photoresist layer is coated on the flat layer 80, and the second via hole 801 is formed by a mask plate through a patterning process of exposure, development and etching.
Step s305, forming a pixel electrode layer 90 on the planarization layer 80, and electrically connecting the pixel electrode layer 90 to the second metal layer 60 through the first via hole 701 and the second via hole 801. The pixel electrode layer 90 may be made of a transparent conductive material such as indium tin oxide, and the preparation process includes a physical vapor deposition process and a patterning process, and specifically, a pixel electrode film layer is deposited on the planarization layer 80 by a physical vapor deposition method, then a photoresist layer is coated on the pixel electrode film layer, and the pixel electrode layer 90 is formed by a patterning process of exposure, development, and etching by using a mask plate. The thickness of the pixel electrode layer 90 is 300 to 1000 angstroms.
In addition, after the pixel electrode layer 90 is prepared, a high temperature annealing process is required to promote crystallization of the transparent conductive material therein, and during the high temperature annealing process, the metal of the second metal layer 60 is further diffused into the etching barrier layer 50, so as to promote further formation and perfection of the electrical connection layer 501.
In summary, the thin film transistor manufacturing method provided by the embodiment of the invention includes the step of forming the titanium-containing etching blocking layer on the semiconductor layer, and by utilizing the characteristic that the metal titanium is easy to oxidize, the titanium oxide capable of isolating the etching liquid is formed in the etching blocking layer, and during the subsequent etching treatment operation, the etching liquid can be prevented from damaging the semiconductor in the semiconductor layer, so that the manufactured thin film transistor is ensured to have normal functions, and the manufacturing yield of the thin film transistor is improved.
Another embodiment of the present invention further provides a display device, where the display device may be a liquid crystal display device or an organic light emitting diode display device, and the display device includes the thin film transistor provided in the embodiment of the present invention or includes the thin film transistor manufactured by the method for manufacturing the thin film transistor provided in the embodiment of the present invention, so that, in a manufacturing process of the display device, an etching barrier layer formed on a semiconductor layer may prevent an etching liquid from damaging the semiconductor layer, so as to improve reliability of the thin film transistor in the display device, and further improve yield and reliability of the display device.
It should be noted that, although the present invention has been described with reference to specific examples, the above-mentioned examples are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention.
Claims (10)
1. A thin film transistor, comprising:
a substrate;
a first metal layer formed on the substrate;
the grid insulation layer is formed on the substrate and covers the first metal layer;
a semiconductor layer formed on the gate insulating layer;
the etching barrier layer is formed on the grid electrode insulating layer and covers the semiconductor layer; and
the second metal layer is formed on the etching barrier layer and comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively and correspondingly arranged at two opposite ends of the semiconductor layer;
wherein the etching barrier layer at least comprises titanium oxide and the metal of the second metal layer.
2. The thin film transistor of claim 1, wherein the etch stop layer further comprises silicon.
3. The thin film transistor according to claim 1, wherein the etch stopper layer comprises an electrical connection layer and a semiconductor protection layer, wherein the electrical connection layer contains a metal in the second metal layer, so that the electrical connection layer forms ohmic contacts with a source electrode and a drain electrode of the second metal layer, respectively.
4. The thin film transistor according to claim 3, wherein the semiconductor layer is a metal oxide semiconductor, and wherein the semiconductor protective layer covers the metal oxide semiconductor, and wherein the semiconductor protective layer is titanium oxide.
5. The thin film transistor according to claim 1, further comprising:
the passivation layer is formed on the substrate and covers the second metal layer and the etching barrier layer, and the passivation layer comprises a first through hole;
a planarization layer formed on the passivation layer, the planarization layer including a second via;
and the pixel electrode layer is formed on the flat layer and is electrically connected with the second metal layer through the first via hole and the second via hole.
6. A preparation method of a thin film transistor is characterized by comprising the following steps:
forming a patterned first metal layer on a substrate;
forming a gate insulating layer covering the first metal layer on the substrate;
forming a patterned semiconductor layer on the gate insulating layer;
forming a transition layer containing metal titanium on the gate insulating layer to cover the semiconductor layer;
oxidizing the metal titanium in the transition layer to convert the transition layer into an etching barrier layer;
forming a patterned second metal layer on the etching barrier layer, wherein the second metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively and correspondingly arranged at two opposite ends of the semiconductor layer;
and carrying out heat treatment on the second metal layer to enable the metal in the second metal layer to diffuse into the etching barrier layer, so that an electric connection layer is formed in the etching barrier layer, and the electric connection layer and the second metal layer form ohmic contact.
7. The method of manufacturing a thin film transistor according to claim 6, wherein the transition layer containing metal titanium is formed of a titanium-silicon alloy.
8. The method for manufacturing a thin film transistor according to claim 6, further comprising the steps of:
forming a passivation layer covering the second metal layer and the etching barrier layer;
forming a first via hole on the passivation layer to partially expose the second metal layer;
forming a planarization layer on the passivation layer to cover the passivation layer;
forming a second via hole on the planarization layer at a position corresponding to the first via hole, so that a part of the second metal layer is exposed through the first via hole and the second via hole;
and forming a pixel electrode layer on the flat layer, and electrically connecting the pixel electrode layer with the second metal layer through the first via hole and the second via hole.
9. The method for manufacturing a thin film transistor according to claim 8, wherein after the pixel electrode layer is formed, the pixel electrode layer is subjected to heat treatment;
and in the process of carrying out heat treatment on the pixel electrode layer, the metal in the second metal layer diffuses towards the etching barrier layer.
10. A display device, comprising:
the thin film transistor of any one of claims 1-4; or
A thin film transistor produced by the method for producing a thin film transistor according to any one of claims 5 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201911217754.1A CN111081782A (en) | 2019-12-03 | 2019-12-03 | Thin film transistor, preparation method thereof and display device |
| PCT/CN2019/125519 WO2021109218A1 (en) | 2019-12-03 | 2019-12-16 | Thin film transistor and preparation method therefor, and display device |
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| CN201911217754.1A CN111081782A (en) | 2019-12-03 | 2019-12-03 | Thin film transistor, preparation method thereof and display device |
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| CN101908537A (en) * | 2009-06-03 | 2010-12-08 | 乐金显示有限公司 | Array substrate for display equipment and method of fabricating the same |
| US20110263079A1 (en) * | 2010-04-23 | 2011-10-27 | Applies Materials, Inc. | Interface protection layaer used in a thin film transistor structure |
| CN103715264A (en) * | 2013-12-23 | 2014-04-09 | 京东方科技集团股份有限公司 | Oxide film transistor, manufacturing method for oxide film transistor, array base board and display device |
| CN104576760A (en) * | 2015-02-02 | 2015-04-29 | 合肥鑫晟光电科技有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| CN105849878A (en) * | 2013-11-15 | 2016-08-10 | 希百特股份有限公司 | Motft with un-patterned etch-stop |
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2019
- 2019-12-03 CN CN201911217754.1A patent/CN111081782A/en active Pending
- 2019-12-16 WO PCT/CN2019/125519 patent/WO2021109218A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908537A (en) * | 2009-06-03 | 2010-12-08 | 乐金显示有限公司 | Array substrate for display equipment and method of fabricating the same |
| US20110263079A1 (en) * | 2010-04-23 | 2011-10-27 | Applies Materials, Inc. | Interface protection layaer used in a thin film transistor structure |
| CN105849878A (en) * | 2013-11-15 | 2016-08-10 | 希百特股份有限公司 | Motft with un-patterned etch-stop |
| CN103715264A (en) * | 2013-12-23 | 2014-04-09 | 京东方科技集团股份有限公司 | Oxide film transistor, manufacturing method for oxide film transistor, array base board and display device |
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