CN111064376B - Ten-switch three-phase three-level inverter and control method thereof - Google Patents
Ten-switch three-phase three-level inverter and control method thereof Download PDFInfo
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- CN111064376B CN111064376B CN202010004306.XA CN202010004306A CN111064376B CN 111064376 B CN111064376 B CN 111064376B CN 202010004306 A CN202010004306 A CN 202010004306A CN 111064376 B CN111064376 B CN 111064376B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
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Abstract
The invention provides a ten-switch three-phase three-level inverter and a control method thereof. A ten-switch three-phase three-level inverter comprising: the bridge comprises an A-phase bridge arm, a B-phase bridge arm, a C-phase bridge arm, an active clamping circuit, a first switch device and a fourth switch device; the A-phase bridge arm, the B-phase bridge arm, the C-phase bridge arm and the active clamping circuit are respectively composed of 2 switching devices. Compared with the related art, the invention can reduce the number of active switching devices and passive devices, reduce the volume of the inverter and reduce the production cost.
Description
Technical Field
The invention relates to the technical field of control, in particular to a ten-switch three-phase three-level inverter and a control method thereof.
Background
The diode-clamped three-level inverter in the related art generally employs the diode-clamped three-level topology shown in fig. 1 (black dots indicate connections). Referring to fig. 1, each leg employs a separate three-level cell, thus requiring up to 12 active switching devices and 6 passive clamping diodes as a whole, making the overall cost of the system relatively high. In high-voltage and high-power occasions, the cost of the active device accounts for the higher proportion of the total cost of the system, and the disadvantage is more prominent.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a ten-switch three-phase three-level inverter and a control method thereof, which are used for solving the technical problems in the related art.
In a first aspect, an embodiment of the present invention provides a ten-switch three-phase three-level inverter, an input side of which is connected to a dc power supply, where the dc power supply includes a voltage neutral point, and the ten-switch three-phase three-level inverter includes: the bridge comprises an A-phase bridge arm, a B-phase bridge arm, a C-phase bridge arm, an active clamping circuit, a first switch device and a fourth switch device;
the first end of the A-phase bridge arm, the first end of the B-phase bridge arm and the first end of the C-phase bridge arm are respectively connected with the anode of the direct-current power supply through the first switching device; the second end of the A-phase bridge arm, the second end of the B-phase bridge arm and the second end of the C-phase bridge arm are respectively connected with the negative electrode of the direct-current power supply through the fourth switching device; the third end of the A-phase bridge arm, the third end of the B-phase bridge arm and the third end of the C-phase bridge arm are used as output ends to output three-phase voltages;
a first end of the active clamping circuit is connected with the positive electrode of the direct current power supply through the first switching device; a second end of the active clamp circuit is connected with a negative electrode of the direct current power supply through the fourth switching device; and the third end of the active clamping circuit is used as an output end and is connected with the voltage neutral point of the direct-current power supply.
Optionally, the method further comprises: the first direct current voltage division capacitor and the second direct current voltage division capacitor;
the first direct current voltage division capacitor and the second direct current voltage division capacitor are connected in series and then connected in parallel at two ends of the direct current power supply, and the series connection point of the first direct current voltage division capacitor and the second direct current voltage division capacitor is a voltage neutral point of the direct current power supply.
Optionally, the a-phase bridge arm, the B-phase bridge arm, the C-phase bridge arm, and the active clamp circuit are respectively formed by 2 switching devices.
Optionally, the a-phase bridge arm includes a second switching device and a third switching device;
the first end of the second switching device is connected with the first end of the A-phase bridge arm, the second end of the second switching device and the first end of the third switching device are both connected with the third end of the A-phase bridge arm, and the second end of the third switching device is connected with the second end of the A-phase bridge arm;
a third end of the second switching device is used as a control end to receive an external control signal and is used for switching on or off the second switching device;
and the third end of the third switching device is used as a control end to receive an external control signal and is used for switching on or off the third switching device.
Optionally, the B-phase bridge arm includes a fifth switching device and a sixth switching device;
a first end of the fifth switching device is connected with a first end of the B-phase bridge arm, a second end of the fifth switching device and a first end of the sixth switching device are both connected with a third end of the B-phase bridge arm, and a second end of the sixth switching device is connected with a second end of the B-phase bridge arm;
a third end of the fifth switching device is used as a control end to receive an external control signal and is used for switching on or off the fifth switching device;
and a third end of the sixth switching device is used as a control end for receiving an external control signal and is used for switching on or off the sixth switching device.
Optionally, the C-phase bridge arm includes a seventh switching device and an eighth switching device;
a first end of the seventh switching device is connected with a first end of the C-phase bridge arm, a second end of the seventh switching device and a first end of the eighth switching device are both connected with a third end of the C-phase bridge arm, and a second end of the eighth switching device is connected with a second end of the C-phase bridge arm;
a third end of the seventh switching device is used as a control end to receive an external control signal and is used for switching on or off the seventh switching device;
and a third end of the eighth switching device is used as a control end for receiving an external control signal and is used for switching on or off the eighth switching device.
Optionally, the active clamping circuit comprises a ninth switching device and a tenth switching device;
a first end of the ninth switching device is connected with a first end of the active clamping circuit, a second end of the ninth switching device and a first end of the tenth switching device are both connected with a third end of the active clamping circuit, and a second end of the tenth switching device is connected with a second end of the active clamping circuit;
a third end of the ninth switching device is used as a control end to receive an external control signal and is used for switching on or off the ninth switching device;
and a third terminal of the tenth switching device is used as a control terminal to receive an external control signal and is used for switching on or off the tenth switching device.
In a second aspect, an embodiment of the present invention provides a ten-switch three-phase three-level inverter SVPWM modulation strategy, including:
acquiring a target large sector of a reference vector in preset six large sectors; two small sectors are preset in each large sector;
acquiring a target small sector of the reference vector in the target large sector;
according to the principle of volt-second balance, acquiring action time of each reference vector for synthesizing the reference vector based on the target small sector; the reference vector refers to three or four vectors adjacent to the reference vector within the target small sector;
and selecting a corresponding vector action sequence according to the target small sector of the reference vector in the target large sector, correspondingly distributing the action time of the reference vector to each vector corresponding to the vector action sequence according to the selected vector action sequence, and accordingly controlling the ten-switch three-phase three-level inverter to obtain three phases and three levels.
Optionally, the obtaining a target small sector of the reference vector in the target large sector includes:
obtaining the components V of the reference vector on the alpha axis and the beta axisα、Vβ；
Computing
If it is
Determining that the reference vector is located in an a sector of the target large sector; if it is
Determining that the reference vector is located in a B sector in the target large sector;
the sector a is a small sector close to the origin of the coordinate system where the axis α and the axis β are located, and the sector B is a small sector far from the origin of the coordinate system where the axis α and the axis β are located.
Optionally, the following principle is adopted for selecting the corresponding vector and the sequence thereof according to the acting time of each reference vector:
(1) ensuring that each switching device in the ten-switch three-phase three-level inverter is conducted at most once in one switching period;
(2) the small vector selected can realize the adjustment of the switching frequency level of the voltage division capacitance voltage.
In a third aspect, an embodiment of the present invention provides an SPWM modulation strategy for injecting a common-mode component into a ten-switch three-phase three-level inverter, including:
and the common-mode component is injected into the three-phase symmetrical modulation wave at the same time at each moment, so that three levels are prevented from appearing at the same time.
According to the technical scheme, the number of active switching devices and passive devices can be reduced, the size of the inverter is reduced, and the production cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a ten-switch three-phase three-level inverter topology in the related art.
Fig. 2 is a block diagram of a ten-switch three-phase three-level inverter according to an embodiment of the present invention.
Fig. 3 is a circuit diagram of a ten-switch three-phase three-level inverter according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of an equivalent circuit of an inverter in a zero vector 000 operating mode according to an embodiment of the present invention.
Fig. 5 is a schematic equivalent circuit diagram of an inverter in a small vector 100 operating mode according to an embodiment of the present invention.
Fig. 6 is a schematic equivalent circuit diagram of an inverter in a small vector 211 operating mode according to an embodiment of the present invention.
Fig. 7 is a schematic equivalent circuit diagram of an inverter in a large vector 200 operating mode according to an embodiment of the present invention.
Fig. 8 is a space vector diagram according to an embodiment of the present invention.
Fig. 9 is a flow chart of SVPWM modulation according to an embodiment of the present invention.
Fig. 10 shows an SPWM waveform injected with a common mode component according to an embodiment of the present invention.
Fig. 11 is a schematic structural diagram of a model for calculating a common-mode component according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, in this embodiment, in order to ensure normal operation of each switching device, a freewheeling diode needs to be connected in parallel to each switching device, the parallel direction of the freewheeling diode is related to the type of the switching device, and a technician may set the connection according to the type of the switching device, which is not limited herein. If not, the switching device may include a freewheeling diode by default, as will be noted in this embodiment. The terms "first" and "second" are used only for distinguishing between the respective devices, and do not limit the order of the respective devices.
The diode-clamped three-level inverter in the related art generally employs the diode-clamped three-level topology shown in fig. 1 (black dots indicate connections). Referring to fig. 1, each leg employs a separate three-level cell, thus requiring up to 12 active switching devices and 6 passive clamping diodes as a whole, making the overall cost of the system relatively high. In high-voltage and high-power occasions, the cost of the active device accounts for the higher proportion of the total cost of the system, and the disadvantage is more prominent.
The embodiment of the invention provides a ten-switch three-phase three-level inverter aiming at the problems in the related art, and the invention conception is that ten switches are utilized to construct the clamp type three-phase three-level inverter, so that the switching devices are saved, and the size and the cost of the inverter are favorably reduced. Meanwhile, an SVPWM (space vector pulse width modulation) strategy for the ten-switch three-phase three-level inverter is also provided to ensure the normal work of the inverter. In addition, an SPWM (sinusoidal pulse width modulation) strategy based on injection of common-mode voltage is provided, and normal operation of the inverter is also guaranteed.
Fig. 2 is a schematic circuit diagram of a ten-switch three-phase three-level inverter according to an embodiment of the present invention, and referring to fig. 2, the input side of the ten-switch three-phase three-level inverter is connected to a dc power source, and the dc power source includes a voltage neutral point. In one example, the method comprises the following steps: the first direct-current voltage-dividing capacitor C1 and the second direct-current voltage-dividing capacitor C2; the first direct-current voltage-dividing capacitor C1 and the second direct-current voltage-dividing capacitor C2 are connected in series and then connected in parallel to two ends of the direct-current power supply, and the first direct-current voltage-dividing capacitor C1 and the second direct-current voltage-dividing capacitor C2 both divide the voltage of the direct-current power supply, that is, a connection point when the first direct-current voltage-dividing capacitor C1 and the second direct-current voltage-dividing capacitor C2 are connected in series serves as a voltage neutral point of the direct-current power supply. The inverter further includes: the circuit comprises an A-phase bridge arm, a B-phase bridge arm, a C-phase bridge arm, an active clamping circuit, a first switching device T1 and a fourth switching device T4. Wherein the content of the first and second substances,
the first direct-current voltage-dividing capacitor C1 and the second direct-current voltage-dividing capacitor C2 are connected in series and then connected in parallel to two ends of the direct-current power supply, and the first direct-current voltage-dividing capacitor C1 and the second direct-current voltage-dividing capacitor C2 equally divide the voltage of the direct-current power supply;
the first end of the A-phase bridge arm, the first end of the B-phase bridge arm and the first end of the C-phase bridge arm are respectively connected with the anode of a direct-current power supply through a first switching device T1; the second end of the phase A bridge arm, the second end of the phase B bridge arm and the second end of the phase C bridge arm are respectively connected with the negative electrode of the direct-current power supply through a fourth switching device T4; the third end of the A-phase bridge arm, the third end of the B-phase bridge arm and the third end of the C-phase bridge arm are used as output ends to output three-phase voltages;
the first end of the active clamping circuit is connected with the anode of the direct current power supply through a first switching device T1; the second end of the active clamping circuit is connected with the negative electrode of the direct-current power supply through a fourth switching device T4; and the third end of the active clamping circuit is used as an output end and is connected with the voltage neutral point of the direct-current power supply.
Considering that the ten-switch three-phase three-level inverter in the present embodiment is constructed by using ten switch devices, in an embodiment, the a-phase bridge arm, the B-phase bridge arm, the C-phase bridge arm, and the active clamp circuit are respectively configured by using 2 switch devices.
Fig. 3 is a circuit schematic diagram of a ten-switch three-phase three-level inverter according to an embodiment of the present invention, and referring to fig. 3, the a-phase bridge arm includes a second switching device T2 and a third switching device T3;
a first end of a second switching device T2 is connected with a first end (the upper end of a dashed line frame) of the A-phase bridge arm, a second end of the second switching device T2 and a first end of a third switching device T3 are both connected with a third end (the right end of the dashed line frame) of the A-phase bridge arm, and a second end of the third switching device T3 is connected with a second end (the lower end of the dashed line frame) of the A-phase bridge arm;
a third terminal of the second switching device T2 is used as a control terminal for receiving an external control signal to turn on or off the second switching device T2;
the third terminal of the third switching device T3 is used as a control terminal for receiving an external control signal to turn on or off the third switching device T3.
With continued reference to fig. 3, the B-phase leg includes a fifth switching device T5 and a sixth switching device T6. A first end of a fifth switching device T5 is connected with a first end (the upper end of the dashed box) of the B-phase bridge arm, a second end of the fifth switching device T5 and a first end of a sixth switching device T6 are both connected with a third end (the right end of the dashed box) of the B-phase bridge arm, and a second end of the sixth switching device T6 is connected with a second end (the lower end of the dashed box) of the B-phase bridge arm;
a third terminal of the fifth switching device T5 is used as a control terminal for receiving an external control signal to turn on or off the fifth switching device T5;
the third terminal of the sixth switching device T6 is used as a control terminal for receiving an external control signal to turn on or off the sixth switching device.
With continued reference to fig. 3, the C-phase leg includes a seventh switching device T7 and an eighth switching device T8;
a first end of a seventh switching device T7 is connected with a first end of the C-phase arm (the upper end of the dashed line box), a second end of the seventh switching device T7 and a first end of an eighth switching device T8 are both connected with a third end of the C-phase arm (the right end of the dashed line box), and a second end of the eighth switching device T8 is connected with a second end of the C-phase arm (the lower end of the dashed line box);
a third terminal of the seventh switching device T7 is used as a control terminal for receiving an external control signal to turn on or off the seventh switching device T7;
the third terminal of the eighth switching device T8 is used as a control terminal for receiving an external control signal to turn on or off the eighth switching device T8.
With continued reference to fig. 3, the active clamp circuit includes a ninth switching device T9 and a tenth switching device T10.
A first end of a ninth switching device T9 is connected with a first end of the active clamp circuit (the upper end of the dashed box), a second end of the ninth switching device T9 and a first end of a tenth switching device T10 are both connected with a third end of the active clamp circuit (the left end of the dashed box), and a second end of the tenth switching device T10 is connected with a second end of the active clamp circuit (the lower end of the dashed box);
a third terminal of the ninth switching device T9 is used as a control terminal for receiving an external control signal to turn on or off the ninth switching device T9;
the third terminal of the tenth switching device T10 serves as a control terminal for receiving an external control signal to turn on or off the tenth switching device T10.
Therefore, in the embodiment, the ten-switch three-phase three-level inverter topology structure is composed of two direct-current voltage-dividing capacitors C1And C2And ten active power switches T1～T10And (4) forming. VdcFor a DC power supply, two capacitors C1And C2Are equally divided into Vdc(C1＝C2)，ia、ib、icRespectively, three-phase output currents.
In this embodiment, two capacitors C are used1And C2Is the DC supply voltageThree-phase output current (i) with the middle point as a reference pointa、ib、ic) Taking the outgoing bridge arm as positive, each phase of bridge arm can respectively output three levels V dc2, 0 and-Vdc/2. However, since the three-phase bridge arm shares the switching device T1、T4、T9And T10That is, there is a certain coupling relationship between three-phase levels, which will result in A, B, C three-phase bridge arm not outputting V simultaneouslydc2, 0 and-VdcAnd/2. E.g. T1、T2、T4And T6When conducting, the A phase outputs VdcA/2 level, B phase output-VdcA/2 level, when T is not7And T8Any one of the switching tubes is conducted, no current flows through the C-phase bridge arm, and therefore zero level output cannot be achieved by the C-phase bridge arm. From the perspective of three-phase system space vectors, the topology can realize the output of all zero vectors, small vectors and large vectors, but cannot realize the output of medium vectors. In the three-phase three-level inverter, the zero vector means that the modular length of the vector is 0, and 1 zero vector is shared; a small vector is a vector having a modulo length of VdcA total of 6 small vectors (each small vector contains two switch states); medium vector means that the vector has a modulo length of
There are 6 medium vectors; large vector means that the modular length of the vector is 2VdcAnd/3, there are 6 large vectors.
Considering that the conventional three-phase three-level inverter has 27 working modes corresponding to 19 voltage vectors, namely 1 zero vector, 6 small vectors, 6 medium vectors and 6 large vectors, the ten-switch three-phase three-level inverter provided in the embodiment of the present invention cannot output a medium vector, so that after the working modes corresponding to the 6 medium vectors in the conventional topology are removed, 21 working modes are left in total, and 13 voltage vectors, namely 1 zero vector, 6 small vectors and 6 large vectors are corresponding to the remaining working modes. In modal analysis, three levels V are used for convenience of expression dc2, 0 and-VdcAnd/2 is represented by 2, 1 and 0, respectively. The switching conditions of the devices of the respective modes are shown in Table 1, whereinZero vector 111a～111iConsidering a mode 111, a number 0 indicates that the corresponding switching device is turned off, and a number 1 indicates that the corresponding switching device is turned on.
TABLE 1 Ten-switch three-phase three-level inverter working mode table
The operation of the ten-switch three-phase three-level inverter shown in fig. 3 is described below with reference to three types of operation modes shown in table 1 as an example:
fig. 4 is a schematic diagram of an equivalent circuit of an inverter in a zero vector 000 operating mode according to an embodiment of the present invention. Referring to fig. 4, in the zero-vector operation mode, the first switching device T1, the second switching device T2, the fifth switching device T5, the seventh switching device T7 and the tenth switching device T10 are turned off, the third switching device T3, the fourth switching device T4, the sixth switching device T6, the eighth switching device T8 and the ninth switching device T9 are turned on, and the a-phase output of the inverter is at 0 level (i.e., voltage-V) in this modedc/2), inverter B phase outputs 0 level (i.e., voltage-V)dc/2), inverter C phase outputs 0 level (i.e., voltage-V)dc/2)。
Fig. 5 is a schematic equivalent circuit diagram of an inverter in a small vector 100 operating mode according to an embodiment of the present invention. Referring to fig. 5, in the small vector 100 operation mode, the first switching device T1, the third switching device T3, the fifth switching device T5, the seventh switching device T7 and the tenth switching device T10 are turned off, the second switching device T2, the fourth switching device T4, the sixth switching device T6, the eighth switching device T8 and the ninth switching device T9 are turned on, and in this mode, the a-phase of the inverter outputs a 1 level (i.e., voltage 0) and the B-phase of the inverter outputs a 0 level (i.e., voltage-V)dc/2), inverter C phase outputs 0 level (i.e., voltage-V)dc/2)
FIG. 6 provides an embodiment of the present inventionThe inverter of (2) is in an equivalent circuit schematic diagram under the small vector 211 working mode. Referring to fig. 6, in the small vector 211 operation mode, the third switching device T3, the fourth switching device T4, the fifth switching device T5, the seventh switching device T7 and the ninth switching device T9 are turned off, and the first switching device T1, the second switching device T2, the sixth switching device T6, the eighth switching device T8 and the tenth switching device T10 are turned on, so that the inverter a outputs 2 levels (i.e., voltage + V) in this modedc/2), inverter phase B outputs 1 level (i.e., voltage 0), inverter phase C outputs 1 level (i.e., voltage 0)
Since the small vector 211 corresponding to the operation mode of fig. 6 is a redundant vector of the small vector 100 corresponding to the operation mode of fig. 5, the operation mode of the small vector will be described with reference to fig. 5 and 6, respectively.
Fig. 7 is a schematic equivalent circuit diagram of an inverter in a large vector 200 operating mode according to an embodiment of the present invention. Referring to fig. 7, in the small vector 200 operation mode, the third, fifth, and tenth switching devices T3, T5, T7, T9, and T10 are turned off, and the tenth, second, and sixth switching devices T1, T2, T4, T6, and T8 are turned on, so that the inverter a outputs 2 levels (i.e., voltage + V) in this modedc/2), inverter B phase outputs 0 level (i.e., voltage-V)dc/2), inverter C phase outputs 0 level (i.e., voltage-V)dc/2)。
Based on the mode table, the invention provides an SVPWM modulation strategy suitable for the ten-switch three-phase three-level inverter, the output voltage vector of which is shown in FIG. 8, and the difference from the output vector of the traditional three-phase three-level inverter is that the topology only has a zero vector, a small vector and a large vector but does not have a medium vector.
In the present invention, the SVPWM modulation strategy, the modulation flow of which is shown in fig. 9, comprises the following main steps:
(1) the spatial vector diagram shown in fig. 8 is divided into six large sectors (sectors I-VI), each occupying an angle of 60 degrees. In order to reduce harmonic distortion as much as possible, the reference vector is composed of three or four vectors nearest thereto, and thus each large sector can be divided into two small sectors a and B again.
The judgment principle of the large sector and the small sector is similar, and the judgment of the large sector is consistent with that of the traditional SVPWM large sector, so that the judgment of the large sector is not repeated herein. Small sector determination is given by the example of sector I, Vα、VβAre respectively a reference vector VrefThe α axis and β axis components of (a) are determined as follows:
firstly, when
Time, reference vector VrefFalls in sector a;
② when
Time, reference vector VrefFalling in sector B.
The sector a is a small sector close to the origin of the coordinate system where the axis α and the axis β are located, and the sector B is a small sector far from the origin of the coordinate system where the axis α and the axis β are located.
It should be noted that the determination manner of the reference vector in each small sector of the other large sectors is the same, and is not described herein again.
(2) The SVPWM waveform is generated by adopting a 7-segment mode, and the following principles are considered when a vector action sequence is selected:
firstly, ensuring that each switching tube is conducted at most once in one switching period;
secondly, the adjustment of the switching frequency level of the voltage dividing capacitor voltage is realized through the reasonable selection of the small vectors, namely the voltage dividing capacitor is charged and discharged in the switching frequency level, so that the voltage dividing capacitor voltage is stable, the system can work stably, and the quality of an output waveform is ensured. Taking the large sector I as an example, in the small sector A, the voltage division capacitance voltage is subjected to switching frequency level adjustment by selecting three vectors 110, 100 and 211; the capacitor voltage is balanced within small sector B by choosing four vectors of 100, 110, 221 and 211.
The final selected 7-segment vector order of action is shown in table 2, according to the above principles.
TABLE 2 Ten-switch three-phase three-level inverter seven-segment type SVPWM vector action sequence table
It can be seen that the vector order table selected in conjunction with table 2 corresponds to fig. 8 to see that the modulation is full. Because the operation range of the traditional diode-clamped three-phase three-level inverter is within the hexagonal inscribed circle, the inverter topology provided by the invention can also operate within the hexagonal inscribed circle shown in fig. 8 under the vector state sequence of table 2, and therefore the modulation degree of the inverter topology is the same as that of the traditional diode-clamped three-phase three-level inverter adopting SVPWM modulation, and the effect of full modulation is achieved.
Considering that the above-mentioned ten-switch three-phase three-level inverter cannot output three levels simultaneously, the present invention also proposes a corresponding SPWM modulation strategy, see fig. 10, for a three-phase symmetric modulation wave u at each instanta、ubAnd ucWhile injecting a common mode component, wherein the magnitude of the common mode component is realized by the model shown in fig. 11. The functions of each part of FIG. 11 are: u. ofa、ubAnd ucGenerating a three-phase symmetric modulation wave; the min module takes u input from the left sidea、ub、ucAnd outputting the minimum value; the max module takes the u of its left inputa、ub、ucAnd outputting the maximum value; -1 or
The module multiplies its left input by the intra-module value-1 or
Then outputting; the six + + modules sum the inputs and then output the sum;
the judgment module on the left side of the module judges the value input by the second input end on the left side of the module, and if the value is more than 0, the output is taken from the first input end on the left sideOtherwise, the output takes the value of the third input end. Modulating the wave u with three phasesa>0>ub>ucFor example, referring to fig. 11, a value of- (u) is injected into a three-phase symmetric modulation wave at the same timea+ub) The common mode component of/2, resulting in a three-phase symmetric modulated wave in FIG. 10, when modulated wave ua *And ub *The switching operation is performed at the same time, so that the simultaneous occurrence of three levels can be avoided.
Therefore, in the embodiment of the invention, the ten-switch three-phase three-level inverter is realized by adopting ten switches, the output voltage and current waveform quality consistent with the traditional three-phase three-level topological structure can be realized, two active switch devices and six passive devices can be reduced, the system volume can be obviously reduced, and the cost can be reduced. In addition, the modulation strategy provided by the invention can ensure the utilization rate of direct-current voltage and has universality, and is suitable for a coupling type three-phase three-level inverter topological structure without medium vectors.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (5)
1. A ten-switch three-phase three-level inverter having an input side connected to a dc power source, the dc power source including a voltage neutral point, comprising: the bridge comprises an A-phase bridge arm, a B-phase bridge arm, a C-phase bridge arm, an active clamping circuit, a first switch device and a fourth switch device;
the first end of the A-phase bridge arm, the first end of the B-phase bridge arm and the first end of the C-phase bridge arm are respectively connected with the anode of the direct-current power supply through the first switching device; the second end of the A-phase bridge arm, the second end of the B-phase bridge arm and the second end of the C-phase bridge arm are respectively connected with the negative electrode of the direct-current power supply through the fourth switching device; the third end of the A-phase bridge arm, the third end of the B-phase bridge arm and the third end of the C-phase bridge arm are used as output ends to output three-phase voltages;
a first end of the active clamping circuit is connected with the positive electrode of the direct current power supply through the first switching device; a second end of the active clamp circuit is connected with a negative electrode of the direct current power supply through the fourth switching device; the third end of the active clamping circuit is used as an output end and is connected with the voltage neutral point of the direct-current power supply;
the A-phase bridge arm, the B-phase bridge arm, the C-phase bridge arm and the active clamping circuit are respectively composed of 2 switching devices;
the A-phase bridge arm comprises a second switching device and a third switching device;
the first end of the second switching device is connected with the first end of the A-phase bridge arm, the second end of the second switching device and the first end of the third switching device are both connected with the third end of the A-phase bridge arm, and the second end of the third switching device is connected with the second end of the A-phase bridge arm;
a third end of the second switching device is used as a control end to receive an external control signal and is used for switching on or off the second switching device;
a third end of the third switching device is used as a control end to receive an external control signal and is used for switching on or off the third switching device;
the B-phase bridge arm comprises a fifth switching device and a sixth switching device;
a first end of the fifth switching device is connected with a first end of the B-phase bridge arm, a second end of the fifth switching device and a first end of the sixth switching device are both connected with a third end of the B-phase bridge arm, and a second end of the sixth switching device is connected with a second end of the B-phase bridge arm;
a third end of the fifth switching device is used as a control end to receive an external control signal and is used for switching on or off the fifth switching device;
a third end of the sixth switching device is used as a control end to receive an external control signal and is used for switching on or off the sixth switching device;
the C-phase bridge arm comprises a seventh switching device and an eighth switching device;
a first end of the seventh switching device is connected with a first end of the C-phase bridge arm, a second end of the seventh switching device and a first end of the eighth switching device are both connected with a third end of the C-phase bridge arm, and a second end of the eighth switching device is connected with a second end of the C-phase bridge arm;
a third end of the seventh switching device is used as a control end to receive an external control signal and is used for switching on or off the seventh switching device;
a third end of the eighth switching device is used as a control end to receive an external control signal and is used for switching on or off the eighth switching device;
the active clamping circuit comprises a ninth switching device and a tenth switching device;
the first end of the ninth switching device is connected with the first end of the active clamping circuit, the second end of the ninth switching device and the first end of the tenth switching device are both connected with the third end of the active clamping circuit, and the second end of the tenth switching device is connected with the second end of the active clamping circuit.
2. The ten-switch three-phase three-level inverter according to claim 1, further comprising: the first direct current voltage division capacitor and the second direct current voltage division capacitor;
the first direct current voltage division capacitor and the second direct current voltage division capacitor are connected in series and then connected in parallel at two ends of the direct current power supply, and the series connection point of the first direct current voltage division capacitor and the second direct current voltage division capacitor is a voltage neutral point of the direct current power supply.
3. The ten-switch three-phase three-level inverter according to any one of claims 1 to 2,
a third end of the ninth switching device is used as a control end to receive an external control signal and is used for switching on or off the ninth switching device;
and a third terminal of the tenth switching device is used as a control terminal to receive an external control signal and is used for switching on or off the tenth switching device.
4. An SVPWM modulation strategy of a ten-switch three-phase three-level inverter according to any of claims 1 to 3, comprising:
acquiring a target large sector of a reference vector in preset six large sectors; two small sectors are preset in each large sector;
acquiring a target small sector of the reference vector in the target large sector;
according to the principle of volt-second balance, acquiring action time of each reference vector for synthesizing the reference vector based on the target small sector; the reference vector refers to three or four vectors adjacent to the reference vector within the target small sector;
selecting a corresponding vector action sequence according to a target small sector of the reference vector in the target large sector, correspondingly distributing action time of a reference vector to each vector corresponding to the vector action sequence according to the selected vector action sequence, and accordingly controlling the ten-switch three-phase three-level inverter to obtain three phases and three levels;
the obtaining a target small sector of the reference vector in the target large sector includes:
obtaining the components V of the reference vector on the alpha axis and the beta axisα、Vβ；
Computing
If it is
Then determine what isThe reference vector is positioned in an A sector in the target large sector; if it is
Determining that the reference vector is located in a B sector in the target large sector; wherein, VdcIs a direct current power supply;
the sector A is a small sector close to the origin of a coordinate system where the alpha axis and the beta axis are located, and the sector B is a small sector far away from the origin of the coordinate system where the alpha axis and the beta axis are located;
the direct-current power supply of the ten-switch three-phase three-level inverter is connected with two voltage division capacitors connected in series in parallel; and selecting corresponding vectors and the sequence thereof according to the action time of each reference vector by adopting the following principles:
(1) ensuring that each switching device in the ten-switch three-phase three-level inverter is conducted at most once in one switching period;
(2) the small vector selected can realize the adjustment of the switching frequency level of the voltage division capacitance voltage.
5. An SPWM modulation strategy for injecting common mode components for a ten-switch three-phase three-level inverter according to any of claims 1-3, comprising:
injecting common-mode components into the three-phase symmetrical modulation waves at each moment, so as to avoid three levels from appearing at the same time; the three-phase symmetrical modulation wave sequentially comprises the following steps from small to large: u. ofmin，-(umin+umax)，umax(ii) a If- (u)min+umax) > 0, the injected common mode component is: - (u)min+ (-(umin+umax) ))/2, i.e., u)max2; if- (u)min+umax) 0 or less, the injected common mode component is: - (u)max+(-(umin+umax) ))/2, i.e., u)min/2。
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