CN111052068A - Memory array accessibility - Google Patents

Abstract

Apparatus and methods for memory array accessibility may include an apparatus having an array of memory cells. The array may include a first portion accessible by a controller of the array and inaccessible to a device external to the apparatus. The array may include a second portion accessible to the device external to the apparatus. The array may include a number of registers that store row addresses that indicate which portion of the array is the first portion. The apparatus may include the controller configured to access the number of registers to allow the device external to the apparatus to access the second portion based on the stored row address.

Description

Memory array accessibility

Technical Field

The present disclosure relates generally to semiconductor memory devices and methods, and more particularly to devices and methods related to memory array accessibility.

Background

Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory may provide persistent data by retaining stored data when not powered, and may include NAND flash memory, NOR flash memory, and resistance variable memory, such as Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), such as spin torque transfer random access memory (sttram), among others.

Electronic systems typically include a number of processing resources (e.g., one or more processors) that can retrieve and execute instructions and store the results of the executed instructions in an appropriate location. A processor may include a number of functional units (e.g., referred to herein as functional unit circuits), such as Arithmetic Logic Unit (ALU) circuits, Floating Point Unit (FPU) circuits, AND/OR combinational logic blocks, that may execute instructions to perform logical operations (e.g., AND, OR, NOT, NAND, NOR, AND XOR logical operations) on data (e.g., one OR more operands).

Several components in an electronic system may be involved in providing instructions to functional unit circuitry for execution. The instructions may be generated, for example, by a processing resource such as a controller and/or a host processor. Data (e.g., operands on which an instruction is to be executed to perform a logical operation) can be stored in a memory array, which can be accessed by the functional unit circuitry. Instructions and/or data may be retrieved from the memory array and sorted and/or buffered before the functional unit circuitry begins executing instructions on the data. Furthermore, since different types of operations may be performed in one or more clock cycles via the functional unit circuitry, intermediate results and/or data of the operations may also be ordered and/or buffered.

In many cases, the processing resources (e.g., the processor and/or associated functional unit circuitry) may be external to the memory array and data may be accessed (e.g., via a bus between the processing resources and the memory array) to execute instructions. Data may be transferred from the memory array to an external processing resource via a bus. Data being transferred between the memory array and the external processing resource may be detected en route (e.g., by "snooping" pins of the bus). Some methods of providing security for data transfer may include encrypting/decrypting data; however, the encryption/decryption process may adversely affect system performance and/or increase circuit complexity, among other drawbacks.

Drawings

Fig. 1 is a block diagram of an apparatus in the form of a computing system including a memory device, according to several embodiments of the present disclosure.

FIG. 2 illustrates a schematic diagram of a portion of a memory array, according to several embodiments of the present disclosure.

FIG. 3 illustrates a schematic diagram of a portion of a memory array, according to several embodiments of the present disclosure.

FIG. 4 illustrates a schematic diagram of a portion of a memory array, according to several embodiments of the present disclosure.

FIG. 5 illustrates a schematic diagram of an example method of memory array accessibility, in accordance with several embodiments of the present disclosure. FIG. 6 is a schematic diagram illustrating a sensing circuit according to several embodiments of the present disclosure.

FIG. 7 is a schematic diagram illustrating a sensing circuit having selectable logical operation selection logic in accordance with several embodiments of the present disclosure.

FIG. 8 is a logic table illustrating results of selectable logic operations implemented by a sensing circuit in accordance with several embodiments of the present disclosure.

FIG. 9 illustrates a timing diagram associated with performing logic operations and shift operations using sensing circuitry in accordance with several embodiments of the present disclosure.

FIG. 10 illustrates a timing diagram associated with performing logic operations and shift operations using sensing circuitry in accordance with several embodiments of the present disclosure.

Detailed Description

An example apparatus includes an array of memory cells. The array may include a first portion that is accessible to a controller of the array and inaccessible to a device external to the apparatus. The array may include a second portion accessible to a device external to the apparatus. The array may include a number of registers that store a row address indicating which portion of the array is the first portion. The apparatus may include a controller configured to access the number of registers to allow a device external to the apparatus to access a second portion based on a stored row address.

According to various embodiments of the present disclosure, data stored in a memory array may be protected by preventing access to a particular portion of the memory array and allowing access to another portion of the memory array. For example, a device external to a memory built-in Processor (PIM) device, such as an external processor, may be prevented from accessing a particular portion (e.g., a non-accessible portion), and an external device may be allowed to access another portion (e.g., an accessible portion) of the memory array. The rows of registers may include addresses that indicate boundaries of inaccessible (e.g., protected) portions of the memory array, and data corresponding to addresses outside of the boundaries may be accessed by an external device. In at least one embodiment, the number of line registers may be written only by ISA instructions. As used herein, a PIM device refers to a memory device capable of performing bit vector operations on bit vectors stored in an array without transferring data to a processing resource external to the PIM device, such as a host processor.

A first row of registers may store an address indicating the beginning of the inaccessible portion and a second row of registers may store an address indicating the end of the inaccessible portion. The address stored in the row register can be modified in order to dynamically modify the inaccessible portion in response to more or less data being protected in the memory array. Since the protected data from the inaccessible portion is not transferred via the bus and/or pins across the PIM device, the protected data is not accessible by an external device that attempts to read the data while the data is being transferred, in order to determine how to access the protected data, change passwords or access to the protected data, alter instructions in the memory array, etc.

As used herein, "bit vector operations" are intended to refer to operations performed on bit vectors associated with virtual address spaces and/or physical address spaces used by PIM devices. Examples of bit vector operations may include logical operations (e.g., boolean operations) and/or mathematical operations (e.g., addition, subtraction, multiplication, division, etc.), among others. Fig. 6-11, described below, describe the operation of the PIM device and additionally describe how the operation is performed without transferring data external to the PIM device. Maintaining data in the memory device allows data in the first portion of the memory array to be protected when data and/or instructions in the memory array can be executed or operated on without transferring data along the bus and/or across pins that can be detected by an external device (e.g., a hacker, a detection device, etc.).

In some embodiments, the bit vector may be a physically contiguous number of bits that are physically contiguous stored in a row and/or in sensing circuitry of the PIM device. For example, a row of virtual address space in a PIM device may have a bit length of 16K bits (e.g., corresponding to 16K complementary pairs of memory cells in a DRAM configuration). As described herein, sensing circuitry 150 for such 16K bit rows can include corresponding 16K processing elements (e.g., compute components as described herein) that are formed at a pitch with sense lines that can be selectively coupled to corresponding memory cells in the 16 bit rows. As described additionally in conjunction with fig. 6 and elsewhere herein, the computing components and corresponding sense amplifiers in the PIM device may operate as a one-bit processing element.

Several embodiments of the present disclosure may provide improved parallelism and/or reduced power consumption in performing logic operations as compared to previous systems having external processors (e.g., processing resources located outside of a memory array, such as on a separate integrated circuit chip). For example, several embodiments may enable performing operations such as integer addition, subtraction, multiplication, division, and Content Addressable Memory (CAM) operations without transferring data out of the memory array and sensing circuitry via, for example, buses (e.g., data bus, address bus, control bus). However, embodiments are not limited to these examples. For example, the PIM device may perform several non-boolean logic operations, such as sense amplifier set, sense amplifier clear, copy, compare, destroy, and the like.

In previous approaches, data may be transferred from the array and sensing circuitry (e.g., via a bus comprising input/output (I/O) lines) to processing resources such as processors, microprocessors, and/or compute engines, which may include ALU circuitry and/or other functional unit circuitry configured to perform appropriate logical operations. However, transferring data from the memory array and sensing circuitry to such processing resources may involve significant power consumption. Even if the processing resources are located on the same chip as the memory array, significant power can be consumed in the following process: moving data out of the array to computational circuitry, which may involve performing a sense line (which may be referred to herein as a digit line or a data line) address access (e.g., activating a column decode signal) in order to transfer data from the sense line onto an I/O line (e.g., a local I/O line), moving the data to the array periphery, and providing the data to circuitry to perform computational functions. The ability of the PIM device to perform operations within the memory (e.g., in conjunction with executing instructions) allows data to be moved through the array to be processed without being transferred across the bus and/or across pins. In this way, a "monolithic" architecture for internally protecting data in a memory array may be achieved.

Furthermore, in some previous approaches, the circuitry of the processing resource (e.g., compute engine) may not comply with the pitch rules associated with the memory array. For example, a cell of a memory array may have a 4F²Or 6F²Cell size, where "F" is the feature size corresponding to a cell. Thus, devices (e.g., logic gates) associated with the ALU circuitry of previous PIM systems may not be able to be formed at the same spacing as the sense lines of the array, whichFor example, chip size and/or memory density may be affected.

For example, the sensing circuitry 150 described herein can be formed at the same pitch with a pair of complementary sense lines. For example, a pair of complementary memory cells may have a bit line with 6F²A unit size of pitch (e.g., 3F × 2F). If the spacing of a pair of complementary sense lines for a complementary memory cell is 3F, then the sensing circuitry being spaced indicates that the sensing circuitry (e.g., sense amplifiers and corresponding compute components of each respective pair of complementary sense lines) is formed to fit within the 3F spacing of the complementary sense lines.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration ways in which one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and structural changes may be made without departing from the scope of the present disclosure. As used herein, the designation "N" specifically with respect to a reference numeral in the drawings indicates that a number of the specific features so designated may be included. As used herein, "a number of a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).

The figures herein follow a numbering convention in which the first one or more digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 206 may represent element "06" in fig. 2, and a similar element may be represented as 606 in fig. 6. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or removed to provide several additional embodiments of the present disclosure. Additionally, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense.

Fig. 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120, according to several embodiments of the present disclosure. As used herein, memory device 120, memory array 130, controller 140, and/or sensing circuitry 150 may also be considered "apparatus" individually.

The system 100 includes a host 110 coupled (e.g., connected) to a memory device 120 that includes a memory array 130. The memory device 120 may be a PIM device. Host 110 may be a host system such as a personal handheld computer, desktop computer, digital camera, smart phone, or memory card reader, among various other types of hosts. The host 110 may include a system motherboard and/or backplane, and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). The system 100 may include separate integrated circuits, or both the host 110 and the memory device 120 may be on the same integrated circuit. For example, system 100 may be a server system and/or a High Performance Computing (HPC) system and/or a portion thereof. Although the example shown in fig. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure may be implemented in a non-Von Neumann architecture (e.g., a Turing (Turing) machine) that may not include one or more components (e.g., CPUs, ALUs, etc.) typically associated with Von Neumann architectures.

For clarity, the system 100 has been simplified to focus on features particularly relevant to the present disclosure. The memory array 130 may be, for example, a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, a RRAM array, a NAND flash array, and/or a NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and arranged in columns coupled by sense lines. Although a single array 130 is shown in fig. 1, embodiments are not limited thereto. For example, the memory device 120 may include several arrays 130 (e.g., arrays of DRAM cells). An example DRAM array is described in connection with fig. 6.

Memory device 120 includes address circuitry 142 to latch address signals provided through I/O circuitry 144 over I/O bus 156, such as a data bus. Address signals may also be received (e.g., via address circuitry 142 and/or via bus 154) to controller 140. Row decoder 146 and column decoder 152 receive and decode address signals to access the memory array 130. Data can be read from the memory array 130 by sensing voltage and/or current changes on the data lines using the sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 may be used for bi-directional data communication with the host 110 via an I/O bus 156. Write circuitry 148 is used to write data to the memory array 130.

The controller 140 decodes signals provided from the host 110 via the control bus 154. These signals may include chip enable signals, write enable signals, and address latch signals to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the controller 140 is responsible for executing instructions from the host 110. The controller 140 may be a state machine, a sequencer, or some other type of control circuitry. The controller 140 may be implemented in hardware, firmware, and/or software. The controller 140 may also control a shift circuit, which may be implemented, for example, in the sensing circuit 150 according to various embodiments.

Examples of the sensing circuit 150 are described further below. For example, in several embodiments, the sensing circuitry 150 may include several sense amplifiers (e.g., the sense amplifier shown as 606 in FIG. 6 and 706 in FIG. 7) and several compute components (e.g., the compute component shown as 631 in FIG. 6 and/or 731 in FIG. 7) that may be used to perform bit vector operations on data stored in the array 130. The sense amplifier may include, for example, a static latch, which may be referred to herein as a master latch. The compute component 631 may include, for example, dynamic and/or static latches, which may be referred to herein as secondary latches, and may act and be referred to as accumulators.

In a number of embodiments, sensing circuitry (e.g., 150) can be used to perform operations using data stored in the array 130 as inputs and store the results of the logical operations back to the array 130 without transferring the data via sense line address access (e.g., without asserting a column decode signal). Thus, various logic functions may be performed using the sensing circuitry 150 and within the sensing circuitry 150, rather than being performed by (or in conjunction with) processing resources external to the sensing circuitry, such as by a processor associated with the host 110 and other processing circuitry, such as ALU circuitry located on the device 120 (e.g., on the controller 140 or elsewhere).

In various previous approaches, for example, data associated with operands would be read from memory via sense circuitry and provided to external ALU circuitry via I/O lines (e.g., via local I/O lines and global I/O lines). The external ALU circuitry may include a number of registers and will perform logical operations using the operands and transfer the results back to the array (e.g., 130) via the I/O lines. In contrast, in several embodiments of the present disclosure, sensing circuitry (e.g., 150) is configured to perform bit vector operations (e.g., logic operations) on data stored in memory (e.g., array 130) and store the results back to memory without enabling I/O lines (e.g., local I/O lines) coupled to the sensing circuitry, which may be formed on pitch with the memory cells of the array. Enabling the I/O line may include enabling (e.g., turning on) a transistor having a gate coupled to a decode signal (e.g., a column decode signal) and a source/drain coupled to the I/O line. The embodiments are not limited thereto. For example, in a number of embodiments, sensing circuitry (e.g., 150) can be used to perform logical operations without enabling column decode lines of the array; however, the local I/O lines may be enabled in order to transfer the results to the appropriate location rather than back to the array (e.g., to an external register).

Thus, in several embodiments, the array 130 and various circuitry external to the sensing circuitry 150 (e.g., external registers associated with the ALUs) need not perform logic functions, as the sensing circuitry 150 may perform appropriate logic operations to perform such logic functions without using external processing resources. In this manner, instructions in the array 130 may be executed on data stored in the array 130 internally to the array 130 without transferring the data out of the array and without exposing the data to possible detection, interception, hacking, and the like. Data and instructions in portions of the array that are not accessible by external devices may be protected, and additional portions of the array 130 storing unprotected data may be accessible.

Further, the sensing circuit 150 can be used to supplement and/or replace, at least to some extent, such external processing resources (or at least the bandwidth of such external processing resources). However, in several embodiments, in addition to performing logical operations by an external processing resource (e.g., host 110), the sensing circuit 150 may be used to perform logical operations (e.g., execute instructions). For example, the host 110 and/or the sensing circuitry 150 may be limited to performing only certain logical operations and/or a particular number of logical operations.

Fig. 2 illustrates a schematic diagram of a portion of a memory array 230, according to several embodiments of the present disclosure. The memory array 230 may be, for example, a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, a RRAM array, a NAND flash memory array, and/or a NOR flash memory array. Array 230 can include memory cells arranged in rows coupled by access lines (which can be referred to herein as word lines or select lines) and arranged in columns coupled by sense lines. Although a single array 230 is shown in fig. 2, embodiments are not limited thereto. For example, a memory device (such as memory device 120 in FIG. 1) may include several arrays 130 (e.g., arrays of DRAM cells). An example DRAM array is described in connection with fig. 7.

The memory array 230 may include a first portion 232 and a second portion 236. First portion 232 may include a number of rows of memory cells, illustrated as row X233 through row Y235, that are inaccessible (e.g., protected) by devices external to the memory device, such as memory device 120. As an example, a device external to the memory device cannot access data stored in the first portion 232, cannot execute instructions stored in the first portion 232, and cannot read data from and/or write data into the first portion 232. The first portion 232 may be accessible within a memory device (e.g., memory device 120), such as by a controller (e.g., controller 140). The first portion 232 may store data and/or instructions that may be executed by the controller. Data and/or instructions originating from first portion 232 may be prevented from being read while in the processor so that they are protected even when read by the processor inside the memory device.

The instructions may refer to Instruction Set Architecture (ISA) instructions, which may be binary-coded instructions that are accepted by the PIM device to perform various bit vector operations. ISA refers to the interface or boundary between software and hardware. Generally, programs executable on a PIM device can include a set of ISA instructions and data (e.g., operands). The ISA may allow for multiple implementations that may vary in terms of performance, physical size, and cost. An instruction stored in the first portion 232 may execute the instruction using data stored in the first portion 232 and the second portion 236 (e.g., using the data as operands). Instructions stored in the first portion 232 may be prevented from being executed at additional locations outside of the second portion 236 or the memory device. Instructions originating outside of the first portion 232 (e.g., DRAM Activate (ACT) instructions) may be prevented from being executed in the first portion 232. Instructions internal to the PIM device (e.g., PIM DRAM Activate (ACT) instructions) may be prevented from being executed outside of the first portion 323. In at least one embodiment, the instructions are executable to store the data result in the second portion 236. Data stored into the second portion 236 by a device external to the PIM device may only be stored in the first portion 232 by execution of the instructions in the first portion 232.

The second portion 236 may include several rows, namely row Y +1 through row Y + N. The second portion 236 may store data that is accessible to a memory device (e.g., the memory device 120) and a device external to the memory device. To transfer data stored in the first portion 232 to an external device, the data may be transferred to the second portion 236 and from the second portion 236 to the external device. To use the data set from the external device, the data set from the external device may be transferred to the second portion 236 and the instructions stored in the first portion 232 may be executed using the data set.

In at least some embodiments, the second portion 236 may be prevented from storing instructions in the second portion 236. In this manner, instructions may be restricted to being executed from the first portion 232 and not being executed from the second portion 236. The data stored in the second portion 236 may be recognized only as data (e.g., operands) and not as instructions. If an external device has added incorrect or erroneous data to the second portion 236, executing instructions from the first portion 232 may cause an error or incorrect result but not allow the instructions in the first portion 232 to be accessed or modified. Since the data in the second portion 236 is accessible, storing only the data and not the instructions in the second portion 236 prevents the instructions from being stored in the second portion 236 and executed from within the second portion 236 by an external device.

Memory array 230 may include registers 238, 239 that store addresses associated with first portion 232 and provide access control to first portion 232. The registers 238, 239 may be stored in the periphery of the array 230 of memory cells (e.g., no operand data is stored in the cells). The first register 238 stores a row address of an initial row of cells that store data in the first portion 232. The second register 239 stores the row address of the last row of cells storing data in the first portion 232. In this manner, the row addresses stored in the first and second registers 238, 236 define boundaries of the first portion 232 that are inaccessible to external devices. Registers 238, 239 may only be accessed by executing instructions (e.g., ISA instructions) stored in first portion 232. When the registers 238, 239 are initially loaded, the registers 238, 239 are only written to during certain stages described in connection with FIG. 4. Once initially loaded, registers 238, 239 may no longer be written to until a particular process may clear the registers (e.g., reset).

In at least one embodiment, the second portion 236 can store instructions for execution by the controller without reading data resulting from the execution or writing into the first portion 232. In this manner, data and/or instructions stored in the first portion 232 are protected from modification by instructions stored and executed in the second portion 236.

In response to a reset (e.g., a soft reset or a hard reset) of the memory device, the first portion 232 may be cleared (e.g., reset). In this manner, data within first portion 232 is also cleared in response to row registers 238, 239 reset that define the boundaries of first portion 232. Otherwise, when the row registers 238, 239 are reset, the boundary of the first portion 232 protecting the data may be cleared, and the data in the first portion 232 will be accessible to external devices and therefore not protected. By resetting the data of the first portion 232, the data previously stored in the first portion 232 is protected upon the memory device reset.

A memory device (e.g., memory device 120 in fig. 1) including memory array 230 may include fuses that disable row registers 238, 239 by default and that define first portion 232 without using the row registers 238, 239. Once the fuses are deactivated, the row registers 238, 239 may be activated to define the first portion 232.

FIG. 3 illustrates a schematic diagram of a portion of a memory array 330, according to several embodiments of the present disclosure. The memory array 330 may include a first portion 332 and a second portion 336. First portion 332 can include a number of rows of memory cells, illustrated as row X (333) through row Y (335), that are inaccessible (e.g., protected) by devices external to the memory device, such as memory device 120. The first portion 332 may be accessible within a memory device (e.g., memory device 120), such as by a controller (e.g., controller 140). The first portion 232 may store data and/or instructions that may be executed by the controller. The second portion 236 may include several rows, namely row Y +1 through row N. The second portion 236 may store data that is accessible to a memory device (e.g., the memory device 120) and a device external to the memory device.

The memory array 330 may include registers 338, 339 that store addresses associated with the first portion 332 and provide access control to the first portion 332. The registers 338, 339 may be stored in the periphery of the array 330 of memory cells (e.g., no operand data is stored in the cells). The first register 338 stores a row address of an initial row of cells that store data in the first portion 332. The second register 339 stores the row address of the last row of cells storing data in the first portion 332. In this manner, the row addresses stored in the first and second registers 338, 336 define the boundaries of the first portion 332 that are inaccessible to external devices.

The row addresses stored in the first and second registers 338, 339 may be modified in order to modify which cells of the array 330 are in the first portion 232 of cells and thereby modify which cells are not accessible to external devices. For example, the address stored in the second row register 338 may be modified from being associated with row Y (235) in FIG. 2 to being associated with row 337-1 to add an additional row of cells into the first portion 332. The additional modifications may include modifying the address stored in the second row register 338 to be associated with row 337-2 to add an additional row of cells, and the additional modifications may include modifying the address to be associated with row 337-3.

In this way, the amount of cell rows may be reduced to a size between row X333 and row 337-1, increased to an amount of rows between row X and row 337-2, and additionally increased to an amount of rows between row X and row 337-3. The modification may be based on the amount of data protected in the first portion 332. The row registers 338, 339 may be writable by ISA instructions. The row registers 338, 339 may be writable by ISA instructions executed from the first portion 332. By modifying the size of the first portion 332, the memory array 330 may dynamically protect the amount of data based on the size of the data and without being limited by the size of the first portion 332.

FIG. 4 illustrates a schematic diagram of a portion of a memory system 404 in accordance with several embodiments of the present disclosure. The memory system 404 may include a memory device (e.g., PIM device) 420 and encrypted user data 449 stored on a hard disk drive. The memory device 420 may include a memory array 430, a decryption key 441, and a hardware decryption engine 443.

The memory array 430 may include a first portion (e.g., a non-accessible portion) 432, a second portion (accessible portion 436 and row registers 438, 439. decryption key 441 may be used to trigger fuses in the memory device 420 to indicate that the rows of the first portion 432 are defined using the row registers 438, 439. the row registers 438, 439 may initially indicate that the first portion 432 is allowed to be accessed when data is initially loaded into the first portion.

FIG. 5 illustrates a schematic diagram of an example method 505 of memory array accessibility in accordance with several embodiments of the present disclosure. Method 505 may include clearing the memory array (e.g., memory arrays 230, 330, 430 in fig. 2-4, respectively) and the register (e.g., registers 238, 239, 338, 339, 438, 439 in fig. 2-4, respectively) at 551. In at least one embodiment, the first portion (e.g., first portion 232, 332, 432) and the second portion (e.g., second portion 236, 336, 436) can be eliminated. In at least one embodiment, the first portion can be removed and the second portion not.

Method 505 may include, at 553, loading an (RAC) register (e.g., registers 238, 239, 338, 339, 438, 439, respectively, in fig. 2-4) from an external device to a memory array (e.g., memory arrays 130, 230, 330, 430, respectively, in fig. 1-4). The data loaded into the register may indicate a section of the memory array that constitutes a first portion of the memory array. The data may include a row address indicating a first initial row of the first portion and a row address indicating a last row of the first portion. The data may indicate a boundary of a row defining the first portion in the memory array.

The method 505 may include, at 555, decrypting the write into the first portion. The writing may be allowed by reversing the normal process of initially blocking writing or reading into the first portion, at which point the data to be protected will be written to the first portion at some point or where no data previously written thereto needs to be protected. The write may be data from an external device and/or a controller of a memory device, such as memory device 120 in fig. 1. The data written may be data indicating protection by the memory array. Where a first portion of a memory array has limited access (e.g., an external device does not access the first portion), data is written into the first portion.

Method 505 may include, at 557, preventing data from being written or read from the first portion. In response to initial data being written to the first portion, the register indicating which rows make up the first portion indicates that data is not to be written to or read from the first portion. This reversal from allowing the initial writing of external data to not allowing any data to be written or read results in limited access and thus protects the data written to the first portion.

The method 505 may include, at 559, performing a normal protected operation. The protected operation may include executing an instruction stored in the first portion on data (e.g., an operand) stored in either of the first portion and the second portion. The protected operation may include preventing an external device from accessing the first portion upon execution of the execution instruction in the first portion. The protected operation may include preventing instructions stored outside the first portion from being executed in the first portion. The protected operation may include preventing instructions from the first portion from executing outside the first portion. In this way, data stored in the first portion is prevented from being snooped or detected by hackers. Instructions and/or data stored in the first portion may be prevented from being read and no instructions and/or data may be written to the first portion. To access the data in the first portion, the data may be first written to and then read from the second portion.

FIG. 6 is a schematic diagram illustrating a sensing circuit according to several embodiments of the present disclosure. A memory cell includes a storage element (e.g., a capacitor) and an access device (e.g., a transistor). For example, transistor 602-1 and capacitor 603-1 comprise memory cells, and transistor 602-2 and capacitor 603-2 comprise memory cells, and so on. In this example, memory array 630 is a DRAM array of one transistor one capacitor (1T1C) memory cells. In a number of embodiments, the memory cells can be destructive read memory cells (e.g., reading data stored in a cell destroys data such that data originally stored in the cell is refreshed after being read).

The cells of the memory array 630 may be arranged in rows coupled by word lines 604-X (row X), 604-Y (row Y), etc., and columns coupled by pairs of complementary sense lines (e.g., data lines DIGIT (n)/DIGIT (n)) _. The individual sense lines corresponding to each pair of complementary sense lines may also be referred to as data lines 605-1(D) and 605-2(D _), respectively. Although only a pair of complementary data lines (e.g., one column) is shown in fig. 6, embodiments of the disclosure are not so limited, and the memory cell array may include additional columns of memory cells and/or data lines (e.g., 4096, 8192, 16384, etc.).

The memory cells may be coupled to different data lines and/or word lines. For example, a first source/drain region of the transistor 602-1 may be coupled to the data line 605-1(D), a second source/drain region of the transistor 602-1 may be coupled to the capacitor 603-1, and a gate of the transistor 602-1 may be coupled to the word line 604-Y. A first source/drain region of the transistor 602-2 may be coupled to the data line 605-2(D _), a second source/drain region of the transistor 602-2 may be coupled to the capacitor 603-2, and a gate of the transistor 602-2 may be coupled to the word line 604-X. A cell plate as shown in fig. 6 may be coupled to each of capacitors 603-1 and 603-2. The cell plates may be common nodes to which a reference voltage (e.g., ground) may be applied in various memory array configurations.

The memory array 630 is coupled to sensing circuitry 650, according to several embodiments of the present disclosure. In this example, the sense circuitry 650 includes sense amplifiers 606 and compute components 631 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines). For example, the sensing circuit 650 may correspond to the sensing circuit 150 shown in fig. 1. Sense amplifier 606 can be coupled to the pair of complementary sense lines 605-1 and 605-2. The compute component 631 may be coupled to the sense amplifier 606 via pass gates 607-1 and 607-2. The gates of pass gates 607-1 and 607-2 may be coupled to logic operation selection logic 613.

The logic operation selection logic 613 may be configured to include pass gate logic for controlling pass gates coupled to the pair of complementary sense lines 605-1 and 605-2 that are not transposed between the sense amplifier 606 and the compute component 631 (as shown in FIG. 6), and/or swap gate logic for controlling swap gates coupled to the pair of complementary sense lines that are transposed between the sense amplifier 606 and the compute component 631 (such as discussed later with respect to FIG. 7). The logical operation selection logic 613 may also be coupled to the pair of complementary sense lines 605-1 and 605-2. The logical operation selection logic 613 may be configured to control the pass gates 607-1 and 607-2 (e.g., to control whether the pass gates 607-1 and 607-2 are in a conductive state or a non-conductive state) based on the selected logical operation, as described in detail below for various configurations of the logical operation selection logic 613.

The sense amplifier 606 may be operated to determine a data value (e.g., a logic state) stored in a selected memory cell. Sense amplifier 606 may include cross-coupled latches, which may be referred to herein as master latches. In the example illustrated in FIG. 6, the circuit corresponding to the sense amplifier 606 includes a latch 615 that includes four transistors coupled to the pair of complementary data lines 605-1 and 605-2. However, embodiments are not limited to this example. The latch 615 may be a cross-coupled latch (e.g., the gates of a pair of transistors, such as n-channel transistors (e.g., NMOS transistors) 627-1 and 627-2) cross-coupled with the gates of another pair of transistors, such as p-channel transistors (e.g., PMOS transistors) 629-1 and 629-2).

In operation, when a memory cell is being sensed (e.g., read), the voltage on one of the data lines 605-1(D) or 605-2(D _) will be slightly greater than the voltage on the other of the data lines 605-1(D) or 605-2(D _). The ACT signal may be driven high and the RNL signal may be driven low to enable (e.g., fire) the sense amplifier 606. The data line 605-1(D) or 605-2 (D) having the lower voltage will turn on the other of the PMOS transistors 629-1 or 629-2 (D) to a greater extent than one of the PMOS transistors 629-1 or 629-2 (D), thereby driving the data line 605-1(D) or 605-2 (D) having the higher voltage high to a greater extent than the other data line 605-1(D) or 605-2 (D) is driven high.

Similarly, the data line 605-1(D) or 605-2 (D) having a higher voltage will turn on the other one of the NMOS transistors 627-1 or 627-2 to a greater extent than one of the NMOS transistors 627-1 or 627-2, thereby driving the other data line 605-1(D) or 605-2 (D) to a greater extent than the other data line 605-1(D) or 627-2 (D) to lowData line 605-1(D) or 605-2(D _) is driven low. Thus, after a short delay, the data line 605-1(D) or 605-2(D _) having a slightly larger voltage is driven to the supply voltage V_DDE.g., through a source transistor (not shown)), and the other data line 605-1(D) or 605-2(D _) is driven to the voltage of the reference voltage (e.g., to Ground (GND) through a sink transistor (not shown)). Thus, the cross-coupled NMOS transistors 627-1 and 627-2 and PMOS transistors 629-1 and 629-2 act as a pair of sense amplifiers that amplify the differential voltage on data lines 605-1(D) and 605-2(D _) and are used to latch the data value sensed from the selected memory cell.

Embodiments are not limited to the sense amplifier 606 configuration illustrated in FIG. 6. As an example, sense amplifier 606 may be a current mode sense amplifier and/or a single ended sense amplifier (e.g., a sense amplifier coupled to one digit line). Also, embodiments of the present disclosure are not limited to the folded data line architecture, such as shown in fig. 6.

The sense amplifier 606 may operate in conjunction with a compute component 631 to perform various logical operations using data from the array as inputs. In several embodiments, the results of the logical operations may be stored back to the array without transferring data via data line address access (e.g., without asserting a column decode signal so that data is transferred via local I/O lines to circuitry external to the array and sensing circuitry). Thus, several embodiments of the present disclosure may enable the use of less power to perform the logical operations associated therewith, as compared to various previous approaches. In addition, because several embodiments may eliminate the need to transfer data across I/O lines in order to perform logical functions (e.g., between memory and a discrete processor), several embodiments may achieve increased parallel processing capabilities over previous approaches.

Sense amplifier 606 may additionally include a balancing circuit 614 that may be configured to balance data lines 605-1(D) and 605-2(D _). In this example, the equilibration circuit 614 includes a transistor 624 coupled between data lines 605-1(D) and 605-2(D _). The balancing circuits 614 also include circuits each having a coupling to a balancing voltage (e.g., V)_DDFirst source of/2)Transistors 625-1 and 625-2 of the pole/drain region, where V_DDIs the supply voltage associated with the array. A second source/drain region of transistor 625-1 may be coupled to data line 605-1(D) and a second source/drain region of transistor 625-2 may be coupled to data line 605-2(D _). The gates of transistors 624, 625-1, and 625-2 may be coupled together and to a balance (EQ) control signal line 626. Thus, activating EQ enables transistors 624, 625-1, and 625-2, which effectively shorts data lines 605-1(D) and 605-2(D _) together and to a balanced voltage (e.g., V @)_DD/2)。

Although fig. 6 shows the sense amplifier 606 to include the balancing circuit 614, embodiments are not so limited, and the balancing circuit 614 may be implemented separately from the sense amplifier 606, in a different configuration than that shown in fig. 6, or not implemented at all.

As described further below, in several embodiments, the sensing circuitry (e.g., the sense amplifiers 606 and compute components 631) is operable to perform selected logical operations and initially store the results in one of the sense amplifiers 606 or compute components 631 without transferring data from the sensing circuitry via the I/O lines (e.g., without performing data line address access via activation of, for example, a column decode signal).

As shown in fig. 6, the compute component 631 may also include a latch 664, which may be referred to herein as a secondary latch. The secondary latch 664 may be configured and operated in a manner similar to that described above with respect to the primary latch 615, except that the pair of cross-coupled p-channel transistors (e.g., PMOS transistors) comprising the secondary latch may have their respective sources coupled to a supply voltage (e.g., V |)_DD) And the pair of cross-coupled n-channel transistors (e.g., NMOS transistors) of the secondary latch may have their respective sources selectively coupled to a reference voltage (e.g., ground) in order to successively enable the secondary latch. The configuration of the computing components is not limited to the configuration shown at 631 in fig. 6, and various other embodiments are described further below.

FIG. 7 is a schematic diagram illustrating a sensing circuit having selectable logical operation selection logic in accordance with several embodiments of the present disclosure. FIG. 7 shows a number of sense amplifiers 706 coupled to respective pairs of complementary sense lines 705-1 and 705-2, and a corresponding number of compute components 731 coupled to the sense amplifiers 706 via pass gates 707-1 and 707-2. The gates of PASS gates 707-1 and 707-2 may be controlled by a logic operation selection logic signal PASS. For example, the output of logical operation selection logic 713-6 may be coupled to the gates of pass gates 707-1 and 707-2.

According to the embodiment illustrated in FIG. 7, compute component 731 may comprise respective stages of loadable shift registers (e.g., shift cells) configured to shift data values left and right. According to some embodiments, the compute component 731 may have bi-directional shifting capability. The compute components 731 can comprise loadable shift registers configured to shift in multiple directions (e.g., to the left and right), in accordance with various embodiments of the present disclosure (e.g., with each compute component 731 acting as a respective shift stage). According to various embodiments of the present disclosure, compute component 731 may comprise respective stages of loadable shift registers (e.g., shift cells) configured to shift in one direction. A loadable shift register may be coupled to the pair of complementary sense lines 705-1 and 705-2, with node ST2 of each stage coupled to the sense line conveying a true data value (e.g., DIGIT (n)) and with node SF2 of each stage coupled to the sense line conveying a complementary (e.g., false) data value (e.g., DIGIT (n)) _).

According to some embodiments and as illustrated in fig. 7, each compute component 731 (e.g., stage) of the shift register includes a pair of right shift transistors 781 and 786, a pair of left shift transistors 789 and 790, and a pair of inverters 787 and 788. Signals PHASE1R, PHASE 2R, PHASE1L and PHASE2L may be applied to respective control lines 782, 783, 791 and 792 to enable/disable feedback on latches of corresponding compute component 731 in association with performing logical operations and/or shifting data according to embodiments described herein. Examples of shifting data (e.g., from a particular compute component 731 to an adjacent compute component 731) are described further below with respect to fig. 9 and 10.

The compute components 731 (e.g., stages) of the loadable shift register can include a first right shift transistor 781 having a gate coupled to a first right shift control line 780 (e.g., "PHASE 1R"), and a second right shift transistor 786 having a gate coupled to a second right shift control line 782 (e.g., "PHASE 2R"). The node ST2 of each stage of the loadable shift register is coupled to the input of the first inverter 787. The output of the first inverter 787 (e.g., node SF1) is coupled to one source/drain of the second right shift transistor 786, and the other source/drain of the second right shift transistor 786 is coupled to the input of the second inverter 788 (e.g., node SF 2). The output of the second inverter 788 (e.g., node ST1) is coupled to one source/drain of the first right shift transistor 781, and the other source/drain of the first right shift transistor 781 is coupled to the input of the second inverter (e.g., node SF2) for the neighboring compute component 731. The LATCH transistor 785 has a gate coupled to a LATCH control signal 784. One source/drain of the latch transistor 785 is coupled to the node ST2, and the other source/drain of the latch transistor 785 is coupled to the node ST 1.

The sense amplifier 706 can be coupled to a respective pair of complementary sense lines 705-1 and 705-2, and a corresponding compute component 731 is coupled to the sense amplifier 706 via respective pass gates 707-1 and 707-2. The gates of pass gates 707-1 and 707-2 may be controlled by respective logic operation selection logic signals "Passd" and "Passdb" that may be output from logic operation selection logic (not shown for clarity).

The first left shift transistor 789 is coupled between node SF2 of one loadable shift register to node SF1 of the loadable shift register corresponding to the adjacent compute component 731. The channel of the second left shift transistor 790 is coupled from node ST2 to node ST 1. The gate of the first left shift transistor 789 is coupled to a first left shift control line 791 (e.g., "PHASE 1L"), and the gate of the second left shift transistor 790 is coupled to a second left shift control line 792 (e.g., "PHASE 2L").

Logic operation selection logic 713-6 includes swap gate 742, as well as logic to control pass gates 707-1 and 707-2 and swap gate 742. Logic operation selection logic 713-6 includes four logic selection transistors: a logic select transistor 762 coupled between the gate of swap transistor 742 and the TF signal control line, a logic select transistor 752 coupled between the gates of pass gates 707-1 and 707-2 and the TT signal control line, a logic select transistor 754 coupled between the gates of pass gates 707-1 and 707-2 and the FT signal control line, and a logic select transistor 764 coupled between the gate of swap transistor 742 and the FF signal control line. The gates of logic select transistors 762 and 752 are coupled to a true sense line through isolation transistor 750-1 (having a gate coupled to an ISO signal control line). The gates of logic select transistors 764 and 754 are coupled to a complementary sense line through isolation transistor 750-2 (also having a gate coupled to an ISO signal control line). Fig. 10 and 11 illustrate timing diagrams associated with performing logic operations and shift operations using the sensing circuit shown in fig. 7.

The data values on the respective complementary sense lines 705-1 and 705-2 can be loaded into the respective compute component 731 (e.g., loadable shift register) by causing pass gates 707-1 and 707-2 to conduct, e.g., causing the pass control signal to go high. A gate controlled to have continuity (e.g., electrical continuity across a channel) is conductive and may be referred to herein as OPEN (OPEN). Gates that are controlled to have no continuity (e.g., electrical continuity across a channel) are said to be non-conductive and may be referred to herein as CLOSED (CLOSED). For example, continuity refers to a low resistance condition in which the gate is on. Data values may be loaded into respective compute components 731 by over-powering the corresponding compute components 731 with sense amplifiers 706 (e.g., to overwrite existing data values in the compute components 731) and/or by turning off the PHASE1R and PHASE 2R control signals 780 and 782 and the LATCH control signal 784. A first latch (e.g., a sense amplifier) may be configured to over-power a second latch (e.g., a compute component) when current provided by and presented to the first latch is sufficient to flip the second latch.

The sense amplifier 706 can be configured to over-power the compute component 731 by driving the voltage on the pair of complementary sense lines 705-1 and 705-2 to a maximum supply voltage corresponding to a data value (e.g., driving the pair of complementary sense lines 705-1 and 705-2 to a rail), which can change the voltage stored in the compute component 731A data value. According to various embodiments, the compute component 731 can be configured to transfer a data value to the pair of complementary sense lines 705-1 and 705-2 without driving the voltage of the pair of complementary sense lines 705-1 and 705-2 to a rail (e.g., to V)_DDOr GND). As such, the compute component 731 can be configured to not over-power the sense amplifier 706 (e.g., the data value from the compute component 731 on the pair of complementary sense lines 705-1 and 705-2 will not change the data value stored in the sense amplifier 706 before the sense amplifier is enabled).

Once the data value is loaded into the compute component 731 of the loadable shift register, the true data value is spaced from the supplemental data value by the first inverter 787. The data value may be shifted to the right (e.g., to adjacent compute component 731) by alternating operation of first right shift transistor 781 and second right shift transistor 786, which may be achieved when first right shift control line 780 and second right shift control line 782 have periodic signals that go high out of phase with one another (e.g., alternating square waves are made 180 degrees out of phase with one another without overlapping). The LATCH control signal 784 can be activated to cause the LATCH transistor 785 to turn on, thereby latching a data value into the corresponding compute component 731 of the loadable shift register (e.g., while the signal PHASE1R remains low and PHASE 2R remains high to maintain the data value latched in the compute component 731).

Fig. 8 is a logic table illustrating results of selectable logic operations implemented by a sensing circuit (e.g., the sensing circuits shown in fig. 6 and 7) in accordance with several embodiments of the present disclosure. Four logic select control signals (e.g., TF, TT, FT, and FF) in combination with particular data values present on the complementary sense lines can be implemented to select one of a plurality of logic operations involving a starting data value stored in the sense amplifier 606 and the compute component 631. The four control signals (e.g., TF, TT, FT, and FF), in combination with particular data values present on the complementary sense lines (e.g., on nodes S and S), control the pass gates 707-1 and 707-2 and swap transistors 742, which in turn affect the data values in the compute component 731 and/or sense amplifier 706 before/after firing. The ability to selectively control the swap transistor 742 facilitates, among other things, implementing logical operations involving inverting data values (e.g., inverting operands and/or inverting results).

The logic table 8-1 illustrated in FIG. 8 shows the starting data value stored in compute component 631 shown in column A at 844, and the starting data value stored in sense amplifier 606 shown in column B at 845. The other 3 columns of headers in the logic table 8-1 refer to the states of the pass gates 607-1 and 607-2 and the swap transistor 742, which pass gates 607-1 and 607-2 and swap transistor 742 may be controlled to be open or closed depending on the states of the four logic select control signals (e.g., TF, TT, FT, and FF), respectively, and in conjunction with the particular data values present on the pair of complementary sense lines 605-1 and 605-2, when the ISO control signal is asserted. A "not open" column corresponds to both pass gates 607-1 and 607-2 and swap transistor 742 being in a non-conducting condition, a "positively open" column corresponds to pass gates 607-1 and 607-2 being in a conducting condition, and an "inversely open" column corresponds to swap transistor 742 being in a conducting condition. The configuration corresponding to pass gates 607-1 and 607-2 and swap transistor 742 both being in a conducting condition is not reflected in logic table 8-1, as this would cause the sense lines to be shorted together.

Via selective control of pass gates 707-1 and 707-2 and swap transistor 742, each of the three columns of the upper portion of logic table 8-1 may be combined with each of the three columns of the lower portion of logic table 8-1 to provide nine (e.g., 3 x 3) different resulting combinations, corresponding to nine different logic operations, as indicated by the respective connection paths shown at 875. The nine different selectable logic operations that may be implemented by the sensing circuit 650 are summarized in logic table 8-2.

The column of logic table 8-2 shows a header 880 that includes the state of the logic select control signals (e.g., FF, FT, TF, TT). For example, the state of a first logic select control signal (e.g., FF) is provided in row 876, the state of a second logic select control signal (e.g., FT) is provided in row 877, the state of a third logic select control signal (e.g., TF) is provided in row 878, and the state of a fourth logic select control signal (e.g., TT) is provided in row 879. The particular logical operations corresponding to the results are summarized in row 847.

Fig. 9 illustrates a timing diagram associated with performing a logical AND operation AND a shift operation using sensing circuitry in accordance with several embodiments of the present disclosure. Fig. 9 contains waveforms corresponding to signals EQ, ROW X, ROW Y, SENSE AMP, TF, TT, FT, FF, PHASE1R, PHASE 2R, PHASE1L, PHASE2L, ISO, Pass, DIGIT, and DIGIT _ respectively. The EQ signal corresponds to a balanced signal associated with the sense amplifier (e.g., EQ 626 shown in fig. 6). The ROW X and ROW Y signals correspond to signals applied to respective access lines (e.g., access lines 604-X and 604-Y shown in fig. 6) to access a selected cell (or ROW of cells). The SENSE AMP signal corresponds to a signal to enable/disable a SENSE amplifier (e.g., SENSE amplifier 706). The TF, TT, FT, and FF signals correspond to logic select control signals (e.g., signals coupled to logic select transistors 762, 752, 754, and 764), such as shown in fig. 7. The PHASE1R, PHASE 2R, PHASE1L and PHASE2L signals correspond to control signals (e.g., clock signals) provided to respective control lines 782, 783, 791 and 792 shown in fig. 7. The ISO signal corresponds to the signal coupled to the gates of isolation transistors 750-1 and 750-2 shown in fig. 7. The PASS signal corresponds to the signal coupled to the gates of PASS transistors 707-1 and 707-2 shown in fig. 7, and the PASS signal corresponds to the signal coupled to the gate of swap transistor 742. The DIGIT and DIGIT _ signals correspond to signals present on respective sense lines 705-1 (e.g., DIGIT (n)) and 705-2 (e.g., DIGIT (n)) _.

The timing diagram shown in FIG. 9 is associated with performing a logical AND operation on a data value stored in a first memory cell AND a data value stored in a second memory cell of the array. The memory cells can correspond to particular columns of the array (e.g., columns including complementary pairs of sense lines) and can be coupled to respective access lines (e.g., row X and row Y). In describing the logical AND operation shown in FIG. 9, reference is made to the sensing circuit described in FIG. 7. For example, the logical operations described in FIG. 9 may include storing a data value of a row X memory cell (e.g., a "row X data value") in a latch of a corresponding compute component 731 (e.g., an "A" data value), storing a data value of a row Y memory cell (e.g., a "row Y data value") in a latch of a corresponding sense amplifier 706 (e.g., a "B" data value), AND performing a selected logical operation on the row X data value AND the row Y data value (e.g., a logical AND operation in this example), the compute component 731 may be referred to as an accumulator 731, where the result of the selected logical operation is stored in the latch of the compute component 731.

As shown in fig. 9, at time T₁The sensing amplifier 706 is disabled from balancing (e.g., EQ goes low). At time T₂ROWX goes high to access (e.g., select) row X memory cells. At time T₃SENSE amplifier 706 is enabled (e.g., SENSE AMP goes high), which drives complementary SENSE lines 705-1 and 705-2 to the appropriate track voltage (e.g., V) responsive to the row X data value (e.g., as shown by the DIGIT and DIGIT _ signals)_DDAnd GND) and latches the row X data value in the sense amplifier 706. At time T₄The PHASE 2R and PHASE2L signals go low, which disables feedback on the latch of compute component 731 (e.g., by turning off transistors 786 and 790, respectively) so that the values stored in the compute component can be overwritten during logic operations. And, at time T₄ISO goes low, which disables isolation transistors 750-1 and 750-2. At time T₅TT and FT are enabled (e.g., high), which causes PASS to go high (e.g., since either transistor 752 or 754 will depend on when at time T₄Which of node ST2 (corresponding to node "S" in fig. 6) or node SF2 (corresponding to node "S" in fig. 6) is high to turn on when ISO is disabled) (recall that the voltages of nodes ST2 and SF2 dynamically reside on the gates of respective enable transistors 752 and 754 when ISO is disabled). PASS high enables PASS transistors 707-1 and 707-2 so that the DIGIT and DIGIT _ signals corresponding to the row X data values are provided to the respective compute component nodes ST2 and SF 2. At time T₆TT and FT are disabled, which causes PASS to go low, disabling PASS transistors 707-1 and 707-2. Note that PASS is at time T₅And T₆Remains low since the TF and FF signals remain low. At time T₇ROW X is disabled and PHASE 2R, PHASE2L and ISO are enabled. At time T₇Enabling PHASE 2R and PHASE2L will startFeedback on the latch of the compute component 731 is used to cause the row X data value to be latched in the latch. At time T₇Enabling ISO again couples nodes ST2 and SF2 to the gates of enable transistors 752, 754, 762, and 764. At time T₈Balance is enabled (e.g., EQ goes high so that DIGIT and DIGIT _ are driven to a balance voltage, e.g., V)_DD/2) and SENSE amplifier 706 is disabled (e.g., SENSE AMP goes low).

With the row X data value latched in compute component 731, balancing is disabled (e.g., at time T)₉EQ goes low). At time T₁₀ROW Y goes high to access (e.g., select) ROW Y memory cells. At time T₁₁SENSE amplifier 706 is enabled (e.g., SENSE AMP goes high), which drives the complementary SENSE lines 705-1 and 705-2 to the appropriate track voltage (e.g., V) in response to the row Y data value (e.g., as shown by the DIGIT and DIGIT _ signals)_DDAnd GND) and the row Y data value is latched in sense amplifier 706. At time T₁₂The PHASE 2R and PHASE2L signals go low, which disables feedback on the latch of compute component 731 (e.g., by turning off transistors 786 and 790, respectively) so that the values stored in the compute component can be overwritten during logic operations. And, at time T₁₂ISO goes low, which disables isolation transistors 750-1 and 750-2. Since the desired logical operation is an AND operation in this example, at time T₁₃TT is enabled while TF, FT, AND FF remain disabled (as shown in table 8-2, FF-0, FT-0, TF-0, AND TT-1 correspond to a logical AND operation). Enabling TT causes PASS to go high or not depends on when at time T₁₂The value stored in the calculation component 731 when ISO is disabled. For example, enable transistor 752 would turn on if node ST2 was high when ISO was disabled, and the enable transistor would be on when at time T₁₂When the ISO is deactivated, the node ST2 is low and does not conduct.

In this example, if at time T₁₃PASS goes high, PASS transistors 707-1 and 707-2 are enabled, and the DIGIT and DIGIT _ signals corresponding to the row Y data values are provided to respective compute component nodes ST2 and SF 2. Thus, the value stored in the compute component 731 (e.g., row X data value) canToggles depending on the values of DIGIT and DIGIT _ e.g., row Y data values. In this example, if PASS is at time T₁₃Held low, pass transistors 707-1 and 707-2 are not enabled so that the DIGIT and DIGIT _ signals corresponding to the row Y data values remain isolated from nodes ST2 and SF2 of compute component 731. Thus, the data values in the compute component (e.g., row X data values) will remain the same.

At time T₁₄TT is disabled, which causes PASS to go low (or remain low), causing PASS transistors 707-1 and 707-2 to be disabled. Note that PASS is at time T₁₃And T₁₄Remains low since the TF and FF signals remain low. At time T₁₅ROW Y is disabled and PHASE 2R, PHASE2L and ISO are enabled. At time T₁₅Enabling PHASE 2R AND PHASE2L enables feedback on the latch of compute component 731 so that the result of the AND operation (e.g., "a" AND "B") is latched in the latch. At time T₁₅Enable ISO again couples nodes ST2 and SF2 to the gates of enable transistors 752, 754, 762, and 764. At time T₁₆The sensing amplifier 706 is disabled (e.g., SENSE AMP goes low) and equilibration is enabled (e.g., EQ goes high so that DIGIT and DIGIT _ are driven to an equilibrium voltage).

The results of the AND operation, which are initially stored in compute component 731 in this example, can be transferred back to the memory array (e.g., via complementary sense lines back to memory cells coupled to row X, row Y, AND/or a different row) AND/or to an external location (e.g., an external processing component) via I/O lines.

Fig. 9 also includes (e.g., at 801) signaling associated with shifting data (e.g., from a compute component 731 to a neighboring compute component 731). The example shown in FIG. 9 illustrates two shifts to the left, such that data values stored in compute components corresponding to column "N" are shifted to the left to compute components corresponding to column "N-2". E.g. at time T₁₆As shown, PHASE 2R and PHASE2L are disabled, which disables feedback on the compute component latches, as described above. To perform the first left shift, PHASE1L is at time T₁₇Is enabled and at time T₁₈And (4) stopping the use. Enabling PHASE 1L-inducedTurning on transistor 789 causes the data value at node SF1 to move to the left to node SF2 of the left adjacent compute component 731. PHASE2L then at time T₁₉Is enabled and at time T₂₀And (4) stopping the use. Enabling PHASE2L causes transistor 790 to turn on, which causes the data value from node ST1 to move to the left to node ST2, completing the shift to the left.

The above sequence (e.g., enable/disable PHASE1L and then enable/disable PHASE 2L) may be repeated to achieve the desired number of left shifts. For example, in this example, by at time T₂₁Enable PHASE1L and at time T₂₂PHASE1L is disabled to perform the second left shift. PHASE2L then at time T₂₃Enabled to complete the second left shift. After the second left shift, PHASE2L remains enabled and PHASE 2R is enabled (e.g., at time T)₂₄) Such that feedback is enabled to latch the data value in the compute component latch.

FIG. 10 illustrates a timing diagram associated with performing a logical XOR operation and a shift operation using sensing circuitry in accordance with several embodiments of the present disclosure. Fig. 10 includes the same waveforms described above in fig. 9. However, the timing diagram shown in fig. 10 is associated with performing a logical XOR operation on the row X AND row Y data values (e.g., as compared to a logical AND operation). Reference is again made to the sensing circuit described in fig. 7.

FIG. 10 at time T₀To T₉The indicated signaling is the same as in fig. 9 and is not repeated here. Thus, at time T9, the EQ is disabled and the row X data value is latched in the compute component 731. At time T₁₀ROW Y goes high to access (e.g., select) ROW Y memory cells. At time T₁₁SENSE amplifier 706 is enabled (e.g., SENSE AMP goes high), which drives the complementary SENSE lines 705-1 and 705-2 to the appropriate track voltage (e.g., V) in response to the row Y data value (e.g., as shown by the DIGIT and DIGIT _ signals)_DDAnd GND) and the row Y data value is latched in sense amplifier 706. At time T₁₂The PHASE 2R and PHASE2L signals go low, which disables feedback on the latch of compute component 731 (e.g., by turning off transistors 786 and 790, respectively) so that logic operation may be performedDuring which the value stored in the calculation component 731 is overwritten. And, at time T₁₂ISO goes low, which disables isolation transistors 750-1 and 750-2. Since the desired logical operation is an XOR operation in this example, at time T₁₃TF and FT are enabled while TT and FF remain disabled (FF-0, FT-1, TF-1, and TT-0 correspond to logical XOR (e.g., "AXB") operations, as shown in table 10-2). Whether enabling TF and FT causes PASS or PASS to go high depends on when at time T₁₂The value stored in the calculation component 731 when ISO is disabled. For example, enable transistor 762 would be turned on if node ST2 was high when ISO is disabled, and enable transistor 762 would be turned on when at time T₁₂When the ISO is deactivated, the node ST2 is low and does not conduct. Similarly, enable transistor 754 will conduct if node SF2 is high when ISO is disabled, and enable transistor 754 will not conduct if node SF2 is low when ISO is disabled.

In this example, if PASS is at time T₁₃High, pass transistors 707-1 and 707-2 are enabled such that the DIGIT and DIGIT _ signals corresponding to the row Y data values are provided to the respective compute component nodes ST2 and SF 2. Thus, the value stored in compute component 731 (e.g., row X data value) can be flipped depending on the values of DIGIT and DIGIT _ such as row Y data value. In this example, if PASS is at time T₁₃Held low, pass transistors 707-1 and 707-2 are not enabled so that the DIGIT and DIGIT _ signals corresponding to the row Y data values remain isolated from nodes ST2 and SF2 of compute component 731. Thus, the data values in the compute component (e.g., row X data values) will remain the same. In this example, if PASS at time T₁₃High, then swap transistor 742 is enabled so that the DIGIT and DIGIT _ signals corresponding to the row Y data values will be provided to node SF2 in a transposed manner (e.g., "true" data values on DIGIT (n) and "supplemental" data values on DIGIT (n) _ will be provided to nodes ST2) to the respective compute component nodes ST2 and SF 2. Thus, the value stored in compute component 731 (e.g., row X data value) can be flipped depending on the values of DIGIT and DIGIT _ such as row Y data value. In this example, if PASS at time T₁₃Is kept low, thatThe swap transistor 742 is not enabled so that the DIGIT and DIGIT _ signals corresponding to the row Y data values remain isolated from nodes ST2 and SF2 of the compute component 731. Thus, the data values in the compute component (e.g., row X data values) will remain the same.

At time T₁₄TF and FT are disabled, which causes PASS and PASS to go low (or remain low), causing PASS transistors 707-1 and 707-2 and swap transistor 742 to be disabled. At time T₁₅ROW Y is disabled and PHASE 2R, PHASE2L and ISO are enabled. At time T₁₅Enabling PHASE 2R and PHASE2L enables feedback on the latch of the compute component 731 so that the result of the XOR operation (e.g., "a" XOR "B") is latched in the latch. At time T₁₅Enable ISO again couples nodes ST2 and SF2 to the gates of enable transistors 752, 754, 762, and 764. At time T₁₆The sensing amplifier 706 is disabled (e.g., SENSE AMP goes low) and equilibration is enabled (e.g., EQ goes high so that DIGIT and DIGIT _ are driven to an equilibrium voltage).

The result of the XOR operation, which is initially stored in compute component 731 in this example, may be transferred back to the memory array (e.g., via complementary sense lines back to memory cells coupled to row X, row Y, and/or a different row) and/or transferred to an external location (e.g., an external processing component) via I/O lines.

Fig. 10 also includes (e.g., at 1001) signaling associated with shifting data (e.g., from a compute component 731 to a neighboring compute component 731). The example shown in FIG. 10 illustrates two shifts to the right, such that data values stored in compute components corresponding to column "N" are shifted to the right to compute components corresponding to column "N + 2". E.g. at time T₁₆As shown, PHASE 2R and PHASE2L are disabled, which disables feedback on the compute component latches, as described above. To perform the first shift right, PHASE1R is at time T₁₇Is enabled and at time T₁₈And (4) stopping the use. Enabling PHASE1R causes transistor 781 to conduct, which causes the data value at node ST1 to move to the right to node ST2 of the right neighboring compute component 731. PHASE 2R then at time T₁₉Is enabled and at time T₂₀And (4) stopping the use. Enabling the PHASE 2R cause transistor786 is on, which causes the data value from node SF1 to move to the right to node SF2, completing the shift to the right.

The above sequence (e.g., enable/disable PHASE1R and then enable/disable PHASE 2R) may be repeated to achieve the desired number of right shifts. For example, in this example, by at time T₂₁Enable PHASE1R and at time T₂₂The PHASE1R is disabled to perform the second right shift. PHASE 2R then at time T₂₃Enabled to complete the second right shift. After the second right shift, PHASE1R remains disabled, PHASE 2R remains enabled, and PHASE2L is enabled (e.g., at time T)₂₄) Such that feedback is enabled to latch the data value in the compute component latch.

Although the examples described in fig. 9 and 10 include the logical operation results being stored in a compute component (e.g., 371), the sense circuitry according to embodiments described herein is operable to perform the logical operation if the results are initially stored in the sense amplifier (e.g., as illustrated in fig. 9). Moreover, embodiments are not limited to the "AND" AND "XOR" logical operation examples described in FIGS. 9 AND 10, respectively. For example, sensing circuitry (e.g., 750 shown in fig. 7) according to embodiments of the disclosure may be controlled to perform various other logical operations, such as those shown in table 10-2.

Although example embodiments including various combinations and configurations of sense circuits, sense amplifiers, compute components, dynamic latches, isolation devices, and/or shift circuits have been illustrated and described herein, embodiments of the present disclosure are not limited to those combinations explicitly recited herein. Other combinations and configurations of the sensing circuits, sense amplifiers, compute components, dynamic latches, isolation devices, and/or shift circuits disclosed herein are expressly included within the scope of this disclosure.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. The scope of one or more embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing detailed description, certain features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims (30)

1. An apparatus, comprising:

an array of memory cells, wherein the array comprises:

a first portion accessible by a controller of the array and inaccessible by a device external to the apparatus;

a second portion accessible to the device external to the apparatus; and

a number of registers configured to store row addresses indicating which portion of the array is the first portion; and is

The controller is configured to access the number of registers to allow the device external to the apparatus to access the second portion based on the stored row address.

2. The apparatus of claim 1, wherein the number of registers comprises an access control register.

3. The apparatus of claim 2, wherein the access control register comprises a row access control register.

4. The apparatus of claim 1, wherein the controller is configured to:

allowing instructions stored in the first portion to be executed to write to or read from the second portion; and

instructions are not allowed to be executed from the second portion.

5. The apparatus of claim 1, wherein the number of registers are writable only by instructions executed from the first portion.

6. The apparatus of claim 1, wherein the controller is configured to allow data to be copied into the first portion only by executing the instructions executed from the first portion.

7. The apparatus of claim 1, wherein the controller is configured to prevent an external DRAMACT command from executing inside the first portion in response to the register being loaded.

8. The apparatus of claim 1, wherein the controller is configured to prevent internal PIM instruction commands from executing outside the first portion in response to the register being loaded.

9. The apparatus of claim 1, wherein the controller is configured to allow instructions to execute from the second portion only in response to the instructions not targeting in the first portion.

10. The apparatus of claim 1, wherein the controller is configured to prevent data from being copied from the first portion to the second portion in response to execution of an instruction not stored in the first portion.

11. The apparatus of claim 1, wherein the controller is configured to prevent data from being copied from the second portion to the first portion in response to execution of an instruction not stored in the first portion.

12. The apparatus of any one of claims 1-11, wherein the apparatus is a processor-built-in-memory PIM device comprising:

the array of the memory cells; and

the controller;

wherein the array and the controller are on the same die.

13. The apparatus of claim 12, wherein a host computer is coupled to the PIM device and is one of the devices external to the apparatus.

14. The apparatus of any one of claims 1-11, wherein the number of registers are configured to each store an address associated with a row of the array.

15. The apparatus of claim 14, wherein the portion of the array between the addresses stored in each of the number of registers is the first portion.

16. The apparatus of claim 14, wherein the first portion of the array is modified in response to the address associated with each of the number of registers being modified.

17. An apparatus, comprising:

an array of memory cells, comprising:

a first portion of a memory unit that is inaccessible to a device external to the apparatus and configured to store a first set of data and a set of instructions;

a second portion of memory cells accessible by the device external to the apparatus and configured to store a second set of data; and

a set of address registers, wherein the set of address registers indicates which portion of the array is the inaccessible first portion; and

a controller configured to execute the first set of instructions in the inaccessible first portion.

18. The apparatus of claim 17, wherein the accessible second portion comprises another set of instructions executed by the controller without reading or writing data into the first inaccessible portion of memory cells.

19. The apparatus of claim 17, wherein the controller is configured to communicate data from the inaccessible first portion to the accessible second portion.

20. The apparatus of any one of claims 17-19, wherein the controller is configured to recognize data written to the accessible second portion as an operand and not recognize the data as an instruction.

21. The apparatus of any one of claims 17-19, wherein the controller is configured to recognize data written to the inaccessible first portion as one of an operand and the set of instructions.

22. The apparatus of claim 21, wherein the controller is configured to execute the set of instructions in the inaccessible first portion.

23. The apparatus of claim 20, wherein the accessible second portion of memory cells is configured to store a second set of instructions, wherein the second set of instructions is executed without reading or writing data into the first inaccessible portion of memory cells.

24. A method, comprising:

reading addresses in a plurality of registers;

identifying a first portion of the memory cell array indicated by the read address;

executing instructions stored in the first portion within memory cells of the first portion;

preventing access to the first portion; and

access to a second portion of the array is allowed.

25. The method of claim 24, comprising modifying the addresses in the number of registers, which modifies which memory cells of the array make up the first portion.

26. The method of any one of claims 24-25, wherein a first address of a first one of the number of registers indicates a first row of cells of the first portion.

27. The method of claim 26, wherein a second address of a second register of the number of registers indicates a last cell row of the first portion.

28. The method of claim 26, comprising:

decrypting data as the data is initially read and written into the first portion; and

leaving the data unencrypted in the first portion.

29. The method of any one of claims 24 to 25, comprising clearing data from the first portion in response to performing a system reset.

30. The method of claim 29, comprising clearing the number of registers in response to performing the system reset.

Images