CN111049575B - Real-time run-length detection system and method for bus type high-speed random number source - Google Patents
Real-time run-length detection system and method for bus type high-speed random number source Download PDFInfo
- Publication number
- CN111049575B CN111049575B CN201811182571.6A CN201811182571A CN111049575B CN 111049575 B CN111049575 B CN 111049575B CN 201811182571 A CN201811182571 A CN 201811182571A CN 111049575 B CN111049575 B CN 111049575B
- Authority
- CN
- China
- Prior art keywords
- random number
- detection
- module
- detection unit
- serial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/70—Photonic quantum communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
- H04L9/0852—Quantum cryptography
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electromagnetism (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses a real-time run length detection method and a real-time run length detection system of a bus type high-speed random number source, wherein a data stream copying module copies random number streams output by the bus type high-speed random number source into three parts, one part is used for being input into a random number application module, the other two parts are respectively used for a first detection module and a second detection module, the first detection module detects whether the random number streams output in the same clock period have a plurality of continuous 0 or 1 exceeding a safety threshold value, the second detection module detects whether the link ends of two adjacent random number streams output in two adjacent clock periods have a plurality of continuous 0 or 1 exceeding the safety threshold value along with the time accumulation of the random number streams output by the same data line. The technical scheme of the invention can be used for the real-time run-length detection of the 10 Gbps-level bus type high-speed random number source.
Description
Technical Field
The invention relates to the technical field of random number detection, in particular to a real-time run-length detection system and method of a bus type high-speed random number source.
Background
The high-speed quantum key distribution equipment based on the BB84 decoy state protocol needs to adopt a high-speed random number source to encode and send out random light pulses. Taking 2GHz luminescence pulse frequency (not the band frequency of the optical signal itself, but the interval frequency of the luminescence pulse) as an example, each luminescence pulse adopts 5bits to perform luminescence coding, wherein 3bits is used to perform proportional coding of a signal state, a decoy state and a vacuum state, and in addition, 2bits is used to code different polarization states of HVPN, so that a high-speed random number source of at least 10Gbps is required. PN is X basis vector, HV is Z basis vector, and X and Z are matrixes defined in quantum mechanics.
The prior art is all a technical scheme for completing the real-time run-length detection of random numbers below the highest Gbps magnitude and is not related to the real-time run-length detection of a 10Gbps magnitude bus type high-speed random number source in the field of quantum secret communication.
Disclosure of Invention
In order to solve the problems, the technical scheme of the invention provides a real-time run-length detection method and a real-time run-length detection system for a bus type high-speed random number source, which can be used for the real-time run-length detection of the bus type high-speed random number source with the magnitude of 10 Gbps.
In order to achieve the above purpose, the invention provides the following technical scheme:
a real-time run-length detection system of a bus-type high-speed random number source comprises:
the data flow copying module is used for copying the random number flow output by the bus type high-speed random number source and outputting three random number flows; one part of the random number stream output by the data stream copying module is used for being independently input to a random number application module;
a first detection module, configured to separately obtain a portion of the random number stream output by the data stream replication module, detect whether the random number stream output in a same clock cycle has multiple consecutive 0s or 1s exceeding a safety threshold, and detect whether a connection end of two adjacent random number streams output in two adjacent clock cycles has multiple consecutive 0s or 1s exceeding the safety threshold;
and the second detection module is used for separately acquiring one random number stream output by the data stream copying module and detecting whether the random number stream output by the same data line has a plurality of continuous 0 or 1 exceeding the safety threshold value or not when accumulated over time.
Preferably, in the real-time run-length detection system, the bus-type high-speed random number source has n parallel data lines; each data line in each clock period respectively outputs a random number to form the random number stream with n-bit random numbers; n is a positive integer greater than 1;
the n-bit random number of the random number stream output by each clock cycle is sequentially a 1 st-nth bit random number.
Preferably, in the above real-time run-length detection system, the first detection module includes: the serial detection units are sequentially a 1 st serial detection unit to an nth serial detection unit;
the random number stream output by any clock cycle enters a 1 st serial detection unit in the clock cycle, and the random number stream is shifted into a next serial detection unit every time one clock cycle is passed until the random number stream is shifted into the nth serial detection unit; the ith serial detection unit is used for detecting the attribute value of the (n-i + 1) th bit random number of the random number stream, after the detection result is updated, shifting and discarding the (n-i + 1) th bit random number, and latching other random numbers of the random number stream into the (i + 1) th serial detection unit, wherein i is a positive integer, and i is more than or equal to 1 and less than or equal to n-1.
Preferably, in the real-time run-length detection system, the serial detection unit has a counter and a register set;
the counter is used for accumulating the detection result by 1 when the last-bit random number stored by the corresponding serial detection unit is the same as the last-bit random number attribute value stored by the previous serial detection unit, and setting the detection result to zero when the last-bit random number attribute values are different.
Preferably, in the real-time run-length detection system, in the jth serial detection unit, the register group has n-j +1 registers, j is a positive integer, and j is greater than or equal to 1 and less than or equal to n.
Preferably, in the real-time run-length detection system, the safety threshold is a, a is a positive integer, and 1 < a < n;
the a +1 th serial detection unit-the nth serial detection unit are respectively connected with the abnormal signal convergence module;
in the a +1 th serial detection unit-the nth serial detection unit, when any serial detection unit detects that the detection result is greater than a, a first alarm signal is sent to the abnormal signal convergence module;
the abnormal signal convergence module is configured to generate first indication information based on the first alarm signal, where the first indication information is used to indicate that the random number stream output in the same clock cycle has a plurality of consecutive 0s or 1s exceeding the safety threshold.
Preferably, in the real-time run-length detection system, the nth serial detection unit is further connected with the splicing position judgment module;
after the nth serial detection unit finishes the detection of the attribute value of the nth bit random number of the random number stream corresponding to one clock cycle, if the detection result is not equal to zero, in a plurality of subsequent consecutive clock cycles which do not exceed a, if the corresponding detection result is greater than a, the detection result is sent to the splicing part judgment module, the splicing part judgment module is used for sending a second alarm signal to the abnormal signal aggregation module based on the detection result, the abnormal signal aggregation module generates second indication information based on the second alarm signal, and the second indication information is used for indicating that the splicing end of two adjacent random number streams output by two adjacent clock cycles has a plurality of consecutive 0 or 1 which exceed the safety threshold.
Preferably, in the real-time run-length detection system, the second detection module includes n parallel detection units;
and each parallel detection unit correspondingly detects the attribute value of the random number output by one data line so as to update the detection result.
Preferably, in the real-time run-length detection system, the parallel detection unit includes a counter, and the counter is configured to accumulate the detection result by 1 when the attribute value of the random number output by the data line corresponding to the current clock cycle is the same as the attribute value of the random number output by the previous clock cycle, and set the detection result to zero when the attribute value of the random number output by the previous clock cycle is different.
The invention also provides a real-time run length detection method of the bus type high-speed random number source, which is used for the real-time run length detection system, and the real-time run length detection method comprises the following steps:
copying a random number stream output by the bus type high-speed random number source, and outputting three random number streams;
the method comprises the steps that one part of random number stream is independently input into a random number application module, the other two parts of random number stream are respectively input into a first detection module and a second detection module, whether the random number stream output in the same clock cycle has a plurality of continuous 0 or 1 exceeding a safety threshold value is detected through the first detection module, whether the connection end of two adjacent random number streams output in two adjacent clock cycles has a plurality of continuous 0 or 1 exceeding the safety threshold value is detected, and whether the random number stream output in the same data line has a plurality of continuous 0 or 1 exceeding the safety threshold value along with time accumulation is detected through the second detection module.
As can be seen from the above description, in the real-time run-length detection method and system for a bus-type high-speed random number source provided in the embodiments of the present invention, a data stream copying module copies three random number streams output by the bus-type high-speed random number source, one stream is used for being input to a random number application module, the other two streams are respectively used for a first detection module and a second detection module, the first detection module detects whether a random number stream output in a same clock cycle has a plurality of consecutive 0s or 1s exceeding a safety threshold, and detects whether a linking end of two adjacent random number streams output in two adjacent clock cycles has a plurality of consecutive 0s or 1s exceeding the safety threshold, and the second detection module detects whether a random number stream output in a same data line has a plurality of consecutive 0s or 1s exceeding the safety threshold as time accumulates. The technical scheme of the invention can be used for the real-time run-length detection of the 10 Gbps-level bus type high-speed random number source.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a 10Gbps bus-type high-speed random number source according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a real-time run-length detection system of a bus-type high-speed random number source according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first detection module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another first detection module according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a second detection module according to an embodiment of the present invention;
fig. 6 is a schematic flow chart of a real-time run-length detection method for a bus-type high-speed random number source according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description thereof.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a 10Gbps bus-type high-speed random number source according to an embodiment of the present invention, which includes 100 data lines, each data line outputs a random number of one bit in the same clock cycle, so as to form a random number stream with 100bits of random numbers, where the 100bits of random numbers in the random number stream are respectively a 1 st bit random number rn _0 to a 100 th bit random number rn _99; the device is provided with a clock signal line, which is used for inputting a clock signal clk _100m, and takes a random number source with a working clock of 100MHz and a bus bit width of 100bits as an example, the output rate of each data line is 100Mbps, and 100 data lines output 10Gbps random numbers per second under the control of a synchronous clock of 100 MHz; there is a reset signal line for inputting a reset signal rst _ n.
In the process of random number luminous coding, 100bits output in each clock period need to be changed into serial use, so that the real-time run length detection needs to be carried out on the random number stream output by the bus type high-speed random number source.
The embodiment of the present invention provides a real-time run length detection system for the bus-type high-speed random number source, the real-time run length detection system is shown in fig. 2, fig. 2 is a schematic structural diagram of the real-time run length detection system for the bus-type high-speed random number source provided by the embodiment of the present invention, and the real-time run length detection system includes: the data stream copying module 11 is configured to copy a random number stream output by the bus-type high-speed random number source, and output three copies of the random number stream; a part of the random number stream output by the data stream copying module 11 is used for being input to a random number application module 12 separately; a first detecting module 13, where the first detecting module 13 is configured to separately obtain one random number stream output by the data stream copying module 11, detect whether the random number stream output in the same clock cycle has multiple consecutive 0s or 1s exceeding a safety threshold, and detect whether a connection end of two adjacent random number streams output in two adjacent clock cycles has multiple consecutive 0s or 1s exceeding the safety threshold; a second detection module 14, where the second detection module 14 is configured to separately obtain a copy of the random number stream output by the data stream replication module 11, and detect whether the random number stream output by the same data line has a plurality of consecutive 0s or 1s exceeding a safety threshold accumulated over time.
The data flow copying module 11 is connected to each output port of the bus-type high-speed random number source, and is configured to obtain random numbers output by all data lines to obtain a random number flow output by the data lines, and the data flow copying module and the data lines share the same clock signal clk _100m and the same reset signal rst _ n for signal line reduction. The data stream copying module 11 obtains the data stream output by the bus-type high-speed random number source, and copies the data stream into three parts, wherein one part is used for the random number application module 12, and the other two parts are respectively used for the first detection module 13 and the second detection module 14 to perform the related detection of the random number stream.
In the real-time run-length detection system according to the embodiment of the present invention, the first detection module 13 may detect:
1) Whether excessive continuous 0 or excessive continuous 1 exist in the 100bits data stream output by the bus type high-speed random number source in each clock cycle;
2) Whether the connection end of the 100-bit data stream output in the previous clock cycle and the connection end of the 100-bit data stream output in the next clock cycle has too many continuous 0 or too many continuous 1.
In the real-time run-length detection system according to the embodiment of the present invention, the second detection module 14 may detect:
3) Each data line in a bus-type high speed random number source accumulates over time whether there are too many consecutive 0s or too many consecutive 1 s.
The purpose of the detection with respect to 1) and 2) is: the run-length property of the serial data is obtained after 100 × 100Mbps parallel random number output at high speed is converted into 10Gbps serial. If the random number run characteristic of each data line in the bus type high-speed random number source is good, but the run characteristic of 100 data lines after being connected in parallel and in series is not appropriate, detection and early warning can be realized through 1) and 2) detection, so that 100bits output in each clock period still have good random characteristics after being changed into serial use in the process of random number luminous coding.
The purpose of the detection of 3) is: the run-length characteristic of the random number output by each data line prevents the random number source corresponding to a certain data line from generating problems, such as non-working or poor contact, and the like, and the detection processes of 1) and 2) can not detect the phenomenon of generating the problems.
The real-time run-length detection system is used for real-time run-length detection of a bus-type high-speed random number source, and the bus-type high-speed random number source is provided with n parallel data lines; each data line outputs a random number in each clock period to form a random number stream with n-bit random numbers; n is a positive integer greater than 1; the n-bit random number of the random number stream output in each clock cycle is sequentially the 1 st-nth bit random number. In the real-time run-length detection system according to the embodiment of the present invention, an implementation manner of the first detection module 13 and the second detection module 14 is described by taking n =100 as an example. It should be noted that the value of n includes, but is not limited to, 100, that is, it can be used for a bus-type high-speed random number source with a magnitude of 10Gbps, and can also be used for a bus-type high-speed random number source with other magnitudes.
When n =100, 100bits of random number is generated in each clock cycle, and the 100MHz working clock generates 10Gbps of random number in each second. Aiming at detection purpose 1), if judging whether each group of 100bits in the same clock period has excessive continuous 0 or excessive continuous 1, a common synchronous sequential circuit is adopted, and 100 clock periods are needed. If the most basic 100-bit packet takes 100 clock cycles to count to obtain a result, and then the run-length characteristic of the 100-bit packet corresponding to the next clock cycle is counted, 10G clock cycles are required for 10Gbps data generated in 1s, that is, 100s time, and the purpose of real-time detection cannot be achieved obviously. In order to solve the problem, in the embodiment of the present invention, when the detection object 1) is implemented, a mode of combining pipeline statistics and a shift register is adopted, and a structure of a first detection module is designed as shown in fig. 3.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a first detection module according to an embodiment of the present invention, where the first detection module includes: n serial detection units 31, the n serial detection units 31 being the 1 st serial detection unit to the nth serial detection unit in sequence;
the random number stream output by any clock cycle clk enters the 1 st serial detection unit when the clock cycle clk passes, and the random number stream is shifted into the next serial detection unit 31 after every clock cycle clk until the random number stream is shifted into the nth serial detection unit; the ith serial detection unit is used for detecting the attribute value of the (n-i + 1) th bit random number of the random number stream, after the detection result is updated, shifting and discarding the (n-i + 1) th bit random number, and latching other random numbers of the random number stream into the (i + 1) th serial detection unit, wherein i is a positive integer, and i is more than or equal to 1 and less than or equal to n-1. After the nth serial detection unit detects the 1 st bit random number of the random number stream corresponding to one clock cycle, the detection result is fed back to the statistics completion module 33. In a random number stream corresponding to one clock cycle, for example, n =100, the 1 st bit random number is rn _99, and the 100 th random number is rn _0.
As shown in fig. 3, when n =100, at any clock cycle clk, the 100bits of random number stream newly generated by the bus-type high-speed random number source has 100bits of random numbers, the random number stream enters the 1 st serial detection unit, 99 groups of random number streams corresponding to 99 clock cycles before the clock cycle respectively complete the detection of the last bit in the corresponding serial detection unit 31, after the detection result is updated, the detected last bit is discarded by shifting, and the rest of random numbers are latched and enter the next serial detection unit 31.
That is, the detection of the random number stream corresponding to the first clock cycle with respect to the detection object 1) is completed in the 100 th clock cycle, and it can be detected whether the random number stream corresponding to the first clock cycle has too many consecutive 0s or too many consecutive 1s, and the detection of the random number stream corresponding to one clock cycle with respect to the detection object 1) is completed every one clock cycle after the 100 th clock cycle.
In the first detection module, the serial detection units 31 are connected in series, each serial detection unit 31 can realize the functions of receiving and latching the statistical result of the previous serial detection unit 31, counting the 01 characteristic of the last bit 1bit random number, discarding the last bit 1bit just counted by the shift register, updating the 01 statistical result and outputting the statistical result to the next serial detection unit 31, and alarming when the continuous 0 or 1 exceeds the threshold value a, the serial detection units 31 are connected in series by 100 to form the pipeline structure shown in fig. 3.
In the embodiment of the present invention, each serial detection unit 31 has a counter and a register set. The counter is configured to accumulate the detection result by 1 when the last-bit random number stored by the corresponding serial detection unit 31 is the same as the last-bit random number attribute value stored by the previous serial detection unit 31, and set the detection result to zero when the last-bit random number attribute values are different. Specifically, in the jth serial detection unit, the register group has n-j +1 shift registers 32, j is a positive integer, and j is greater than or equal to 1 and less than or equal to n. The jth serial detection unit is configured to detect an attribute value of an n-j +1 th bit random number in the random number stream corresponding to a clock cycle clk.
By adopting the pipeline structure, the 100bits random number stream corresponding to each clock cycle sequentially flows through 100 serial detection units 31 through 100 clock cycles, and the run-length characteristic of the random number stream in the current serial detection unit 31 can be obtained after the operation of discarding the last bit after counting the 01 attribute value of the last bit 1bit each time. During the whole detection process, if a plurality of continuous 0 or a plurality of continuous 1 exceeding the safety threshold value are found in the middle, an alarm is given. If a plurality of continuous 0 or a plurality of continuous 1 exceeding the safety threshold are not found until the last 100bits random number stream is detected, the random number stream corresponding to the clock period passes the run length detection, and the detection result of the last serial detection unit is that the tail of the random number stream corresponding to the clock period and a section of random number of continuous 0 or 1 of the random number stream connection end corresponding to the next period are used for detecting the detection of the purpose 2).
Due to the pipeline result, 100 groups of random number streams output in the last 100 clock cycles of each clock cycle complete the 01 attribute value detection of the corresponding last-bit random number in the serial detection unit 31. The group of 100bits random numbers in the 100 th serial detection unit has completed 99 times of detection statistics of the first 99bits in the previous stage, the group of 100bits random numbers in the 99 th serial detection unit has completed 98 times of detection statistics of the first 98bits in the previous stage, …, the group of 100bits random numbers in the 2 nd serial detection unit has completed 1 time of detection statistics of the first 1bit in the previous stage, the 1 st serial detection unit has just completed receiving a 100bits random number stream corresponding to a new clock cycle, and is ready to start the 1 st detection statistics.
In the embodiment of the invention, although 100 clock cycles are needed for the 100-bit random number stream corresponding to each clock cycle to complete the detection purpose 1), after the pipeline runs, the 100 th clock cycle starts, and each clock cycle has a new group of 100-bit random number streams to complete the detection purpose 1) detection statistics, so that the detection statistical result can reach the statistical speed of 10Gbps, and the real-time run detection capability of 10Gbps is realized.
In order to implement real-time alarm detection of detection purposes 1) and 2), a structure of the first detection module according to the embodiment of the present invention may be as shown in fig. 4 on the basis of that shown in fig. 3, where fig. 4 is a schematic structural diagram of another first detection module provided in the embodiment of the present invention.
Setting the safety threshold value as a, wherein a is a positive integer, and a is more than 1 and less than n. The a +1 th serial detection unit to the nth serial detection unit are respectively connected with the abnormal signal convergence module 41; in the a +1 th serial detection unit to the nth serial detection unit, when any serial detection unit 31 detects that the detection result is greater than a, a first alarm signal is sent to the abnormal signal convergence module 41; the anomaly signal converging module 41 is configured to generate first indication information based on the first alarm signal, where the first indication information is used to indicate that a plurality of consecutive 0s or 1s in the random number stream output in the same clock cycle exceed a safety threshold. In the embodiment shown in fig. 4, n =100 is still used as an example for description, and in an actual product, the value of n and the number of shift registers 32 in each serial detection unit may be selected according to the number of bits of the random number in the random number stream.
The nth serial detection unit is also connected with the splice judgment module 42. After the nth serial detection unit completes the detection of the attribute value of the nth bit random number of the random number stream corresponding to one clock cycle, when the detection result is not equal to zero, in a plurality of subsequent consecutive clock cycles not exceeding a, if the detection result corresponding to the nth bit random number is greater than a, the detection result is sent to the splice judgment module 42, the splice judgment module 42 is configured to send a second alarm signal to the abnormal signal convergence module 41 based on the detection result, the abnormal signal convergence module 41 generates second indication information based on the second alarm signal, and the second indication information is used to indicate that the splice end of two adjacent random number streams output in two adjacent clock cycles has a plurality of consecutive 0s or 1s exceeding a safety threshold.
And finishing detection statistics after the random number stream of 100bits corresponding to any clock period passes through the subsequent 100 clock periods. In the 100 th subsequent clock cycle of the clock cycle, the 1 st bit random number of the corresponding random number stream in the nth serial detection unit completes 01 attribute value detection statistics, and completes detection purpose 1).
The front a serial detection units 31 detect and count 01 statistical results of the lowest a bits of the 100bits random number stream RN _ New [99] corresponding to the just input clock cycle. When the lowest bit RN _ New [0] is 0, recording the bit value, counting the number of continuous 0 from RN _ New [0] to RN _ New [ a-1] and latching the counting result New _ Head _ Cnt; when the lowest bit RN _ New [0] is 1, the bit value is recorded, and the statistics of how many consecutive 1's are from RN _ New [0] to RN _ New [ a-1] are counted and the statistics New _ Head _ Cnt is latched. When RN _ New [99] goes through 99 clock cycles, only the last RN _ New [99] remains without participating in the run-length detection statistic, the 100-bit random number packet RN _ Old [99] one clock cycle before RN _ New [99] has completed the run-length detection statistic, and the last statistic is the number of bits Old _ Tail _ Cnt whose upper part of RN _ Old [99] is consistent with the value of RN _ Old [99] bit. RN _ New [ 99. Fusing the statistical results of the RN _ Old [99] and the RN _ New [0] to obtain a result, accumulating the statistical counts of the RN _ Old [99] and the RN _ New [0] and judging whether the accumulated sum exceeds a threshold value a or not, and triggering a run detection abnormal alarm if the accumulated sum exceeds the threshold value a; and if the values of the RN _ Old [99] bit and the RN _ New [0] bit are not consistent, no alarm is given.
Based on the above description, the implementation process of any two adjacent clock cycle link ends with respect to the detection purpose 2) includes:
after the random number stream corresponding to the previous clock cycle completes the detection object 1), the 1 st bit random number corresponding to the random number stream in the clock cycle completes the detection statistics of the 01 th attribute value in the nth serial detection unit, and the two results are obtained, wherein one is the accumulated detection result about the random number 1 counted last in the clock cycle, and the other is the accumulated detection result about the random number 0, and the detection result is recorded.
In the process of carrying out the detection purpose 1) correspondingly in the next clock period, at most a-1 times of detection is carried out, and the detection purpose 2) can be completed. After the random number stream corresponding to the next clock cycle starts to be detected, the 01 attribute of the random number stream is the same as the 01 attribute value of the last time of the previous clock cycle, and the sum of the accumulated detection result of the 01 attribute and the accumulated detection result of the 01 attribute value of the last time of the previous cycle is greater than the safety threshold, which indicates that the connection end of the two adjacent clock cycles has too many continuous 0s or too many continuous 1s exceeding the safety threshold. The accumulated detection result of 01 attribute of the next clock cycle is the detection result including the last bit random number in the corresponding random number stream, if the accumulated detection result does not include the 01 attribute value indicating that the last bit random number of the random number stream corresponding to the next clock cycle is different from the first bit random number of the previous clock cycle, that is, the join end of the two adjacent clock cycles does not have too many consecutive 0s or too many consecutive 1s exceeding the safety threshold.
In this embodiment of the present invention, a structure of the second detection module may be as shown in fig. 5, where fig. 5 is a schematic structural diagram of the second detection module provided in this embodiment of the present invention, and the second detection module includes n parallel detection units 51; each of the parallel detection units 51 correspondingly detects an attribute value of the random number output by one of the data lines to update the detection result. The parallel detection unit 51 includes a counter configured to add 1 to the detection result when the attribute value of the random number output by the data line corresponding to the current clock cycle is the same as the attribute value of the random number output by the previous clock cycle, and set the detection result to zero when the attribute value of the random number output by the previous clock cycle is different from the attribute value of the random number output by the previous clock cycle. If the accumulated detection result exceeds the safety threshold, the parallel detection unit 51 sends a third alarm signal to the abnormal signal convergence module 41, and the abnormal signal convergence module 41 generates third indication information based on the third alarm signal, where the third indication information is used to indicate that the random number stream output by the same data line has a plurality of consecutive 0s or 1s exceeding the safety threshold accumulated over time.
As can be seen from the above description, in the embodiment of the present invention, the first detection module connected in series in the transverse direction and the second detection module connected in parallel in the longitudinal direction can respectively implement the detection of the runs in the transverse direction and the longitudinal direction, and implement the real-time run detection of the 10Gbps bus-type random number source. Whether serial 10Gbps random number streams have multiple continuous 0 or multiple continuous 1 with an ultra-safe threshold value in the actual use process after parallel-serial conversion or a single data line has multiple continuous 0 or multiple continuous 1 with the ultra-safe threshold value accumulated along with time, the serial 10Gbps random number streams can be detected by the technical scheme of the embodiment of the invention and alarm is given.
In the embodiment of the invention, the random number stream corresponding to each clock period does not need to be segmented, can be continuously input and has no limit on the length of a processing segment; the invention discloses a bus type high-speed random number source, which is characterized in that a random number stream output by a bus type high-speed random number source is converted into a serial random number stream in a using mode in a random number application program, and the special technical scheme for detecting the parallel-serial 10Gbps magnitude random number stream is to realize pipelined detection statistics through a first detection module with a pipeline and a shift register 32, so that the detection statistics of 01 attribute values of the same clock cycle and the detection statistics of 01 attribute values of two adjacent clock cycle link ends can be realized; the technical scheme of the embodiment of the invention is not limited to be realized by FPGA, but can also be realized in ASIC, DSP, ARM, CPU or other computing chips; in the embodiment of the present invention, parameters such as 10Gbps magnitude, 100bits bit wide data bus, 100MHz clock frequency, etc. are set only for convenience of expression, and actually using this idea, run length detection of a bus type random number source with higher speed/low speed and higher bit wide/low bit wide can be realized, for example: if the data bus is 32bits wide and the operation clock is 200MHz, a 32-level pipeline structure is adopted under 200MHz working frequency, and real-time run length detection can be realized for the random number source of 6.4 Gbps; the threshold value a of the number of consecutive 0s or 1s in the embodiment of the present invention may be set arbitrarily, and for example, 10 consecutive 0s or 1s, 20 consecutive 0s or 1s, 32 consecutive 0s or 1s, 48 consecutive 0s or 1s, and the like may be detected.
As can be seen from the above description, the technical scheme of the embodiment of the invention realizes the real-time run-length detection of the 10Gbps bus-type high-speed random number source in the quantum secret communication QKD system. The technical scheme of the embodiment of the invention has very high processing bandwidth, can be used for any equipment needing a high-speed random number source except quantum secret communication, and can continuously input the input random number without segmentation and without the limitation of processing segment length. The technical scheme of the embodiment of the invention has good real-time performance, can report the abnormity in dozens of clock cycles after the random number with problems is output, and has the reaction time within 1 us. The technical scheme of the embodiment of the invention can support the run detection requirement of almost any bit width, any rate and any continuous 01 detection threshold value.
Based on the foregoing embodiment, another embodiment of the present invention further provides a real-time run-length detection method, used in the real-time run-length detection system described in the foregoing embodiment, where the real-time run-length detection method is shown in fig. 6, and fig. 6 is a schematic flow diagram of a real-time run-length detection method for a bus-type high-speed random number source provided in the foregoing embodiment of the present invention, where the real-time run-length detection method includes:
step S11: copying a random number stream output by the bus type high-speed random number source, and outputting three parts of the random number stream;
step S12: and independently inputting one part of the random number stream into a random number application module, and respectively inputting the other two parts of the random number stream into a first detection module and a second detection module.
The method comprises the steps that whether the random number stream output in the same clock cycle has a plurality of continuous 0 or 1 exceeding a safety threshold value or not is detected through a first detection module, whether the connecting ends of two adjacent random number streams output in two adjacent clock cycles have a plurality of continuous 0 or 1 exceeding the safety threshold value or not is detected, and whether the random number stream output in the same data line has a plurality of continuous 0 or 1 exceeding the safety threshold value or not is detected through a second detection module in a time accumulation mode.
The real-time run length detection method of the embodiment of the invention is used for detecting the real-time run length of a 10 Gbps-magnitude bus-type high-speed random number source; the processing bandwidth is very high, the method can be used for any equipment needing a high-speed random number source except quantum secret communication, the input random number does not need to be segmented, can be continuously input, and is not limited by the length of a processing segment; the real-time performance is good, the abnormity can be reported within dozens of clock cycles after the random number with problems is output, and the reaction time is within 1 us; the run detection requirement of almost any bit width, any rate and any continuous 01 detection threshold value can be supported.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the real-time run-length detection method disclosed by the embodiment, the description is relatively simple because the method corresponds to the system disclosed by the embodiment, and relevant points can be obtained by referring to the partial description of the real-time run-length detection system.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A real-time run-length detection system of a bus-type high-speed random number source is characterized by comprising:
the data flow copying module is used for copying the random number flow output by the bus type high-speed random number source and outputting three parts of the random number flow; one part of the random number stream output by the data stream copying module is used for being independently input to a random number application module;
a first detection module, configured to separately obtain a portion of the random number stream output by the data stream replication module, detect whether the random number stream output in a same clock cycle has multiple consecutive 0s or 1s exceeding a safety threshold, and detect whether a connection end of two adjacent random number streams output in two adjacent clock cycles has multiple consecutive 0s or 1s exceeding the safety threshold;
a second detection module, configured to separately obtain one of the random number streams output by the data stream replication module, and detect whether the random number streams output by the same data line have a plurality of consecutive 0s or 1s exceeding the safety threshold as accumulated over time;
the bus type high-speed random number source is provided with n parallel data lines; outputting a random number by each data line in each clock period to form the random number stream with n-bit random numbers; n is a positive integer greater than 1;
the n-bit random number of the random number stream output by each clock cycle is sequentially a 1 st bit random number to an nth bit random number;
the first detection module includes: the serial detection units are sequentially a 1 st serial detection unit to an nth serial detection unit;
the random number stream output by any clock cycle enters a 1 st serial detection unit in the clock cycle, and the random number stream is shifted into a next serial detection unit every time one clock cycle is passed until the random number stream is shifted into the nth serial detection unit; the ith serial detection unit is used for detecting the attribute value of the (n-i + 1) th bit random number of the random number stream, after the detection result is updated, shifting and discarding the (n-i + 1) th bit random number, and latching other random numbers of the random number stream into the (i + 1) th serial detection unit, wherein i is a positive integer, and i is more than or equal to 1 and less than or equal to n-1.
2. The real-time run-length detection system according to claim 1, wherein the serial detection unit has a counter and a register set;
the counter is used for accumulating the detection result by 1 when the last-bit random number stored by the corresponding serial detection unit is the same as the last-bit random number attribute value stored by the previous serial detection unit, and setting the detection result to zero when the last-bit random number attribute values are different.
3. The real-time run-length detection system of claim 2, wherein the j-th serial detection unit has n-j +1 registers, j is a positive integer, and j is greater than or equal to 1 and less than or equal to n.
4. The real-time run-length detection system of claim 2, wherein the safety threshold is a, a is a positive integer, and 1 < a < n;
the a +1 th serial detection unit-the nth serial detection unit are respectively connected with the abnormal signal convergence module;
in the a +1 th serial detection unit-the nth serial detection unit, when any serial detection unit detects that the detection result is greater than a, a first alarm signal is sent to the abnormal signal convergence module;
the abnormal signal convergence module is configured to generate first indication information based on the first alarm signal, where the first indication information is used to indicate that the random number stream output in the same clock cycle has a plurality of consecutive 0s or 1s exceeding the safety threshold.
5. The real-time run-length detection system according to claim 4, wherein the n-th serial detection unit is further connected to the splice judgment module;
after the nth serial detection unit finishes the detection of the attribute value of the nth bit random number of the random number stream corresponding to one clock cycle, if the detection result is not equal to zero, in a plurality of subsequent consecutive clock cycles which do not exceed a, if the corresponding detection result is greater than a, the detection result is sent to the splicing part judgment module, the splicing part judgment module is used for sending a second alarm signal to the abnormal signal aggregation module based on the detection result, the abnormal signal aggregation module generates second indication information based on the second alarm signal, and the second indication information is used for indicating that the splicing end of two adjacent random number streams output by two adjacent clock cycles has a plurality of consecutive 0 or 1 which exceed the safety threshold.
6. The real-time run-length detection system according to any one of claims 1 to 5, wherein the second detection module comprises n parallel detection units;
and each parallel detection unit correspondingly detects the attribute value of the random number output by one data line so as to update the detection result.
7. The system of claim 6, wherein the parallel detection unit comprises a counter, and the counter is configured to accumulate the detection result by 1 when the attribute value of the random number output by the data line corresponding to the current clock cycle is the same as the attribute value of the random number output by the previous clock cycle, and set the detection result to zero when the attribute value of the random number output by the data line corresponding to the previous clock cycle is different from the attribute value of the random number output by the previous clock cycle.
8. A real-time run-length detection method of a bus-type high-speed random number source, which is used for the real-time run-length detection system according to any one of claims 1-7, wherein the real-time run-length detection method comprises the following steps:
copying a random number stream output by the bus type high-speed random number source, and outputting three random number streams;
the method comprises the steps that one part of random number stream is independently input into a random number application module, the other two parts of random number stream are respectively input into a first detection module and a second detection module, whether the random number stream output in the same clock cycle has a plurality of continuous 0 or 1 exceeding a safety threshold value is detected through the first detection module, whether the connection end of two adjacent random number streams output in two adjacent clock cycles has a plurality of continuous 0 or 1 exceeding the safety threshold value is detected, and whether the random number stream output in the same data line has a plurality of continuous 0 or 1 exceeding the safety threshold value along with time accumulation is detected through the second detection module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811182571.6A CN111049575B (en) | 2018-10-11 | 2018-10-11 | Real-time run-length detection system and method for bus type high-speed random number source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811182571.6A CN111049575B (en) | 2018-10-11 | 2018-10-11 | Real-time run-length detection system and method for bus type high-speed random number source |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111049575A CN111049575A (en) | 2020-04-21 |
| CN111049575B true CN111049575B (en) | 2023-01-31 |
Family
ID=70229235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811182571.6A Active CN111049575B (en) | 2018-10-11 | 2018-10-11 | Real-time run-length detection system and method for bus type high-speed random number source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111049575B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118377459A (en) * | 2024-06-21 | 2024-07-23 | 山东云海国创云计算装备产业创新中心有限公司 | Random number detection device and method, storage medium and electronic equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6675113B2 (en) * | 2002-03-26 | 2004-01-06 | Koninklijke Philips Electronics N.V. | Monobit-run frequency on-line randomness test |
| CN104461454A (en) * | 2013-09-14 | 2015-03-25 | 安徽量子通信技术有限公司 | High-speed true random number generating device |
| CN107038015B (en) * | 2016-11-18 | 2020-04-07 | 杭州电子科技大学 | High-speed true random number generator |
-
2018
- 2018-10-11 CN CN201811182571.6A patent/CN111049575B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111049575A (en) | 2020-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108123813B (en) | Transmission method and device for operation, administration and maintenance OAM data | |
| US6680970B1 (en) | Statistical methods and systems for data rate detection for multi-speed embedded clock serial receivers | |
| KR101104033B1 (en) | Forward error correction encoding for multiple link transmission compatible with 64b/66b scrambling | |
| CN108717353B (en) | True random number generation method and device with detection and correction functions | |
| US10236907B2 (en) | Forward error correction (FEC) emulator | |
| US8405529B2 (en) | Using bus inversion to reduce simultaneous signal switching | |
| US6983403B2 (en) | Detecting bit errors in a communications system | |
| CN111049575B (en) | Real-time run-length detection system and method for bus type high-speed random number source | |
| JP4831018B2 (en) | Parallel cyclic code generation apparatus and parallel cyclic code inspection apparatus | |
| CN101771525B (en) | High-speed digital communication line error code detection device and method | |
| JP4709526B2 (en) | Method and apparatus for generating a low bandwidth channel within a high bandwidth channel | |
| CN108768619B (en) | Working method of strong PUF circuit based on ring oscillator | |
| WO2018059604A1 (en) | Information transmission method, device, and computer storage medium | |
| Muthiah et al. | Implementation of high-speed LFSR design with parallel architectures | |
| CN107329915B (en) | Method and system for recovering low-speed data through high-speed SerDes interface | |
| CN102914375A (en) | Device and method for counting photons | |
| CN101047477A (en) | Signal degrade detecting method, signal restoration detecting method, devices for those methods, and traffic transmission system | |
| CN103220122A (en) | Variable parameter high-speed parallel frame synchronizer | |
| CN105721107B (en) | A kind of piecemeal calculates device and method of the CRC to improve clock frequency | |
| US20130077961A1 (en) | Techniques for generating low rate data patterns compliant with passive optical networks | |
| CN102025696A (en) | Parallel scrambling and descrambling processing device and method | |
| CN107431672B (en) | Data scrambling method and scrambling device | |
| US6959019B2 (en) | Aharmonic interleaving of forward error corrected (FEC) signals | |
| CN204883682U (en) | Multichannel pseudo -random signal generator | |
| CN115529210B (en) | Die-to-DIE SERDES interface scrambling method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |