CN111049388B - Quasi-resonance control circuit - Google Patents

Quasi-resonance control circuit Download PDF

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CN111049388B
CN111049388B CN201911240471.9A CN201911240471A CN111049388B CN 111049388 B CN111049388 B CN 111049388B CN 201911240471 A CN201911240471 A CN 201911240471A CN 111049388 B CN111049388 B CN 111049388B
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trigger
signal
gate
wave trough
unit circuit
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CN111049388A (en
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於昌虎
李依娇
刘洋
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Shenzhen Nanyun Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a quasi-resonance control circuit. The circuit sets the return difference of frequency (namely time) at the valley enable signal EN output by the PFM unit circuit. Remember the previous main switching tube MPAt the Nth trough, if frequencyIf the trend is increasing, the N +1 th wave trough can be selected to be opened, and the position of the EN signal is advanced by one return difference time, so that the Nth wave trough is kept to be opened; if the frequency tends to decrease, and the nth-1 valley may be selected to be turned on, then a delay time is delayed at the EN signal to keep the nth valley turned on. Only if the frequency change exceeds the return difference time, the (N + 1) th or (N-1) th trough is selected to be switched on. The circuit can solve the problem that the output ripple of the converter is increased due to the fact that the opening wave trough is switched back and forth.

Description

Quasi-resonance control circuit
Technical Field
The present invention relates to a switching power supply, and more particularly, to a control circuit for a switching power supply operating in a quasi-resonant mode.
Background
The flyback converter is widely applied to medium and small power off-line switching power supplies due to the advantages of low cost, simple topology and the like. Fig. 1 shows a circuit diagram 100 of a typical flyback converter. In the figure, LMFor exciting inductance, CAIs a clamping capacitor, RAIs a bleeder resistor, DAFor clamping diodes, MPAs a main switch tube, COSSParasitic capacitance, R, being the switching nodeSSampling resistance, N, for exciting inductor currentPIs the number of turns of the primary winding of the transformer, NSThe number of turns of the secondary winding of the transformer, DRIs a rectifier diode, COUTIs the converter output capacitance, unit 101 is the controller of the converter, unit 102 is the isolation feedback circuit. Controller 101 samples the resistance R by sampling the converter output voltage and currentSThe voltage drop realizes the dual-loop peak current mode control and determines the main switch tube MPWhen on and when off. MPThe excitation of the magnetic core of the transformer is realized in the switching-on stage, and the energy is stored in the transformer; mPAnd in the turn-off stage, the demagnetization of the magnetic core is realized, and the energy is output to a load end through the secondary winding.
Since the birth of switching power, high frequency, high power density and high efficiency have become the constant trend. When the flyback converter is applied to the ACDC field, high frequency is difficult. The reason is that the converter input voltage is high (typically in the range of 85V-265 VAC), and the switching loss increases with the frequency, resulting in a decrease in efficiency. The specific formula for the switching loss is as follows:
Figure GDA0002722112640000011
Figure GDA0002722112640000012
wherein, VDSIs the voltage of the switching node, VINThe converter input voltage. It can be seen that a larger converter input voltage increases the proportionality coefficient of the switching loss to the frequency f, and that a higher frequency causes more efficiency loss. Therefore, various techniques for reducing the switching loss have been developed in order to realize high frequency while ensuring efficiency. Among them, the quasi-resonance technology and the soft switching technology (zero-voltage switching-on, zero-current switching-off) are widely used. The soft switching technology is complex in control and high in cost, so that the quasi-resonance technology is more attractive under medium frequency.
FIG. 2 shows a waveform diagram 200 of the quasi-resonant technique, G _ MPAnd driving voltage waveform for the grid end of the main switch tube. The controller enables the main switching tube to be at V by directly or indirectly detecting the voltage waveform of the switching nodeDSThe trough of the resonance voltage is opened, thereby reducing the switching loss of the main switching tube and making it possible to increase the frequency.
As the load is relieved, the efficiency is reduced if the converter still maintains a higher frequency. Therefore, many converters have both PWM (pulse width modulation) and PFM (pulse frequency modulation) modes. When the load is light, the frequency of the converter is reduced, namely, the switching loss is reduced, and the smoothness of an efficiency curve is ensured. However, in quasi-resonant applications, the frequency reduction cannot be achieved in an analog-linear fashion, and the main switching tube would be in turn at VDSThe first wave trough and the second wave trough of the waveform are opened. Therefore, the frequency variation of the converter is discrete. Reference numeral 301 in 300 of fig. 3 is an internal block diagram of a typical quasi-resonant controller. Comprising a feedback resistor R FB303. A trough detection unit circuit 304, a PFM unit circuit 305, a PWM comparator 306, a trough selection unit circuit 307, an RS flip-flop 308, and a drive unit circuit 309; the isolation feedback signal FB outputs an enabling signal EN through the working frequency of the PFM unit circuit regulation converter, and the enabling wave trough selection unit circuit selects the Nth wave troughConducting signal ON to the reset end of RS trigger, and turning ON the main switch tube M after amplified by the drive unit circuitP. The current of the exciting inductor LM begins to rise linearly, and the current detection resistor RSThe peak voltage reaches the value of the feedback signal FB, the PWM comparator outputs high level to reset the RS trigger, and the main switching tube M is closed through the driving unit circuitP。
Under a certain load, assume that the converter is at VDSThe Nth wave trough of the waveform is opened, and the input voltage has small disturbance +. DELTA.VINSince the voltage loop response lags behind the current loop, the excitation time of the transformer is first changed, reducing Δ TON. This condition will likely cause the converter to switch to the nth-1 valley on, thus abruptly changing the frequency by +. DELTA.f, causing the output voltage to drift high and the FB voltage to drop, which may revert back to the nth valley on after being maintained for several cycles. The waveforms shown in fig. 4 illustrate the main switching tube repeatedly switching between the second and third troughs. Such repeated switching results in a large output voltage ripple and abnormal noise in the switching frequency within the audio frequency range.
In order to solve the problem, most of the controllers on the market adopt a mode of locking the wave trough, namely, within a certain range of the FB voltage, the Nth wave trough is fixed to be switched on, and the wave trough is switched only when the FB jumps out of the set range. The chinese patent application publication "CN 108347173A" discloses another processing method, that is, detecting the operating frequency of the converter, converting the operating frequency into a voltage through integration, filtering, and the like, comparing the voltage with a reference voltage, and then determining whether to keep the current trough open or select the previous or next trough open. The control logic of the two modes is complex, and the circuit cost is high.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the above disadvantages in the prior art, and to provide a quasi-resonant control circuit, which prevents the switching-on wave trough from switching back and forth, avoids the increase of the output ripple of the converter, and is simple and practical.
In order to solve the technical problem, the technical scheme of the application is as follows:
a quasi-resonance control circuit comprises a feedback resistor RFBThe device comprises a wave trough detection unit circuit, a PFM unit circuit, a PWM comparator, a wave trough hysteresis unit circuit, an RS trigger and a driving unit circuit; the isolation feedback signal FB outputs an enabling signal EN through the working frequency of the PFM unit circuit regulation converter, an enabling wave trough hysteresis unit circuit selects a certain wave trough conducting signal to a position end of the RS trigger, and a main switching tube M is switched on after the signal is amplified by a driving unit circuitP(ii) a The method is characterized in that: setting a back difference time at the enable signal EN; the wave trough hysteresis unit circuit remembers that the Nth wave trough conducting signal is selected before; when the frequency is increased but the increment does not exceed the return difference time, the wave trough hysteresis unit circuit leads the enable signal EN by one return difference time, so that the wave trough hysteresis unit circuit selects the Nth wave trough conducting signal; when the frequency increment exceeds the return difference time, the wave trough hysteresis unit circuit selects the (N + 1) th wave trough conducting signal; when the frequency is reduced but the reduction amount does not exceed the return difference time, the wave trough hysteresis unit circuit delays the enable signal EN by one return difference time, so that the wave trough hysteresis unit circuit selects the Nth wave trough conducting signal; when the frequency reduction amount exceeds the return difference time, the wave trough hysteresis unit circuit selects the (N-1) th wave trough conducting signal.
The first embodiment of the valley hysteresis unit circuit includes a first D flip-flop, a first nand gate, a first and gate, a second D flip-flop, a first current source, a first switch, a second switch, a first capacitor, a first schmitt trigger, and a first inverter. The D input end of the first D trigger is connected with the output end of the first AND gate, the trigger end is connected with the output end of the first phase inverter, and the inverted output end
Figure GDA0002722112640000031
Is connected with one input end of the first NAND gate; a trough conducting signal is input to the input end of the first phase inverter; the other input end of the first NAND gate is connected with the Q output end of the second D trigger, and the output end of the first NAND gate is connected with one input end of the first AND gate; the other input end of the first AND gate inputs an enable signal EN, and the output end of the first AND gate is also connected with one end of a second AND gateAn input terminal; the other input end of the second AND gate inputs a trough conducting signal, and the output end of the second AND gate provides a setting signal of the RS trigger; the D input end of the second D trigger is connected with an internal power supply VCC, the trigger end is connected with an enable signal EN, the Q output end is also connected with the control end of the first switch, and the reverse phase output end
Figure GDA0002722112640000032
The reset end is connected with the output end of the first Schmitt trigger; one end of the first current source is connected with an internal power supply VCC, and the other end of the first current source is connected with one end of the first switch; the other end of the first switch is connected with the input end of the first Schmitt trigger, one end of the second switch and the upper polar plate of the first capacitor; the other end of the second switch is grounded with the lower polar plate of the first capacitor. The second D trigger, the first current source, the first switch, the second switch, the first capacitor and the first Schmitt trigger form a return difference time signal which is not influenced by the pulse width of the EN signal. The time signal determines whether to delay the return difference time based on the enable signal according to the timing relationship between the trough conducting signal and the actual enable signal.
The wave trough hysteresis unit circuit comprises a third D trigger, a second current source, a second Schmitt trigger, a second capacitor, a third switch, a fourth switch, a first delayer, a fourth D trigger, a second NAND gate, a third AND gate and a fourth AND gate; the D input end of the third D trigger inputs an enable signal EN, the trigger end is connected with the output end of the first delayer, and the output end Q is connected with one input end of the first NAND gate; the input end of the first delayer is connected with the output end of the second Schmitt trigger; the other input end of the second NAND gate is connected with the Q output end of the fourth D trigger, and the output end of the second NAND gate is connected with one input end of the third AND gate; the other input end of the third AND gate inputs an enable signal EN, and the output end of the third AND gate is connected with one input end of the fourth AND gate; the other input end of the fourth AND gate inputs a trough conducting signal, and the output end of the fourth AND gate provides a setting signal of the RS trigger; the D input end of the fourth D trigger is connected with an internal power supply VCC, the trigger end is connected with an enable signal EN, and the Q output end is also connected with the control of a third switchEnd-making, reverse output end
Figure GDA0002722112640000041
The reset end is connected with the output end of the second Schmitt trigger; one end of the second current source is connected with the internal power supply, and the other end of the second current source is connected with one end of the third switch; the other end of the third switch is connected with the input end of the first Schmitt trigger, one end of the fourth switch and an upper polar plate of the second capacitor; the other end of the fourth switch and the lower pole plate of the second capacitor are grounded. The connection and function of the valley hysteresis unit circuit are similar to those of the first embodiment, except that the third D flip-flop is triggered by a return difference time signal delayed by a period of time. Whether the back-off time is delayed based on the EN signal is determined by the timing relationship between the back-off time signal itself and the EN signal.
The detailed working principle of the present invention will be described in conjunction with specific embodiments in specific embodiments, which are not described herein, and the beneficial effects of the present invention are as follows:
1. simply setting a return difference time at an enabling signal to realize a wave trough hysteresis function;
2. based on the wave trough hysteresis function, the problem of wave trough repeated switching can not occur when the converter system is disturbed, and the stability of the system is facilitated.
Drawings
Fig. 1 is a functional block diagram of a typical flyback converter circuit;
FIG. 2 is a waveform of a key node of a quasi-resonance technique;
FIG. 3 is a functional block diagram of an exemplary quasi-resonant controller;
FIG. 4 is a key signal waveform of a typical quasi-resonant controller;
FIG. 5 is a functional block diagram of a quasi-resonant controller of the present invention;
FIG. 6 is a schematic diagram of a valley hysteresis cell circuit according to a first embodiment of the present invention;
FIG. 7 is a schematic diagram of a valley hysteresis cell circuit according to a second embodiment of the present invention;
FIG. 8 shows waveforms of key signals according to an embodiment of the present invention.
Detailed Description
Fig. 5 is a block diagram of a circuit for a quasi-resonant controller according to the present invention. The trough hysteresis unit circuit 507 is configured to determine to provide an actual enable signal according to a timing relationship between an enable signal EN output by the PFM unit circuit in the previous stage and a trough conduction signal ON, and select which trough conduction signal ON triggers the set end of the RS flip-flop.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following describes the valley hysteresis unit circuit of the present invention in detail with reference to fig. 6 to 8. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example one
FIG. 6 illustrates one embodiment of a valley hysteresis cell circuit. Including D flip-flop 601, nand gate 602, and gates 603 and 604, D flip-flop 605, current source 606, switch 607, switch 608, capacitor 609, schmitt trigger 610, and inverter 611. The D input end of the D trigger 601 is connected with the output end of the AND gate 603, the trigger end is connected with the output end of the phase inverter 611, and the inverted output end
Figure GDA0002722112640000051
An input terminal of the nand gate 602; the input end of the inverter 611 inputs a valley conduction signal ON; the Q output end of the D flip-flop 605 outputs the return difference time signal EN _ HY to the other input end of the nand gate 602, and the output end of the nand gate 602 is connected to one input end of the and gate 603; 603, the other input end inputs the enable signal EN output by the PFM unit circuit, and the output end outputs the Actual enable signal EN _ Actual to one input end of the and gate 604; the other input end of the and gate 604 inputs a trough conducting signal ON, and the output end outputs a set signal of the RS flip-flop 508 in the controller; the D input terminal of the D flip-flop 605 is connected to the internal power VCC, the trigger terminal inputs the enable signal EN, the Q output terminal is further connected to the control terminal of the switch 607,
Figure GDA0002722112640000052
the output end is connected with the control end of the switch 608; one end of the switch 607 is connected to the current source 606, and the other end is connected to the switchOne end of 608, an input end of schmitt trigger 610 and an upper plate of capacitor 609; the lower plate of the capacitor 609 and the other end of the switch 608 are simultaneously grounded; the output of the schmitt trigger 610 is connected to the reset terminal of the D-flip-flop 605.
As can be seen from fig. 4, the enable signal EN is characterized by being active high, the rising edge is determined by the PFM unit circuit, and the falling edge is determined by the valley conducting signal ON. The D flip-flop 605 is triggered by the rising edge of the enable signal EN, the Q output terminal becomes high level, the switch 607 is closed, the capacitor 609 is charged by the current source 606, when the voltage of the upper plate of the 609 exceeds the flip-flop threshold of the schmitt trigger 610, the schmitt trigger 610 outputs low level to reset the D flip-flop 605, and the Q output terminal of the D flip-flop 605 becomes low level, that is, the return difference time signal EN _ HY is not affected by the pulse width of the enable signal EN. If the rising edge of the valley conducting signal ON is in the low level region of the Actual enable signal EN _ Actual signal, the inverted output terminal of the D flip-flop 601 outputs a high level, the nand gate 602 outputs a signal inverted from the return time signal EN _ HY, and the enable signal EN passes through the and gate 603 and then outputs the Actual enable signal EN _ Actual signal, thereby forming a locked loop. If the enable signal ON in this region is to trigger the main switch tube to be turned ON, it must transition to the high level region of the Actual enable signal EN _ Actual. If the rising edge of the valley conduction signal ON is in the high level region of the Actual enable signal EN _ Actual signal, the inverting output terminal of the D flip-flop 601 outputs a low level, and the nand gate 602 outputs a high level. At this time, if the Actual enable signal EN _ Actual signal is identical to the enable signal EN, the valley ON signal ON in this region must transition to the low level region of the enable signal EN in order to stop triggering the main switch to turn ON. Therefore, a time return difference is formed, the return difference is the pulse width of the EN _ HY, and sudden change of a trough conduction signal can be avoided, namely the N trough triggers the conduction of the main switching tube to suddenly change to the N +1 th or the N-1 th trough triggers the conduction of the main switching tube.
Example two
FIG. 7 shows another embodiment of a valley hysteresis cell circuit. Including D flip-flop 701, nand gate 702, and gates 703 and 704, D flip-flop 705, current source 706, switch 707, switch 708, capacitor 709, schmitt trigger 710, and delay 711. The connection relationship between these components is substantially the same as that of the first embodiment, except that the input terminal of the added delay 711 is connected to the output terminal of the schmitt trigger 710, the D input terminal of the D flip-flop 701 is connected to the EN enable signal, and the Q output terminal of the D flip-flop 701 is connected to one input terminal of the nand gate 702. The delay 711 outputs a delay signal of the back difference time signal EN _ HY determined by a loop delay composed of the D flip-flop 705, the switch 707, the switch 708, the current source 706, the capacitor 709, and the schmitt trigger 710, and the width of the delay signal is similar to the pulse width of the back difference time signal EN _ HY. Generally, the delay signal is in a high level region of an enable signal EN, that is, the ON time of a conduction signal of a wave trough triggering the main switch tube to be turned ON is after the delay signal. At this time, the Q output of the D flip-flop 701 outputs a high level to one input of the nand gate 702. The nand gate 702 outputs a signal having an inverted phase with the return time signal EN _ HY to one input terminal of the and gate 703. The and gate 703 outputs the Actual enable signal EN _ Actual delayed by the pulse width of the return difference time signal EN _ HY compared to the enable signal EN. Thus, the valley conduction signal ON in the low level region of the enable signal EN must transition to the high level region of the Actual enable signal EN _ Actual in order to trigger the main switch to turn ON in the sub-cycle. If the main switch is to be stopped triggering, the valley conducting signal ON in the high level region of the Actual enable signal EN _ Actual will lead the delay signal, the enable signal EN will be at a low level at the rising edge of the delay signal, and the Q output end of the D flip-flop 701 will output a low level, so that the nand gate 709 will output a high level. At this time, the Actual enable signal EN _ Actual signal coincides with the enable signal EN. Therefore, the valley conduction signal ON in the high level region of the Actual enable signal EN _ Actual must transition to the low level region of the enable signal EN to stop triggering the main switch to turn ON.
To more intuitively illustrate the operation of the circuit of the present invention, the key waveforms of FIG. 8 are illustrated. In the first period, the main switch tube is switched on at the third trough, in the second period, the region shown as the part I in the figure is still determined by the enable signal EN, the second trough should be switched on, but the Actual enable signal EN _ Actual still selects the third trough to be switched on due to the increase of the return difference time; until the third period, in the area indicated by the second time, the second trough conducting signal ON is transited to the high level area of the Actual enabling signal EN _ Actual, and the second trough is selected to be switched ON; the fourth period shows that the second trough conducting signal ON is in a region where the return difference time signal EN _ HY is high level, but the second trough is still kept ON, as shown in the region indicated by the third step; until the fourth period, which is shown as the area indicated by the fourth value, the second valley conduction signal ON transits to the low level area of the enable signal EN, the third valley is selected to be turned ON.
The embodiments of the present invention are not limited thereto, and other embodiments of the present invention can be made based on the above-mentioned matters, according to the common technical knowledge and the conventional means in the field without departing from the basic inventive concept of the present invention; therefore, it is intended that the present invention cover the modifications, substitutions and alternatives of the present invention as described above.

Claims (3)

1. A quasi-resonance control circuit comprises a feedback resistor RFBThe device comprises a wave trough detection unit circuit, a PFM unit circuit, a PWM comparator, a wave trough hysteresis unit circuit, an RS trigger and a driving unit circuit; the isolation feedback signal FB outputs an enabling signal EN through the working frequency of the PFM unit circuit regulation converter, an enabling wave trough hysteresis unit circuit selects a certain wave trough conducting signal to a position end of the RS trigger, and a main switching tube M is switched on after the signal is amplified by a driving unit circuitP(ii) a The method is characterized in that: setting a back difference time at the enable signal EN; the wave trough hysteresis unit circuit remembers that the Nth wave trough conducting signal is selected before; when the frequency is increased but the increment does not exceed the return difference time, the wave trough hysteresis unit circuit leads the enable signal EN by one return difference time, so that the wave trough hysteresis unit circuit selects the Nth wave trough conducting signal; when the frequency increment exceeds the return difference time, the wave trough hysteresis unit circuit selects the (N + 1) th wave trough conducting signal; when the frequency is reduced but the reduction amount does not exceed the backstepping time, the wave trough hysteresis unit circuit delays the enable signal EN by one backstepping time to enable the enable signal EN to be delayed by one backstepping timeThe wave trough hysteresis unit circuit selects the Nth wave trough conducting signal; when the frequency reduction amount exceeds the return difference time, the wave trough hysteresis unit circuit selects the (N-1) th wave trough conducting signal.
2. The quasi-resonant control circuit of claim 1, wherein: the wave trough hysteresis unit circuit comprises a first D trigger, a first NAND gate, a first AND gate, a second D trigger, a first current source, a first switch, a second switch, a first capacitor, a first Schmitt trigger and a first phase inverter; the D input end of the first D trigger is connected with the output end of the first AND gate, the trigger end is connected with the output end of the first phase inverter, and the inverted output end
Figure FDA0002306074410000011
Is connected with one input end of the first NAND gate; a trough conducting signal is input to the input end of the first phase inverter; the other input end of the first NAND gate is connected with the Q output end of the second D trigger, and the output end of the first NAND gate is connected with one input end of the first AND gate; the other input end of the first AND gate inputs an enable signal EN, and the output end of the first AND gate is also connected with one input end of the second AND gate; the other input end of the second AND gate inputs a trough conducting signal, and the output end of the second AND gate provides a setting signal of the RS trigger; the D input end of the second D trigger is connected with an internal power supply VCC, the trigger end inputs an enable signal EN, the Q output end is also connected with the control end of the first switch, and the reverse phase output end
Figure FDA0002306074410000012
The reset end is connected with the output end of the first Schmitt trigger; one end of the first current source is connected with an internal power supply VCC, and the other end of the first current source is connected with one end of the first switch; the other end of the first switch is connected with the input end of the first Schmitt trigger, one end of the second switch and the upper polar plate of the first capacitor; the other end of the second switch is grounded with the lower polar plate of the first capacitor.
3. Quasi-resonant control according to claim 1A circuit, characterized by: the wave trough hysteresis unit circuit comprises a third D trigger, a second current source, a second Schmitt trigger, a second capacitor, a third switch, a fourth switch, a first delayer, a fourth D trigger, a second NAND gate, a third AND gate and a fourth AND gate; the D input end of the third D trigger inputs an enable signal EN signal, the trigger end is connected with the output end of the first delayer, and the output end Q is connected with one input end of the first NAND gate; the input end of the first delayer is connected with the output end of the second Schmitt trigger; the other input end of the second NAND gate is connected with the Q output end of the fourth D trigger, and the output end of the second NAND gate is connected with one input end of the third AND gate; the other input end of the third AND gate inputs an enable signal EN, and the output end of the third AND gate is connected with one input end of the fourth AND gate; the other input end of the fourth AND gate inputs a trough conducting signal, and the output end of the fourth AND gate provides a setting signal of the RS trigger; the D input end of the fourth D trigger is connected with an internal power supply VCC, the trigger end is connected with an enable signal EN, the Q output end is also connected with the control end of the third switch, and the reverse output end
Figure FDA0002306074410000021
The reset end is connected with the output end of the second Schmitt trigger; one end of the second current source is connected with the internal power supply, and the other end of the second current source is connected with one end of the third switch; the other end of the third switch is connected with the input end of the first Schmitt trigger, one end of the fourth switch and an upper polar plate of the second capacitor; the other end of the fourth switch and the lower pole plate of the second capacitor are grounded.
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