CN111041482A - 一种用于半导体封装模具内腔的复合涂层及其制备方法 - Google Patents
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Abstract
本发明涉及的用于半导体封装模具内腔的复合涂层，包括直接与模具内腔表面结合的过渡层、以及部分嵌入在过渡层的功能层，过渡层为Cu晶枝层，功能层为DLC/SiC层，Cu晶枝层能够提供高比表面积，提高DLC/SiC涂层与内腔基底的结合力，有效防止在封装作业过程中复合涂层的剥落；由于DLC/SiC涂层具有耐侵蚀性和低黏附性，可以使半导体封装模具内腔表面避免污染物的残留破坏产品以及对于模具内腔的侵蚀，提高半导体封装模具的使用寿命。
Description
技术领域
本发明涉及一种用于半导体封装模具内腔的复合涂层及其制备方法。
背景技术
随着工业的发展，利用半导体模具封装成型方法对各种半导体产品的封装外壳进行塑性成型生产已十分广泛。在不断重复的成型生产操作过程中，外壳原料在成型过程中容易受摩擦升温而热解渗出，从而产生热解残留物附着于封装模具的内腔表面。随着附着物的不断堆积，会对模具内腔表面形态产生显著影响。这些污染物不仅会影响后续产品的外观及质量，且对模具自身产生一定的侵蚀作用，导致模具使用寿命降低，影响封装成型过程的生产效率。为了解决这一问题，可以在半导体封装模具内腔表面制备一种有效的复合涂层来解决污染物的附着及表面侵蚀问题。通过磁控溅射技术在基底表面制备具有特定功能的涂层能够有效的增强模具耐侵蚀性，并降低污染物的附着，从而提高模具使用寿命并显著提升生产效率。在现有的技术中，磁控溅射的功能性涂层与基底材料间的结合力不足，导致涂层易于在生产过程中发生剥落，进而增加模具内腔的损坏几率。
发明内容
本发明的目的在于提供一种用于半导体封装模具内腔且不易剥落、高耐侵蚀性以及低黏附性的复合涂层。
为达到上述目的，本发明提供如下技术方案：一种用于半导体封装模具内腔的复合涂层，包括直接与模具内腔表面结合的过渡层、以及部分嵌入在所述过渡层的功能层，所述过渡层为Cu晶枝层，所述功能层为DLC/SiC层。
进一步地，所述Cu晶枝层的厚度为1um-2um。
进一步地，所述DLC/SiC层的厚度为3um-5um。
进一步地，所述DLC/SiC层包括DLC层以及分布在DLC层中的SiC颗粒。
进一步地，所述用于半导体封装模具内腔的复合涂层的厚度为4um-7um。
本发明还提供了一种用以制备所述用于半导体封装模具内腔的复合涂层的制备方法，所述制备方法如下：
S1、提供半导体封装模具，将所述半导体封装模具内腔表面镀覆Cu晶枝层，所述Cu晶枝层的厚度为1um-2um；
S2、在所述Cu晶枝层表面沉积DLC/SiC层，所述DLC/SiC层的厚度为3um-5um。
进一步地，所述Cu晶枝层由电沉积方法制备得到。
进一步地，所述DLC/SiC层由磁控溅射技术沉积制备得到。
本发明的有益效果在于：本发明所提供的用于半导体封装模具内腔的复合涂层包括与内腔表面紧密结合的Cu晶枝层和DLC/SiC涂层，Cu晶枝层能够提供高比表面积，提高DLC/SiC涂层与内腔基底的结合力，有效防止在封装作业过程中复合涂层的剥落；由于DLC/SiC涂层具有耐侵蚀性和低黏附性，可以使半导体封装模具内腔表面避免污染物的残留破坏产品质量以及对于模具内腔的侵蚀，提高半导体封装模具的使用寿命。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下以本发明的较佳实施例并配合附图详细说明如后。
附图说明
图1为本发明一实施例的半导体封装模具内腔及复合涂层的结构示意图。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的机构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
此外，下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
请参见图1，本发明一实施例所示的用于半导体封装模具1内腔的复合涂层2，包括直接与模具1内腔表面结合的过渡层21、以及部分嵌入在过渡层21的功能层22，过渡层21为Cu晶枝层21，功能层22为DLC/SiC层22。DLC/SiC层22包括DLC层221以及分布在DLC层221中的SiC颗粒222，DLC层为具有高硬度和高弹性模量，以及耐磨损且很适合于作为耐磨涂层的类金刚石层。其中，Cu晶枝层21的厚度为1um-2um，DLC/SiC层22的厚度为3um-5um，复合涂层2的厚度为4um-7um。
Cu晶枝层21具有多孔晶枝结构，该结构促使Cu晶枝层21与模具1内腔表面之间可产生较强的结合力，同时多孔晶枝结构自身具有较大的比表面积，Cu晶枝层21设置在在DLC/SiC层22与模具1内腔表面之间，可促使DLC/SiC层22与模具1内腔表面之间产生更强的结合力，从而有效防止在封装作业过程中复合涂层2的剥落，延长复合涂层2的使用寿命。
通过制备多孔晶枝结构的Cu晶枝层21和具有高耐侵蚀性及低黏附性的DLC/SiC层22形成的复合涂层2，使其与模具1内腔表面具有高结合力并且使模具1内腔表面拥有较高耐侵蚀性，并有效减小污染物的粘附。
本发明还提供了一种用以制备上述用于半导体封装模具1内腔的复合涂层2的制备方法，制备方法如下：
S1、提供半导体封装模具，将半导体封装模具1内腔表面镀覆Cu晶枝层21，具体的，Cu晶枝层21由电沉积方法制备，使用去离子水配制Cu镀液，镀液组成为：二氯化铜10g/L-40g/L，混合络合剂20g/L-60g/L，氢氧化钠0.2g/L-2g/L，稳定剂1mg/L-100mg/L。调节镀液pH值为11，电沉积温度为60℃，阴极电流密度20mA·cm-2-60mA·cm-2，电沉积时间为2min。制备得到的Cu晶枝层21的厚度为1um-2um。
S2、在Cu晶枝层21表面沉积DLC/SiC层22，具体的，利用磁控溅射技术沉积制备DLC/SiC涂层22：抽真空到1.0x10-3Pa以上，通入纯度为99.999％的氩气(Ar)，将Si靶和C靶安装于真空室内的磁控溅射源上，进行双靶共溅射操作。对Si靶开启射频电源，10W/cm2-20W/cm2，溅射时长为30min；同时对C靶开启直流电源，0.5kW/cm2-1kW/cm2，溅射时长为30min，制备得到DLC层221以及分布在DLC层221中的SiC颗粒222形成的DLC/SiC层22的厚度为3um-5um。DLC/SiC层22部分嵌入Cu晶枝层21的多孔晶枝结构内，Cu晶枝层21和DLC/SiC层22形成镀覆在半导体封装模具1内腔表面的复合涂层2。
综上，本发明所提供的用于半导体封装模具内腔的复合涂层包括与内腔表面紧密结合的Cu晶枝层和DLC/SiC涂层，Cu晶枝层能够提供高比表面积，提高DLC/SiC涂层与内腔基底的结合力，有效防止在封装作业过程中复合涂层的剥落；由于DLC/SiC涂层具有耐侵蚀性和低黏附性，可以使半导体封装模具内腔表面避免污染物的残留破坏产品质量以及对于模具内腔的侵蚀，提高半导体封装模具的使用寿命。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。
Claims (8)
1.一种用于半导体封装模具内腔的复合涂层，其特征在于，所述用于半导体封装模具内腔的复合涂层包括直接与模具内腔表面结合的过渡层、以及部分嵌入在所述过渡层的功能层，所述过渡层为Cu晶枝层，所述功能层为DLC/SiC层。
2.如权利要求1所述的用于半导体封装模具内腔的复合涂层，其特征在于，所述Cu晶枝层的厚度为1um-2um。
3.如权利要求1所述的用于半导体封装模具内腔的复合涂层，其特征在于，所述DLC/SiC层的厚度为3um-5um。
4.如权利要求3所述的用于半导体封装模具内腔的复合涂层，其特征在于，所述DLC/SiC层包括DLC层以及分布在DLC层中的SiC颗粒。
5.如权利要求1所述的用于半导体封装模具内腔的复合涂层，其特征在于，所述用于半导体封装模具内腔的复合涂层的厚度为4um-7um。
6.一种用以制备权利要求1至5项中任一项所述的用于半导体封装模具内腔的复合涂层的制备方法，其特征在于，所述制备方法如下：
S1、提供半导体封装模具，将所述半导体封装模具内腔表面镀覆Cu晶枝层，所述Cu晶枝层的厚度为1um-2um；
S2、在所述Cu晶枝层表面沉积DLC/SiC层，所述DLC/SiC层的厚度为3um-5um。
7.如权利要求6所述的用于半导体封装模具内腔的复合涂层的制备方法，其特征在于，所述Cu晶枝层由电沉积方法制备得到。
8.如权利要求6所述的用于半导体封装模具内腔的复合涂层的制备方法，其特征在于，所述DLC/SiC层由磁控溅射技术沉积制备得到。
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