CN111029354B - Three-dimensional integrated circuit structure of large-area-array high-frame-frequency high-reliability miniaturized image sensor - Google Patents

Three-dimensional integrated circuit structure of large-area-array high-frame-frequency high-reliability miniaturized image sensor Download PDF

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CN111029354B
CN111029354B CN201911217001.0A CN201911217001A CN111029354B CN 111029354 B CN111029354 B CN 111029354B CN 201911217001 A CN201911217001 A CN 201911217001A CN 111029354 B CN111029354 B CN 111029354B
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pixel
substrate
improved
chip
image sensor
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CN111029354A (en
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杨力宏
单光宝
朱樟明
卢启军
杨银堂
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Xidian University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14632Wafer-level processed structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14634Assemblies, i.e. Hybrid structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14636Interconnect structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687Wafer level processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469Assemblies, i.e. hybrid integration

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention relates to a three-dimensional integrated circuit structure of a large-area array high-frame-frequency high-reliability miniaturized image sensor, which comprises a substrate, wherein a cavity is arranged on the upper surface of the substrate, and a pixel chip is arranged in the cavity; by leading out the pixels in the pixel chip longitudinally, the area consumed by wiring of the pixel chip is saved, the weak light or low light imaging capability can be improved by increasing the pixel size, and the sensitivity of the chip is improved; the higher resolution can be obtained by increasing the number of pixels, so that the system integration level is improved; the number of channels is increased through the lateral extraction of the added pixels, so that the complexity of clock arrangement can be effectively reduced, the system integration level is improved, and the reliability of signal transmission is improved; the pixel chip is arranged in the substrate with the cavity and is provided with the filler, so that the data transmission speed is improved, and the system frame frequency is improved; and the coupling between channels is reduced, and the signal-to-noise ratio is improved.

Description

Three-dimensional integrated circuit structure of large-area-array high-frame-frequency high-reliability miniaturized image sensor
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a three-dimensional integrated circuit structure of a large-area-array high-frame-frequency high-reliability miniaturized image sensor.
Background
In the prior art, the pixel units and the readout circuits of the image sensor chip are manufactured on the same substrate, so that not only is the filling rate of the pixel units reduced, but also the complexity of time sequence design and clock arrangement is increased due to uneven delay of signal lines, the frame rate is low, and the output dynamic range is not high; in order to save the chip area, the wiring channel area is compressed, so that the mutual crosstalk of signal lines is increased, and the signal-to-noise ratio is reduced; meanwhile, as the area array units and the wiring channels occupy a large amount of area of the whole chip, more processing circuits cannot be integrated, the functions of the reading circuit are limited, and the system is required to adopt a two-dimensional integration mode, so that the performance of the system is improved. The whole system volume is increased, the parasitic effect influence is increased, the system complexity is improved, the miniaturization integration is not facilitated, and the use of low noise and high frame rate is not facilitated; in order to improve the system performance, better process technology is required, and the cost is increased.
In addition, although the system performance can be improved by three-dimensional integration in the prior art, the problems of dark current, crosstalk, warpage and the like are not ignored. In order to reduce dark current, the pixel chip needs to adopt a larger pixel size, and the working speed is lower, so that the resolution of the system is low, the definition is poor, the volume is large, and the application of the large-area array pixel chip is limited; to reduce crosstalk, methods of extending the lifetime of carriers of silicon and improving the silicon processing process are often employed. Extending the lifetime of the carriers naturally increases quantum efficiency, but increases crosstalk due to charge diffusion; methods of improving the silicon processing process increase the cost of manufacturing the system. Because the thermal expansion coefficients of the materials in the three-dimensional integration are not matched, the stacking quantity of chips is limited, the performance of the system is reduced, and the reliability of the system is deteriorated.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a three-dimensional integrated circuit structure of a large-area-array high-frame-rate high-reliability miniaturized image sensor, which comprises a substrate, wherein a cavity is arranged on the upper surface of the substrate, and a pixel chip is arranged in the cavity.
The pixel chip comprises pixels, longitudinal pixel extraction and transverse pixel extraction, wherein the pixels are longitudinally extracted through the pixels; the pixel is transversely led out and electrically connected with an RDL layer arranged above the substrate.
The micro-bump is arranged in the cavity, a first through hole is further formed in the substrate, and the micro-bump is arranged between the pixel chips of the first through hole.
The second RDL layer is arranged below the substrate, the welding ball is arranged below the second RDL layer, and the reading circuit chip is arranged below the welding ball.
The first via includes a normal via or a TSV via.
The substrate is also provided with a second through hole, a bump is arranged below the substrate, and the bump corresponds to the second through hole.
The second via includes a normal via or TSV via.
The substrate is made of one or more of silicon, germanium, silicon germanium alloy, silicon carbon alloy, silicon germanium carbon alloy, gallium arsenide, indium phosphide, III-V semiconductor material, II-IV semiconductor material and organic semiconductor material.
The cavity and the pixel chip are also filled with filler.
The invention has the beneficial effects that: the three-dimensional integrated structure of the large-area-array high-frame-frequency high-reliability miniaturized image sensor provided by the invention has the following advantages: firstly, in order to reduce the pixel structure and enlarge the area array size, the pixel structure of the existing image sensor can only adopt a better process technology, but the invention saves the area consumed by wiring of the pixel chip by leading out the pixels in the pixel chip longitudinally, and can improve the weak light or low light imaging capability and the sensitivity of the chip by increasing the pixel size; the higher resolution can be obtained by increasing the number of pixels, so that the system integration level is improved; secondly, the added pixels are led out transversely, the number of channels is increased, the complexity of clock arrangement can be effectively reduced, the system integration level is further improved, and the reliability of signal transmission is improved; thirdly, the pixel chip is arranged in the substrate with the cavity, the cavity is filled with the filler with high isolation, easy heat conduction and mutually matched thermal expansion coefficients, and the through hole or the TSV adopts a high isolation structure, so that the longitudinal distance between the pixel in the pixel chip and the corresponding signal processing unit in the reading circuit chip is reduced, the data transmission speed is improved, and the system frame frequency is improved; the coupling between channels is reduced, and the signal to noise ratio is improved; meanwhile, as the pixel chip and the readout circuit are longitudinally interconnected, logic circuits such as row and column decoding and the storage units of the readout circuit can be removed, the readout efficiency is improved, the uniformity of pixel reaction is improved, the pixels can be sampled at the same time, and an image without distortion is generated; the problem of mismatch of thermal expansion coefficients caused by integration of various materials is solved, and the reliability of the system is improved. Fourthly, the read-out circuit chip is separated from the pixel chip, and the read-out circuit chip and the pixel chip can adopt respective optimal processes, so that the two types of circuits can obtain optimal performance; meanwhile, more functional modules can be integrated in the read-out circuit chip, the system can obtain images with higher dynamic range, and the system performance is improved. The manufacturing process of each chip and the whole system is compatible with the prior process technology, a new process technology is not required to be developed, and the cost is low. Therefore, the large-area-array high-frame-frequency high-reliability miniaturized image sensor structure fully plays the advantages of three-dimensional integrated interconnection, and realizes the high-density, high-performance and high-reliability image sensing integrated system.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of a three-dimensional integrated circuit structure of a large-area-array high-frame-rate high-reliability miniaturized image sensor.
In the figure: 1. a substrate; 2. a cavity; 3. a through hole; 3-1, a second through hole; 4. a bump; 5. a micro bump; 6. welding balls; 7. an RDL layer; 7-1, a second RDL layer; 8. a pixel chip; 9. a pixel; 10. the pixels are longitudinally led out; 11. the pixels are led out transversely; 12. and reading out the circuit chip.
Detailed Description
The following detailed description, structural features and functions of the present invention are provided with reference to the accompanying drawings and examples in order to further illustrate the technical means and effects of the present invention to achieve the predetermined objects.
Example 1
In order to improve the integration density of the image sensor, higher resolution is obtained, and meanwhile, high reliability, higher frame frequency and higher uniformity of pixel reaction are realized; the embodiment provides a three-dimensional integrated circuit structure of a large-area-array high-frame-frequency high-reliability miniaturized image sensor shown in fig. 1, which comprises a substrate 1, wherein a cavity 2 is arranged on the upper surface of the substrate 1, and a pixel chip 8 is arranged in the cavity 2. The substrate 1 is made of one or more of silicon, germanium, silicon germanium alloy, silicon carbon alloy, silicon germanium carbon alloy, gallium arsenide, indium phosphide, III-V semiconductor material, II-IV semiconductor material and organic semiconductor material. The substrate 1 supports the overall structure and the integrated system.
The pixel chip 8 comprises a pixel 9, a pixel longitudinal extraction 10 and a pixel transverse extraction 11, wherein the pixel 9 is extracted through the pixel longitudinal extraction 10; the pixel transverse leading-out 11 is electrically connected with the RDL layer 7 arranged above the substrate 1; thus, the area consumed by wiring of the pixel chip 8 can be saved, the space between the pixels 9 is reduced, the weak light or low light imaging capability can be improved by increasing the size of the pixels 9, and the sensitivity of the pixel chip 8 is improved; the number of pixels 9 can be increased, the number of channels can be increased, higher resolution can be obtained, and the system integration level can be improved. The pixel transverse leading-out 11 is electrically interconnected with the RDL layer 7 on the cavity, so that the number of channels is increased, the clock arrangement complexity can be effectively reduced, the system integration level is further improved, and the reliability of signal transmission is improved; and the pixel transverse leading-out 11 can be utilized to be connected with power ground, so that good ESD protection is formed for the pixel chip 8, and the reliability of the pixel chip 8 is improved. By reducing the thickness of the pixel chip 8, the data transmission speed is improved, and the system frame frequency is improved; and the warping of the chip is reduced, and the reliability of the system is improved.
A second RDL layer 7-1 is arranged below the substrate 1, a welding ball 6 is arranged below the second RDL layer 7-1, a reading circuit chip 12 is arranged below the welding ball 6, and the reading circuit chip 12 is connected with the second RDL layer 7-1 through the welding ball 6; the signal processing units in the read-out circuit chip 12 form a longitudinal interconnection with the corresponding picture elements 9 in the picture element chip 8, respectively. Because of this connection, the logic circuits and memory cells such as row and column decoding adopted by the read-out circuit chip 12 in the prior art are not required, so that not only is the read-out efficiency improved, but also the uniformity of pixel reaction is improved, and the pixels 9 can be sampled at the same time to generate an image without distortion. Because the read-out circuit chip 12 is separated from the pixel chip 8, the read-out circuit chip and the pixel chip can adopt respective optimal processes, so that the two circuits can obtain optimal performance; meanwhile, more functional modules can be integrated in the read-out circuit chip 12, the system can obtain images with higher dynamic range, and the system performance is improved.
The cavity 2 is internally provided with a micro-bump 5, the substrate 1 is also provided with a first through hole 3, the micro-bump 5 is arranged between the first through hole 3 and the pixel chip 8, the first through hole 3 is arranged between the micro-bump 5 and the second RDL layer 7-1, and the micro-bump 5, the first through hole 3 and the second RDL layer 7-1 have the function of connecting the pixel chip 8 and the read-out circuit chip 12 and support the pixel chip 8; the pixel chip 8 is placed in the cavity 2 and forms interconnection with the first through hole 3 in the substrate 1 through the micro-bump 5; the pixel chip 8 is arranged in the substrate 1 with the cavity 2, so that the longitudinal distance between the pixel 9 in the pixel chip 8 and a corresponding signal processing unit in the read-out circuit chip 12 is reduced, the data transmission speed is improved, and the system frame frequency is improved; the filling agent with high isolation, easy heat conduction and mutually matched thermal expansion coefficients is filled in the cavity 2, so that the problems of dark current increase and noise occurrence caused by overheating due to too frequent current transformation when the fast-changing image is processed can be solved; the problem of mismatch of thermal expansion coefficients caused by integration of various materials is solved, and the reliability of the system is improved. The cavity 2 is electrically interconnected with the pixel transversely led out 11 through the RDL layer 7, so that the number of channels is increased, the clock arrangement complexity can be effectively reduced, the system integration level is further improved, and the reliability of signal transmission is improved.
The first via 3 includes a general via or TSV via.
The substrate 1 is also provided with a second through hole 3-1, a bump 4 is arranged below the substrate 1, and the bump 4 corresponds to the second through hole 3-1; in this way, the bump 4 is connected to the second through hole 3-1, and not only functions as an overall system electrical connection, but also functions as a support for each module on the substrate 1.
The second via 3-1 includes a general via or TSV via.
Further, the first through hole 3 and the second through hole 3-1 are used as channels of corresponding signal wires and power wires; the through holes or TSVs 3 adopt a high-isolation structure, so that crosstalk between signals is reduced, and the signal-to-noise ratio is improved.
In summary, the three-dimensional integrated structure of the large-area array high-frame-frequency high-reliability miniaturized image sensor has the following advantages: firstly, in order to reduce the pixel structure and enlarge the area array size, the pixel structure of the existing image sensor can only adopt a better process technology, but the invention saves the area consumed by wiring of the pixel chip by leading out the pixels in the pixel chip longitudinally, and can improve the weak light or low light imaging capability and the sensitivity of the chip by increasing the pixel size; the higher resolution can be obtained by increasing the number of pixels, so that the system integration level is improved; secondly, the added pixels are transversely led out 11, so that the number of channels is increased, the complexity of clock arrangement can be effectively reduced, the system integration level is further improved, and the reliability of signal transmission is improved; thirdly, the pixel chip 8 is arranged in the substrate 1 with the cavity 2, the cavity 2 is filled with a filler with high isolation, easy heat conduction and mutually matched thermal expansion coefficients, and the through hole or TSV adopts a high isolation structure, so that the longitudinal distance between the pixel 9 in the pixel chip 8 and a corresponding signal processing unit in the read-out circuit chip 12 is reduced, the data transmission speed is improved, and the system frame frequency is improved; the coupling between channels is reduced, and the signal to noise ratio is improved; meanwhile, as the pixel chip 8 and the readout circuit are longitudinally interconnected, logic circuits such as row and column decoding and the storage units of the readout circuit can be removed, the readout efficiency is improved, the uniformity of pixel reaction is improved, pixels can be sampled at the same time, and an image without distortion is generated; the problem of mismatch of thermal expansion coefficients caused by integration of various materials is solved, and the reliability of the system is improved. Fourthly, the read-out circuit chip 12 is separated from the pixel chip 8, and the read-out circuit chip and the pixel chip can adopt respective optimal processes, so that the two types of circuits can obtain optimal performance; meanwhile, more functional modules can be integrated in the read-out circuit chip 12, the system can obtain images with higher dynamic range, and the system performance is improved. The manufacturing process of each chip and the whole system is compatible with the prior process technology, a new process technology is not required to be developed, and the cost is low. Therefore, the large-area-array high-frame-frequency high-reliability miniaturized image sensor structure can fully exert the advantages of three-dimensional integrated interconnection, and realize a high-density, high-performance and high-reliability image sensing integrated system.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (6)

1. The three-dimensional integrated circuit structure of the high-frame-rate high-reliability miniaturized image sensor of a large area array comprises a substrate (1), and is characterized in that: the upper surface of the substrate (1) is provided with a cavity (2), and a pixel chip (8) is arranged in the cavity (2); the pixel chip (8) comprises a pixel (9), a pixel longitudinal extraction (10) and a pixel transverse extraction (11), wherein the pixel (9) is extracted through the pixel longitudinal extraction (10); the pixel transverse leading-out (11) is electrically connected with the RDL layer (7) arranged above the substrate (1); a micro-bump (5) is further arranged in the cavity (2), a first through hole (3) is further formed in the substrate (1), and the micro-bump (5) is arranged between the first through hole (3) and the pixel (9); the cavity (2) is filled with filler with high isolation, easy heat conduction and mutually matched thermal expansion coefficients.
2. The three-dimensional integrated circuit structure of the large-area-array high-frame-rate high-reliability miniaturized image sensor according to claim 1, wherein: the circuit board is characterized in that a second RDL layer (7-1) is arranged below the substrate (1), a welding ball (6) is arranged below the second RDL layer (7-1), and a reading circuit chip (12) is arranged below the welding ball (6).
3. A three-dimensional integrated circuit structure of a large area array high frame rate high reliability miniaturized image sensor according to claim 2, wherein: the first through hole (3) comprises a common through hole or a TSV through hole.
4. The three-dimensional integrated circuit structure of the large-area-array high-frame-rate high-reliability miniaturized image sensor according to claim 1, wherein: the substrate (1) is further provided with a second through hole (3-1), a bump (4) is arranged below the substrate (1), and the bump (4) corresponds to the second through hole (3-1).
5. The three-dimensional integrated circuit structure of the large-area-array high-frame-rate high-reliability miniaturized image sensor according to claim 4, wherein: the second via (3-1) comprises a common via or a TSV via.
6. The three-dimensional integrated circuit structure of the large-area-array high-frame-rate high-reliability miniaturized image sensor according to claim 1, wherein: the substrate (1) is made of one or more of silicon, germanium, silicon germanium alloy, silicon carbon alloy, silicon germanium carbon alloy, III-V semiconductor material, II-IV semiconductor material and organic semiconductor material.
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CN107851651A (en) * 2015-07-23 2018-03-27 索尼公司 Semiconductor device, its manufacture method and electronic equipment
CN108074944A (en) * 2016-11-14 2018-05-25 三星电子株式会社 Image sensor package
CN110085614A (en) * 2019-04-30 2019-08-02 德淮半导体有限公司 Back side illumination image sensor and its manufacturing method

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Publication number Priority date Publication date Assignee Title
CN101533836A (en) * 2008-12-12 2009-09-16 昆山锐芯微电子有限公司 Large-array CMOS image sensor and manufacturing method thereof
CN107851651A (en) * 2015-07-23 2018-03-27 索尼公司 Semiconductor device, its manufacture method and electronic equipment
CN108074944A (en) * 2016-11-14 2018-05-25 三星电子株式会社 Image sensor package
CN110085614A (en) * 2019-04-30 2019-08-02 德淮半导体有限公司 Back side illumination image sensor and its manufacturing method

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