CN202009001U - Ball grid array for chip scale package of imaging sensor - Google Patents
Ball grid array for chip scale package of imaging sensor Download PDFInfo
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- CN202009001U CN202009001U CN2010206293056U CN201020629305U CN202009001U CN 202009001 U CN202009001 U CN 202009001U CN 2010206293056 U CN2010206293056 U CN 2010206293056U CN 201020629305 U CN201020629305 U CN 201020629305U CN 202009001 U CN202009001 U CN 202009001U
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Abstract
The utility model provides a ball grid array for chip scale package of an imaging sensor, which aims to increase chip packaging yield in the prior art, reduce mutual interference of signals among chip base pins and increase the number of effective chips after unit wafers of the imaging sensor are packaged. The ball grid array is a rectangular array provided with a plurality of lines and a plurality of rows, and each grid of the rectangular array comprises at most one welding ball. Compared with the prior art, the ball grid array reduces the mutual interference of the signals among the chip base pins and increases the number of the effective chips after the unit wafers of the imaging sensor are packaged, and chip scale package quality of the imaging sensor is greatly improved by the aid of the design of the space and size of the welding ball.
Description
Technical field
The utility model relates to the semiconductor packaging field, particularly a kind of ball grid array that is used for the encapsulation of image sensor chip level.
Background technology
In order to adapt with existing miniaturization of electronic products, lightness, multifunctional integrated development trend, the encapsulation technology of integrated circuit (IC) chip also develops towards the direction of high density, multitube pin.Wherein, in order to reduce to encapsulate the back area of chip, improve pin densities, and improve chip cooling, ball grid array package structure (Ball Grid Array for example, BGA), (Wafer Level Package, WLP) etc. advanced encapsulation technology has become main flow for flip-chip (Flip Chip) and wafer-level packaging.
On the other hand, along with the development of image sensing technology, be applied to more and more widely in the various electronic products such as charge-coupled device (CCD) and complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor.And conventional images sensor array density is higher, and therefore, it is used to import, the number of pin of output signal is numerous.For described imageing sensor, prior art adopts the encapsulating structure of ball grid array that it is carried out wafer-level package usually.Yet, still there is certain problem in described encapsulating structure, carries out in the process of IMAQ, signal transmission at imageing sensor, and the signal that transmits on the numerous pin in the imageing sensor is easy to the phase mutual interference, influence the imageing sensor operate as normal, and then the image quality decrease that makes the collection acquisition.
Therefore, be necessary to provide a kind of ball grid array that is suitable for imageing sensor, to improve the quality of image sensor chip level encapsulation.
The utility model content
As seen, need provide a kind of ball grid array, be used for the chip of package image transducer, avoid signal phase mutual interference between the pin of described imageing sensor, to improve image sensor chip level package quality.
In order to address the above problem, in according to embodiment of the present utility model, a kind of ball grid array that is used for the encapsulation of image sensor chip level is provided, and described ball grid array is the rectangular array with a plurality of row, a plurality of row, and each lattice point of described rectangular array contains a soldered ball at the most.
Alternatively, the column pitch of described rectangular array is 0.62 millimeter to 1.02 millimeters, and the line space of described rectangular array is 0.47 millimeter to 0.87 millimeter.
Alternatively, described rectangular array comprises 6 row, 7 row, and the direction of wherein said row is consistent with the long side direction of image sensor chip pel array, and the direction of described row is consistent with the short side direction of image sensor chip pel array.
Alternatively, described ball grid array indicates all or part of soldered ball that comprises on the lattice point at have " soldered ball " expressed down.
| The 1st row | The 2nd row | The 3rd row | The 4th row | The 5th row | The 6th row | |
| The 1st row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
| The 2nd row | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
| The 3rd row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | ||
| The 4th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | |
| The 5th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
| The 6th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | ||
| The 7th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
Alternatively, described ball grid array in last table, do not have on the lattice point of " soldered ball " sign and outside the lattice point all, part or do not comprise invalid soldered ball.
Alternatively, the 1st row the 3rd row of described rectangular array, the 3rd row the 1st row, the 5th row the 6th row and the 6th row the 4th row comprise no more than 4 soldered ball in totally 4 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 4 lattice points.
Alternatively, the 1st row the 5th row of described rectangular array, the 1st row the 6th row, the 3rd row the 2nd row, the 4th row the 1st row, the 4th row the 5th row and the 7th row the 6th row comprise no more than 6 soldered ball in totally 6 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 6 lattice points.
Alternatively, the 3rd row the 5th row of described rectangular array, the 6th row the 3rd row or the 7th row the 5th row comprise no more than 3 soldered ball in totally 3 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 3 lattice points.
Alternatively, the 1st row the 4th row of described rectangular array, the 2nd row the 4th row or the 7th row the 1st row comprise no more than 3 soldered ball in totally 3 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 3 lattice points.
Alternatively, the sphere diameter of described soldered ball is less than or equal to 0.4 millimeter.
Alternatively, described ball grid array can be according to above-mentioned ball grid array left and right sides mirror image, spin upside down or the combination in any between them.
Compared with prior art, noise and the signal between pin that ball grid array of the present utility model has reduced image sensor chip disturb, improved the Chip Packaging quality, increase the effective number of chips after imageing sensor unit's wafer encapsulates, make the encapsulation yield of image sensor chip improve greatly.
Above characteristic of the present utility model and other characteristics are partly set forth embodiment hereinafter clearly.
Description of drawings
Read following detailed description by the reference accompanying drawing, can more easily understand feature of the present utility model, purpose and advantage non-limiting example.Wherein, same or analogous Reference numeral is represented same or analogous device.
Fig. 1 shows according to an embodiment of the present utility model, the structural representation of ball grid array 100;
Fig. 2 shows according to an embodiment of the present utility model, the generalized section of ball grid array 100.
Embodiment
Below in conjunction with accompanying drawing the utility model is described in detail.
Fig. 1 shows according to an embodiment of the present utility model, the structural representation of ball grid array 100.As shown in Figure 1, described ball grid array 100 is used to be arranged at image sensor chip 101, and described ball grid array 100 is for having the rectangular array of a plurality of row, a plurality of row, and each lattice point 103 of described rectangular array contains 1 soldered ball 105 at the most.In actual use, described soldered ball 105 can be effective soldered ball, and so-called effectively soldered ball is meant that the soldered ball 105 on the image sensor chip 101 has corresponding bonding pad on the printed circuit board (PCB) of correspondence, thereby realizes being connected of image sensor chip and printed circuit board (PCB); Described soldered ball 105 can also be invalid soldered ball, and so-called invalid soldered ball is meant that the soldered ball on the image sensor chip 101 does not have corresponding bonding pad on the printed circuit board (PCB) of correspondence, can't realize being connected of image sensor chip 101 and printed circuit board (PCB).
The lattice point 103 of so-called rectangular array is meant the unit area that constitutes described rectangular array, and the lattice point 103 that is arranged in order has promptly constituted 1 row or 1 row of rectangular array, and the row of described rectangular array should be vertical substantially mutually with the direction of row.
In specific embodiment, the column pitch of described ball grid array 100 is 0.62 millimeter to 1.02 millimeters, for example be 0.66 millimeter, 0.72 millimeter, 0.76 millimeter, 0.80 millimeter, 0.84 millimeter, 0.88 millimeter, 0.92 millimeter, 0.96 millimeter or 1.00 millimeters, and the column pitch of different adjacent two row lattice points can be identical or different; The line space of described ball grid array 100 is 0.47 millimeter to 0.87 millimeter, for example be 0.50 millimeter, 054 millimeter, 0.58 millimeter, 0.62 millimeter, 0.66 millimeter, 0.70 millimeter, 0.74 millimeter, 0.78 millimeter or 0.80 millimeter, and the line space of different adjacent two row lattice points can be identical or different.So-called column pitch is meant the average distance of the centreline space that adjacent two row lattice point centers constitute, and so-called line space is meant the average distance of the centreline space that adjacent two row lattice point centers constitute.
In actual applications, each lattice point in might not rectangular array all comprises soldered ball.Lattice point 103 also can select not to be provided with soldered ball 105.
As can be seen, the ball grid array 100 that described soldered ball 105 constitutes has arranging of rectangular array, and this makes each soldered ball 105 pairing pins be arranged to as far as possible away from adjacent pin, thereby the signal that reduces between pin disturbs, and then reduces the noise that causes because of encapsulation.
In specific embodiment, described soldered ball 105 is hemispherical, the sphere diameter of described soldered ball 105 is less than or equal to 0.4 millimeter, for example be 0.20 millimeter, 0.25 millimeter, 0.30 millimeter, 0.35 millimeter or 0.40 millimeter, and the sphere diameter of different soldered ball 105 can be identical or different.
For the ball grid array 100 that adopts above-mentioned setting, it can be so that corresponding printed circuit board (PCB) has enough spaces for the track cabling; Simultaneously, the encapsulation yield of the design raising imageing sensor of space between solder balls and size in the described ball grid array 100.
In a preferred embodiment, the rectangular array of described ball grid array 100 has 6 row, 7 row, wherein, the direction of described row is consistent with the long side direction of image sensor chip pel array, and the direction of described row is consistent with the short side direction of image sensor chip pel array.Further preferably, described ball grid array 100 is all or part of soldered ball 105 that includes on the following lattice point of expressing 103 that " soldered ball " sign is arranged, and described soldered ball 105 can be effective soldered ball, also can be invalid soldered ball.In another preferred embodiment, described ball grid array 100 in following table, do not have on the lattice point 103 of " soldered ball " sign and outside the lattice point 103 all, part or do not comprise invalid soldered ball.Need to prove; soldered ball 105 that comprises in the described ball grid array 100 and position thereof also only are not limited to the rectangular array of following table, by left and right sides mirror image for example, spin upside down or mirror image ball grid array 100 resulting with the modes such as combination in any that spin upside down and that this soldered ball arrangement mode is consistent in the left and right sides still belongs to the protection range of this patent.
| The 1st row | The 2nd row | The 3rd row | The 4th row | The 5th row | The 6th row | |
| The 1st row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
| The 2nd row | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
| The 3rd row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | ||
| The 4th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | |
| The 5th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
| The 6th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | ||
| The 7th row | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball | Soldered ball |
In actual applications, the different lattice points of rectangular array may be corresponding to the different pins of image sensor chip to be packaged, for example the signal input tube pin of image sensor chip, signal output pin, power supply biasing pin or common potential pin etc.And need based on the performance design of for example image sensor chip itself, the pin of realizing some function on the described image sensor chip can be for a plurality of, and for example the 1st row the 3rd corresponding to ball grid array is listed as on the image sensor chip, the 3rd row the 1st is listed as, the pin of the lattice point position of the 5th row the 6th row can all have the function of introducing bias supply.In this case, if image sensor chip inside connects the pin with identical function by leads such as for example interconnection lines, then can omit pin one or more with identical function.Correspondingly, can omit one or more soldered balls on the lattice point of described ball grid array correspondence.
Based on above-mentioned explanation, in a preferred embodiment of the present utility model, the 1st row the 3rd row of described rectangular array, the 3rd row the 1st row, the 5th row the 6th row and the 6th row the 4th row lattice point comprise no more than 4 soldered ball in totally 4 lattice points, for example include 1,2,3 or 4 soldered ball altogether, described soldered ball is distributed in arbitrarily on all or part of lattice point of these 4 lattice points.
In another preferred embodiment, the 1st row the 5th row of described rectangular array, the 1st row the 6th row, the 3rd row the 2nd row, the 4th row the 1st row, the 4th row the 5th row and the 7th row the 6th row lattice point comprise no more than 6 soldered ball in totally 6 lattice points, for example include 1,2,3,4,5 or 6 soldered ball altogether, described soldered ball is distributed in arbitrarily on all or part of lattice point of these 6 lattice points.
In another preferred embodiment, the 3rd row the 5th row, the 6th row the 3rd row or the 7th row the 5th row lattice point of described rectangular array comprise no more than 3 soldered ball in totally 3 lattice points, for example include 1,2 or 3 soldered ball altogether, described soldered ball is distributed in arbitrarily on all or part of lattice point of these 3 lattice points.
In a preferred embodiment again, the 1st row the 4th row, the 2nd row the 4th row or the 7th row the 1st row lattice point of described rectangular array comprise no more than 3 soldered ball in totally 3 lattice points, for example include 1,2 or 3 soldered ball altogether, described soldered ball is distributed in arbitrarily on all or part of lattice point of these 3 lattice points.
Fig. 2 shows according to an embodiment of the present utility model, the generalized section of ball grid array 100.As shown in Figure 2, described ball grid array 100 is arranged on the image sensor chip 101, and described image sensor chip 101 is connected on the substrate 107 by salient point 109, and described substrate 107 for example is a glass substrate.The soldered ball 105 that described ball grid array 100 comprises is hemispherical, and the height of described soldered ball 105 is for example 0.05 millimeter to 0.20 millimeter.
More than specific embodiment of the utility model is described.It will be appreciated that the utility model is not limited to above-mentioned specific implementations, those skilled in the art can make various distortion or modification within the scope of the appended claims.
Claims (11)
1. a ball grid array that is used for the encapsulation of image sensor chip level is characterized in that described ball grid array is the rectangular array with a plurality of row, a plurality of row, and each lattice point of described rectangular array contains a soldered ball at the most.
2. ball grid array according to claim 1 is characterized in that, the column pitch of described rectangular array is 0.62 millimeter to 1.02 millimeters, and the line space of described rectangular array is 0.47 millimeter to 0.87 millimeter.
3. ball grid array according to claim 2, it is characterized in that, described rectangular array comprises 6 row, 7 row, and the direction of wherein said row is consistent with the long side direction of image sensor chip pel array, and the direction of described row is consistent with the short side direction of image sensor chip pel array.
4. ball grid array according to claim 3 is characterized in that, all or part of soldered ball that comprises on " soldered ball " sign lattice point that has that described ball grid array is being expressed down.
5. ball grid array according to claim 4 is characterized in that, described ball grid array in last table, do not have on the lattice point of " soldered ball " sign and outside the lattice point all, part or do not comprise invalid soldered ball.
6. ball grid array according to claim 4, it is characterized in that, the 1st row the 3rd row of described rectangular array, the 3rd row the 1st row, the 5th row the 6th row and the 6th row the 4th row comprise no more than 4 soldered ball in totally 4 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 4 lattice points.
7. ball grid array according to claim 4, it is characterized in that, the 1st row the 5th row of described rectangular array, the 1st row the 6th row, the 3rd row the 2nd row, the 4th row the 1st row, the 4th row the 5th row and the 7th row the 6th row comprise no more than 6 soldered ball in totally 6 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 6 lattice points.
8. ball grid array according to claim 4, it is characterized in that, the 3rd row the 5th row of described rectangular array, the 6th row the 3rd row or the 7th row the 5th row comprise no more than 3 soldered ball in totally 3 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 3 lattice points.
9. ball grid array according to claim 4, it is characterized in that, the 1st row the 4th row of described rectangular array, the 2nd row the 4th row or the 7th row the 1st row comprise no more than 3 soldered ball in totally 3 lattice points, and described soldered ball is distributed in arbitrarily on all or part of lattice point of these 3 lattice points.
10. according to each described ball grid array of claim 1 to 9, it is characterized in that the sphere diameter of described soldered ball is less than or equal to 0.4 millimeter.
11. a ball grid array is characterized in that, described ball grid array be according to each described ball grid array of claim 1 to 10 left and right sides mirror image, spin upside down or the combination in any between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206293056U CN202009001U (en) | 2010-11-26 | 2010-11-26 | Ball grid array for chip scale package of imaging sensor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010206293056U CN202009001U (en) | 2010-11-26 | 2010-11-26 | Ball grid array for chip scale package of imaging sensor |
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| CN202009001U true CN202009001U (en) | 2011-10-12 |
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| CN2010206293056U Expired - Lifetime CN202009001U (en) | 2010-11-26 | 2010-11-26 | Ball grid array for chip scale package of imaging sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106331535A (en) * | 2015-07-06 | 2017-01-11 | 上海瑞艾立光电技术有限公司 | Image collection system |
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2010
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106331535A (en) * | 2015-07-06 | 2017-01-11 | 上海瑞艾立光电技术有限公司 | Image collection system |
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| C14 | Grant of patent or utility model | ||
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Granted publication date: 20111012 |
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