CN111029247A - Preparation method of oxide layer for reducing dark current and composite structure - Google Patents

Preparation method of oxide layer for reducing dark current and composite structure Download PDF

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CN111029247A
CN111029247A CN201911283396.4A CN201911283396A CN111029247A CN 111029247 A CN111029247 A CN 111029247A CN 201911283396 A CN201911283396 A CN 201911283396A CN 111029247 A CN111029247 A CN 111029247A
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oxide layer
silicon substrate
dark current
etching
diffusion furnace
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CN111029247B (en
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李亭亭
贺晓彬
项金娟
王晓磊
李俊峰
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Institute of Microelectronics of CAS
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Abstract

The invention discloses a preparation method of an oxide layer for reducing dark current and a composite structure, belongs to the technical field of dark current, and solves the problems of poor quality of the oxide layer, large dark current, long production time and high cost in the prior art. The preparation method of the oxide layer comprises the following steps: cleaning the silicon substrate and removing a natural oxidation layer; forming an oxide layer on the silicon substrate by adopting an oxidation process; forming a photoetching pattern on the surface of the oxide layer by using a photoetching technology; and forming a groove structure on the oxide layer by etching. The oxide layer composite structure for reducing dark current comprises a silicon substrate and an oxide layer which are arranged in a stacked mode, wherein a groove structure is formed in the oxide layer. The oxide layer and the composite structure prepared by the preparation method have the advantages of short production time and small dark current.

Description

Preparation method of oxide layer for reducing dark current and composite structure
Technical Field
The invention relates to the technical field of dark current, in particular to a preparation method of an oxide layer for reducing dark current and a composite structure.
Background
In a photodetector device, dark current is an important parameter of such devices. The dark current is increased, so that the noise power of the detector is increased, the detection sensitivity is reduced, and the performance of the detector is influenced; the magnitude of the dark current is directly related to the quality of the oxide layer, if the oxide layer has more defects, the dark current of the product is directly increased, and the current process for preparing the oxide layer is generally completed by adopting a process of oxide layer growth twice, namely a process of dry oxidation-wet oxidation-dry oxidation of the first thick oxide layer; and then completely etching the first oxide layer, and then carrying out second oxidation. In the existing two-time oxide layer growth process, the quality of an oxide layer is poor due to interface defects in the second-time oxide layer growth process, and further the dark current of a product is large; and because the growth is carried out twice, the production time is longer and the cost is higher.
Disclosure of Invention
In view of the above analysis, the present invention aims to provide a method for preparing an oxide layer to reduce dark current and a composite structure, which can solve at least one of the following technical problems: (1) in the two oxide layer growth processes, the quality of the oxide layer is poor due to interface defects in the second oxide layer growth process; (2) the dark current of the product is large; (3) the production time is longer and the cost is higher.
The purpose of the invention is mainly realized by the following technical scheme:
the invention provides a preparation method of an oxide layer for reducing dark current, which comprises the following steps:
step S1, cleaning the silicon substrate and removing the natural oxidation layer;
step S2, forming an oxide layer on the silicon substrate by adopting an oxidation process;
step S3, forming a photoetching pattern on the surface of the oxide layer by using a photoetching technology;
and step S4, forming a groove structure on the oxide layer by etching.
In one possible design, step S1 includes the following steps:
step S11, cleaning the silicon substrate for the first time by adopting a mixed solution of concentrated sulfuric acid and hydrogen peroxide;
step S12, carrying out secondary cleaning on the silicon substrate by adopting a mixed aqueous solution of ammonia water and hydrogen peroxide;
and step S13, removing the natural oxide layer by adopting hydrofluoric acid solution.
In one possible design, in step S11, the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide solution is 4: 1.
In one possible design, in step S12, the volume ratio of ammonia water, hydrogen peroxide and water in the mixed aqueous solution of ammonia water and hydrogen peroxide is 1:4: 25.
In one possible design, step S2 includes the following steps:
step S21, the silicon substrate enters a diffusion furnace at the temperature of T1, and oxygen with the flow rate of a1 and nitrogen with the flow rate of b1 are introduced at the moment when the silicon substrate enters the furnace;
s22, after the silicon substrate completely enters the diffusion furnace, heating the diffusion furnace to T2, and stabilizing for 10-15 min; then introducing oxygen at a flow rate of a2 for dry oxidation, and then introducing hydrogen at a flow rate of c1 and oxygen at a flow rate of a3 for wet oxidation; completing the growth of an oxide layer;
s23, after the oxide layer grows, cooling the diffusion furnace to T1, and then removing the silicon substrate with the oxide layer out of the diffusion furnace;
wherein, a1< a3< a 2.
In one possible design, step S3 includes the following steps:
s31, performing surface hydrophobization treatment on the oxide layer;
s32, coating photoresist on the surface of the oxide layer;
and S33, baking, exposing, developing and curing the coated photoresist.
In one possible design, in S33, the baking temperature is 85-95 ℃ and the baking time is 85-95S.
In a possible design, in step S4, the etching process adopted is to place the silicon substrate processed in step S3 in a reaction tank for wet etching, the etching liquid is BOE, and the BOE comprises the following components by volume percent: HF: 6.23% -6.43%, NH 4F: 34.3% -35.3%, H2O: 41.5 to 59.5 percent.
In one possible design, the temperature of the wet etching in step S4 is 5-15 ℃.
The invention also provides an oxide layer composite structure for reducing dark current, which comprises a silicon substrate (1) and an oxide layer (2) which are arranged in a stacked mode, wherein the oxide layer (2) is provided with a groove structure (3).
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
a) according to the method for preparing the oxide layer for reducing the dark current, the oxide layer can be formed on the surface of the silicon substrate through one-time oxide layer growth (dry method + wet method oxidation) and one-time etching process, so that the process steps can be saved, and the contamination of the exposed silicon surface in the subsequent process after the silicon oxide is completely etched for the first time in the traditional process can be effectively avoided; the reason is that the 'dangling bond' on the surface of the monocrystalline silicon has strong attraction, other atoms and molecules in the surrounding environment can be adsorbed on the surface, and the surface exposed in the air can also form a 3-4nm thin oxide layer due to the oxidation effect of the air; these can cause contamination of the silicon substrate surface, and the contamination of the silicon substrate surface can directly affect the quality of the regrown oxide layer where body defects are formed, thereby affecting the dark current of the device. Therefore, the process can effectively reduce the defects of the oxide layer, thereby reducing the dark current of the product.
b) According to the preparation method of the oxide layer for reducing the dark current, provided by the invention, the oxide layer with more uniform thickness and better surface quality and meeting the use requirement is obtained by accurately controlling the parameters of dry oxidation, photoetching and etching processes, and the prepared oxide layer can reduce the dark current of a product.
c) The preparation method of the oxide layer for reducing the dark current provided by the invention has simple procedures, shortens the process flow compared with the traditional process, saves a large amount of time and reduces the cost.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a schematic diagram of an oxide layer composite structure for reducing dark current according to the present invention;
FIG. 2 is a diagram illustrating a test result of a conventional oxide layer;
fig. 3 is a diagram illustrating the test results of the oxide layer of the present application.
Reference numerals:
1-a silicon substrate; 2-an oxide layer; 3-groove structure.
Detailed Description
The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and which together with the embodiments of the invention serve to explain the principles of the invention.
The invention provides a preparation method of an oxide layer for reducing dark current, which comprises the following steps:
step S1, cleaning the silicon substrate and removing the natural oxidation layer;
step S2, forming an oxide layer 2 (e.g., a silicon dioxide layer) on the silicon substrate 1 by using an oxidation process;
step S3, forming a photoetching pattern on the surface of the oxide layer 2 by using a photoetching technology;
step S4, forming a groove structure 3 on the oxide layer 2 by etching.
Specifically, the step S1 includes the following steps: firstly, cleaning a silicon substrate by using a cleaning solution, wherein the cleaning is mainly used for cleaning the surface of the silicon substrate and preventing the surface from being polluted; and then, removing the natural oxide layer on the surface of the silicon substrate by adopting a hydrofluoric acid solution to prevent the natural oxide layer from influencing the quality of the grown oxide layer.
Specifically, the step S1 includes the following steps:
step S11, cleaning the silicon substrate for the first time by adopting a mixed solution of concentrated sulfuric acid and hydrogen peroxide, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 4: 1;
and step S12, carrying out secondary cleaning on the silicon substrate by adopting a mixed aqueous solution of ammonia water and hydrogen peroxide, wherein the volume ratio of the ammonia water to the hydrogen peroxide to the water is 1:4: 25.
And step S13, removing the natural oxide layer by adopting hydrofluoric acid solution.
Specifically, in step S13, the silicon substrate is damaged by an excessively high concentration of the hydrofluoric acid solution, and the reaction time is too long and the efficiency is low due to an excessively low concentration. Thus, the volume ratio of HF to water in the hydrofluoric acid solution was controlled to be 1: 8-12, preferably, the volume ratio of HF to water in the hydrofluoric acid solution is 1: 10.
specifically, in step S2, the oxide layer 2 is grown by using an oxidation process of dry oxidation and wet oxidation in a diffusion furnace, and the principle is as follows: dry oxidation of Si + O2→SiO2Wet oxidation of Si +2H2O→2H2+SiO2。
Specifically, the step S2 includes the following steps:
step S21, the silicon wafer (i.e. the silicon substrate) enters a diffusion furnace at the temperature of T1(680-720 ℃), and in order to optimize the interface between the silicon dioxide film and the silicon substrate and improve the interface quality, oxygen with the flow rate of a1 and nitrogen with the flow rate of b1 (nitrogen is used as inert protective gas) are introduced at the moment when the silicon wafer enters the furnace; considering that the silicon wafer enters the diffusion furnace from room temperature, the temperature in the diffusion furnace is high, and in order to prevent the silicon wafer from deforming, the process that the silicon wafer enters the diffusion furnace cannot be too fast, and the total time of entering the furnace is controlled to be 20-25 min;
s22, after the silicon wafer completely enters the diffusion furnace, heating the diffusion furnace to T2 at a speed of V1, and stabilizing for 10-15 min; then introducing oxygen at a2 flow rate for dry oxidation, and then introducing hydrogen at a c1 flow rate and oxygen at a3 flow rate for wet oxidation (the process time can be reduced by adopting wet oxidation because the wet oxidation speed is faster and the time is shorter); completing the growth of an oxide layer;
and S23, after the growth of the oxide layer is finished, cooling the diffusion furnace to T1 at the speed of V2, and then moving the silicon wafer with the oxide layer out of the diffusion furnace, wherein in order to prevent the silicon wafer from deforming, the process of moving the silicon wafer out of the diffusion furnace cannot be too fast, and the total time of discharging the silicon wafer is controlled to be 20-25 min.
Specifically, in step S22, in order to reduce defects of the oxide layer and improve the quality of the oxide layer growth, ethylene dichloride is introduced while oxygen is introduced.
Wherein a1< a3< a2, illustratively, a1 is 1-1.5L/min; a2 is 18-20L/min; a3 is 16-17.5L/min.
Wherein, c1 is a 3.
Wherein b1 is 19-21L/min; illustratively, b1 is 20L/min.
Wherein, V1 is V2, and V1 and V2 are both 3-5 ℃/min; exemplarily, V1-V2-5 ℃/min.
Where T1 is 680-720 deg.C, and exemplary T1 is 700 deg.C.
Specifically, T2 is 900-.
Specifically, step S3 includes the following steps:
s31, performing surface hydrophobization treatment on the oxide layer;
s32, coating photoresist on the surface of the oxide layer;
s33, baking, exposing, developing and curing the coated photoresist;
in S31, considering that the surface state of the oxide layer directly affects the adhesion of the photoresist, the photoresist is hydrophobic, and therefore the surface of the oxide layer needs to be hydrophobized; specifically, the surface hydrophobization treatment needs to heat the oxide layer in the steam atmosphere of HMDS with the temperature of T3 for T1 time to remove the surface hydrogen-oxygen bonds, so as to achieve the purpose of changing the surface of the oxide layer into hydrophobicity;
specifically, T3 was 105 ℃ and 115 ℃, and preferably, T3 was 110 ℃.
Specifically, t1 is 110-130s, preferably t1 is 120 s.
In S32, in order to achieve a better lithography effect, the film thickness of the photoresist needs to be strictly controlled, and if the film thickness is too large, the lithography pattern is likely to collapse, and if the film thickness is too small, the uniformity of the photoresist coating is poor, so that the film thickness of the photoresist is controlled to be 3-5 mm; in order to ensure the film thickness of the photoresist, the film forming rotating speed of the photoresist needs to be adjusted, and the edge of the silicon wafer can form wind veins due to the overlarge film forming rotating speed, so that the edge gluing is poor; if the film forming rotating speed is too low, the gluing uniformity can be poor, and the difference of the gluing thickness in the whole silicon wafer is large. Therefore, the film formation speed of the photoresist is controlled to be 2950 and 3050 rpm.
In the above S33, after the photoresist is coated, in order to evaporate the organic solvent in the photoresist, the coated photoresist needs to be baked at 85-95 ℃ for 85-95S; lithography can use contact or projection lithography machines depending on the specific design dimensions.
Specifically, after exposure is finished, the exposed photoresist needs to be developed, and in order to obtain a better photoresist morphology, the developing temperature and time need to be strictly controlled, for example, the developing is performed at normal temperature (15-28 ℃); the developing time is controlled to be 55-65s, preferably 60s, considering that the developing is not clean when the developing time is too short and the pattern is displayed when the developing time is too long.
In S33, in order to perform the next etching step smoothly, the photoresist needs to be cured at a temperature of 130 ℃ to 150 ℃ for 30-50 min.
Specifically, in the step S4, the etching process adopted is to perform wet etching on the silicon wafer processed in the step S3 in a reaction tank, the etching liquid is BOE, and the BOE comprises the following components in percentage by volume: HF: 6.23% -6.43% of NH4F：34.3％-35.3％、H2O: 41.5% -59.5%; wherein NH4F is a buffer solution to make up for the loss of fluorine ions in the process of corroding the oxide and reduce the corrosion rate of the glue; the BOE adopting the component aims to prevent the corrosion rate of silicon dioxide from being too fast, and the too fast corrosion rate can cause the uncontrollable process; concretely, the reverseThe principle is as follows: SiO 22+6HF→H2SF6+2H2O。
Specifically, in step S4, considering that the reaction temperature also has a direct influence on the corrosion rate, the reaction temperature needs to be controlled at a constant value; with the rise of the temperature of the solution, the etching rate is increased sharply, and the time required for etching the same depth is reduced correspondingly; in order to obtain a uniform oxide layer, the process temperature needs to be controlled at a lower temperature, so that the temperature of the wet etching is controlled to be 5-15 ℃.
Specifically, in step S4, considering that the improvement of the temperature control precision of the etching liquid is a necessary condition for improving the etching uniformity, in order to improve the temperature uniformity of the whole etching environment, an overflow circulation manner is adopted, i.e., the reaction liquid is sucked out by a circulation pump, treated by a heat exchanger, and then uniformly injected into the reaction tank, and the process is repeated continuously, so as to ensure the stability of the process temperature.
Specifically, in step S4, the etching depth is too deep due to too long etching time, and the etching depth is too shallow due to too short etching time, so the etching time is controlled to be 4-5 min.
Specifically, in the step S4, the etching depth is 450-550 nm.
The invention also provides an oxide layer composite structure for reducing dark current, which is shown in figure 1 and comprises a silicon substrate 1 and an oxide layer 2 which are arranged in a laminated manner, wherein a groove structure 3 is arranged on the oxide layer 2, and the depth of the groove structure 3 is 450-550 nm.
Example 1
The method for preparing the oxide layer for reducing dark current in the embodiment includes the following steps:
step S1, cleaning the silicon substrate and removing the natural oxidation layer;
specifically, step S1 includes: step S11, cleaning the silicon substrate for the first time by adopting a mixed solution of concentrated sulfuric acid and hydrogen peroxide, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 4: 1;
step S12, carrying out secondary cleaning on the silicon substrate by adopting a mixed aqueous solution of ammonia water and hydrogen peroxide, wherein the volume ratio of the ammonia water to the hydrogen peroxide to the water is 1:4: 25;
step S13, removing the natural oxide layer by adopting hydrofluoric acid solution; the volume ratio of HF to water in the hydrofluoric acid solution is 1: 10.
step S2, forming an oxide layer 2 (silicon dioxide thin film) on the silicon substrate 1 by using a diffusion furnace to perform an oxidation process of dry-process and wet-process oxidation; specifically, a silicon wafer (i.e. a silicon substrate) enters a diffusion furnace at 700 ℃, and 1L/min of oxygen and 20L/min of nitrogen are introduced at the moment when the silicon wafer enters the furnace; after the silicon chip completely enters the diffusion furnace (the time of entering the furnace is 20min totally), heating the diffusion furnace to 900 ℃ at the speed of 5 ℃/min, and stabilizing for 15 min; then introducing 19L/min of oxygen and dichloroethylene for dry oxidation, and then introducing 17L/min of hydrogen and 17L/min of oxygen for wet oxidation; and after the growth of the oxide layer is finished, cooling the diffusion furnace to 700 ℃ at the speed of 5 ℃/min, and then removing the silicon wafer with the oxide layer out of the diffusion furnace (discharging for 20 min).
Step S3, forming a photolithography pattern (e.g., a rectangle) on the surface of the oxide layer 2 by using a photolithography technique; specifically, step S3 includes the following steps:
s31, performing surface hydrophobization treatment on the oxide layer; heating the oxide layer in a vapor atmosphere of HMDS at 110 ℃ for 120 s;
s32, coating photoresist on the surface of the oxide layer; specifically, the film forming speed of the photoresist is 3000rpm, and the film thickness of the photoresist is 4 mm;
s33, baking the coated photoresist (baking temperature is 90 ℃, baking time is 90S), exposing, developing (developing temperature is 20 ℃, developing time is 60S) and curing (curing temperature is 140 ℃, curing time is 40min) in sequence.
Step S4, forming a groove structure 3 on the oxide layer 2 by etching;
specifically, in step S4, the etching process adopted is wet etching, the etching liquid is BOE, and the BOE comprises the following components in percentage by volume: HF: 6.23% NH4F：35％、H2O: 58.77 percent; the etching temperature is 10 ℃, the etching time is 4.5min, and the etching depth is 500 nm.
Total time: and 7 h.
Example 2
The method for preparing the oxide layer for reducing dark current in the embodiment includes the following steps:
step S1, cleaning the silicon substrate and removing the natural oxidation layer;
specifically, step S1 includes: step S11, cleaning the silicon substrate for the first time by adopting a mixed solution of concentrated sulfuric acid and hydrogen peroxide, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 4: 1;
step S12, carrying out secondary cleaning on the silicon substrate by adopting a mixed aqueous solution of ammonia water and hydrogen peroxide, wherein the volume ratio of the ammonia water to the hydrogen peroxide to the water is 1:4: 25;
step S13, removing the natural oxide layer by adopting hydrofluoric acid solution; the volume ratio of HF to water in the hydrofluoric acid solution is 1: 10.
step S2, forming an oxide layer 2 (silicon dioxide thin film) on the silicon substrate 1 by using a diffusion furnace to perform an oxidation process of dry-process and wet-process oxidation; specifically, a silicon wafer (i.e. a silicon substrate) enters a diffusion furnace at 700 ℃, and 1L/min of oxygen and 20L/min of nitrogen are introduced in the process of entering the furnace; after the silicon wafer completely enters the diffusion furnace (the time of entering the furnace is 25min totally), heating the diffusion furnace to 1050 ℃ at the speed of 5 ℃/min, and stabilizing for 10 min; then introducing 19L/min of oxygen and dichloroethylene for dry oxidation, and then introducing 17L/min of hydrogen and 17L/min of oxygen for wet oxidation; and after the growth of the oxide layer is finished, cooling the diffusion furnace to 700 ℃ at the speed of 5 ℃/min, and then removing the silicon wafer with the oxide layer out of the diffusion furnace (discharging for 25 min).
Step S3, forming a photolithography pattern (e.g., a rectangle) on the surface of the oxide layer 2 by using a photolithography technique; specifically, step S3 includes the following steps:
s31, performing surface hydrophobization treatment on the oxide layer; heating the oxide layer in a vapor atmosphere of HMDS at 105 ℃ for 130 s;
s32, coating photoresist on the surface of the oxide layer; specifically, the film forming rotation speed of the photoresist is 2950rpm, and the film thickness of the photoresist is 3 mm;
s33, baking the coated photoresist (baking temperature is 85 ℃, baking time is 95S), exposing, developing (developing temperature is 15 ℃, developing time is 65S) and curing (curing temperature is 130 ℃, curing time is 50min) in sequence.
Step S4, forming a groove structure 3 on the oxide layer 2 by etching;
specifically, in step S4, the etching process adopted is wet etching, the etching liquid is BOE, and the BOE comprises the following components in percentage by volume: HF: 6.43% NH4F：34.3％、H2O: 59.27 percent; the etching temperature is 5 ℃, the etching time is 5min, and the etching depth is 500 nm.
Total time: 7.3 h.
Example 3
The method for preparing the oxide layer for reducing dark current in the embodiment includes the following steps:
step S1, cleaning the silicon substrate and removing the natural oxidation layer;
specifically, step S1 includes: step S11, cleaning the silicon substrate for the first time by adopting a mixed solution of concentrated sulfuric acid and hydrogen peroxide, wherein the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide is 4: 1;
step S12, carrying out secondary cleaning on the silicon substrate by adopting a mixed aqueous solution of ammonia water and hydrogen peroxide, wherein the volume ratio of the ammonia water to the hydrogen peroxide to the water is 1:4: 25;
step S13, removing the natural oxide layer by adopting hydrofluoric acid solution; the volume ratio of HF to water in the hydrofluoric acid solution is 1: 10;
step S2, forming an oxide layer 2 (silicon dioxide thin film) on the silicon substrate 1 by using a diffusion furnace to perform an oxidation process of dry-process and wet-process oxidation; specifically, a silicon wafer (i.e. a silicon substrate) enters a diffusion furnace at 700 ℃, and 1.5L/min of oxygen and 21L/min of nitrogen are introduced into the diffusion furnace in the process of entering the silicon wafer into the furnace; after the silicon chip completely enters the diffusion furnace (the time of entering the furnace is 20min totally), heating the diffusion furnace to 1000 ℃ at the speed of 5 ℃/min, and stabilizing for 10 min; then introducing 19L/min of oxygen and dichloroethylene for dry oxidation, and then introducing 17.5L/min of hydrogen and 17.5L/min of oxygen for wet oxidation; and after the growth of the oxide layer is finished, cooling the diffusion furnace to 700 ℃ at the speed of 5 ℃/min, and then removing the silicon wafer with the oxide layer out of the diffusion furnace (discharging for 25 min).
Step S3, forming a photolithography pattern (e.g., a rectangle) on the surface of the oxide layer 2 by using a photolithography technique; specifically, step S3 includes the following steps:
s31, performing surface hydrophobization treatment on the oxide layer; heating the oxide layer in the vapor atmosphere of HMDS at 115 ℃ for 110 s;
s32, coating photoresist on the surface of the oxide layer; specifically, the film forming speed of the photoresist is 3050rpm, and the film thickness of the photoresist is 5 mm;
s33, baking the coated photoresist (baking temperature is 95 ℃ and baking time is 85S), exposing, developing (developing temperature is 28 ℃ and developing time is 55S) and curing (curing temperature is 150 ℃ and curing time is 30min) in sequence.
Step S4, forming a groove structure 3 on the oxide layer 2 by etching;
specifically, in step S4, the etching process adopted is wet etching, the etching liquid is BOE, and the BOE comprises the following components in percentage by volume: HF: 6.33% NH4F：35.3％、H2O: 58.37 percent; the etching temperature is 15 ℃, the etching time is 3min, and the etching depth is 500 nm.
Total time: 6.6 h.
Comparative example 1
The oxide layer is prepared by adopting a traditional two-step method, and the total time is 15 h.
The oxide layer prepared in example 1 of the present invention and the oxide layer prepared in comparative example 1 were tested using a CV tester, and the test results are shown in table 1 (fig. 2 is the test result of comparative example 1, and fig. 3 is the test result of example 1). As can be seen from table 1, when the same voltage is applied to the oxide layer, the dark current of example 1 is significantly smaller than that of comparative example 1, which shows that the process flow of the present invention can effectively improve the quality of the oxide layer, reduce the dark current, and reduce the dark spot current by more than one order of magnitude compared with the conventional process.
The oxide layer prepared in the embodiment 2-3 of the invention is tested by a CV tester, and the dark current is obviously reduced.
The preparation time of the embodiments 1 to 3 of the invention can save one-step cleaning and one-step oxidation respectively, and the preparation time is saved by more than 7.5h (for example, 7.7 to 8.4h) compared with the comparative example. Therefore, the preparation time of the invention is far shorter than that of a comparative example, the efficiency is obviously improved, and the cost is reduced.
Table 1 test results of example 1 and comparative example 1
Figure BDA0002317370300000131
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims (10)

1. A method for preparing an oxide layer for reducing dark current is characterized by comprising the following steps:
step S1, cleaning the silicon substrate and removing the natural oxidation layer;
step S2, forming an oxide layer on the silicon substrate by adopting an oxidation process;
step S3, forming a photoetching pattern on the surface of the oxide layer by using a photoetching technology;
and step S4, forming a groove structure on the oxide layer by etching.
2. The method of claim 1, wherein the step S1 comprises the steps of:
step S11, cleaning the silicon substrate for the first time by adopting a mixed solution of concentrated sulfuric acid and hydrogen peroxide;
step S12, carrying out secondary cleaning on the silicon substrate by adopting a mixed aqueous solution of ammonia water and hydrogen peroxide;
and step S13, removing the natural oxide layer by adopting hydrofluoric acid solution.
3. The method for preparing an oxide layer for reducing dark current according to claim 2, wherein in the step S11, the volume ratio of the concentrated sulfuric acid to the hydrogen peroxide solution is 4: 1.
4. The method for preparing an oxide layer for reducing dark current according to claim 2, wherein in step S12, the volume ratio of ammonia water to hydrogen peroxide to water is 1:4: 25.
5. The method of claim 1, wherein the step S2 comprises the steps of:
step S21, the silicon substrate enters a diffusion furnace at the temperature of T1, and oxygen with the flow rate of a1 and nitrogen with the flow rate of b1 are introduced at the moment when the silicon substrate enters the furnace;
s22, after the silicon substrate completely enters the diffusion furnace, heating the diffusion furnace to T2, and stabilizing for 10-15 min; then introducing oxygen at a flow rate of a2 for dry oxidation, and then introducing hydrogen at a flow rate of c1 and oxygen at a flow rate of a3 for wet oxidation; completing the growth of an oxide layer;
s23, after the oxide layer grows, cooling the diffusion furnace to T1, and then removing the silicon substrate with the oxide layer out of the diffusion furnace;
wherein, a1< a3< a 2.
6. The method of claim 1, wherein the step S3 comprises the steps of:
s31, performing surface hydrophobization treatment on the oxide layer;
s32, coating photoresist on the surface of the oxide layer;
and S33, baking, exposing, developing and curing the coated photoresist.
7. The method as claimed in claim 6, wherein in S33, the baking temperature is 85-95 ℃ and the baking time is 85-95S.
8. The method for preparing an oxide layer to reduce dark current according to claims 1 to 7, wherein in step S4, the etching process is to place the silicon substrate processed in step S3 in a reaction tank for wet etching, the etching liquid is BOE, and the BOE comprises, by volume: HF: 6.23% -6.43% of NH4F：34.3％-35.3％、H2O：41.5％-59.5％。
9. The method as claimed in claim 8, wherein the wet etching temperature in step S4 is 5-15 ℃.
10. A dark current reducing oxide layer composite structure, characterized in that, it is made by the method for preparing a dark current reducing oxide layer according to claims 1-9, comprising a silicon substrate (1) and an oxide layer (2) arranged in a stack, the oxide layer (2) having a groove structure (3).
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Publication number Priority date Publication date Assignee Title
EP0022580A1 (en) * 1979-07-17 1981-01-21 Western Electric Company, Incorporated Advantageous fabrication technique for devices relying on magnetic properties
US6287929B1 (en) * 1999-08-19 2001-09-11 Nec Corporation Method of forming a bipolar transistor for suppressing variation in base width
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