CN111025244A - Signal detection device, signal detection method and radar system - Google Patents

Abstract

The present invention relates to the field of radar technologies, and in particular, to a signal detection apparatus, a signal detection method, and a radar system. The signal detection device provided by the invention comprises a ring-shaped register link, a data acquisition unit and a data processing unit, wherein the ring-shaped register link is used for updating the value of a corresponding data bit in indication data according to each signal edge of a signal to be detected, and the frequency of the signal to be detected linearly changes in a detection interval; and the processing circuit is used for obtaining a measured value according to the initial value and the end value of the indication data in the detection interval and obtaining detection result data according to the offset between the measured value and a preset expected value corresponding to the detection interval so as to enable the detection result data to represent whether the average value of the frequency of the signal to be detected in the detection interval meets an expected range or not. The radar system, the signal detection device and the signal detection method can monitor the frequency of the signal to be detected in real time, so that whether the signal to be detected is in a normal state or not is judged.

Description

Signal detection device, signal detection method and radar system

Technical Field

The present invention relates to the field of radar technologies, and in particular, to a signal detection apparatus, a signal detection method, and a radar system.

Background

In the radar system, the frequency difference between the echo signal and the transmitted signal can be obtained by transmitting and receiving the frequency modulation continuous wave, so that the information such as the distance and the speed of the target can be obtained according to the frequency difference. The modulation mode adopting the frequency modulation continuous wave has the outstanding advantages of simple realization structure, simple signal processing process, low cost, low power and the like, and is widely applied to the fields of vehicle-mounted radars and the like.

Because the frequency of the frequency modulation continuous wave is constantly changed in the working process of the radar system, the frequency state of the frequency modulation continuous wave can be used for judging whether modules such as a phase-locked loop and the like in the radar system are in a normal working state.

Based on this, it is desirable to provide a frequency detection scheme for frequency modulated continuous waves, which is used to determine whether the radar system is in a normal operation state.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a radar system, a signal detection method and a signal detection device, which can monitor the frequency of a signal to be detected in real time so as to judge whether the frequency change of the signal to be detected is in a normal state.

According to a first aspect of embodiments of the present invention, there is provided a signal detection apparatus, including: the loop register link is used for updating the value of a corresponding data bit in the indication data according to each signal edge of the signal to be detected, and the frequency of the signal to be detected changes linearly in a detection interval; and the processing circuit is used for obtaining a measured value according to the starting value and the ending value of the indication data in the detection interval and obtaining detection result data according to the offset between the measured value and a preset expected value corresponding to the detection interval, so that the detection result data represents whether the average value of the frequency of the signal to be detected in the detection interval meets an expected range or not.

Optionally, each rising edge and/or each falling edge of the signal to be detected is the signal edge, and for each detection interval, the ring register link is adapted to: circularly updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and updating the value of a respective one of the data bits in the indicating data triggered by each of the signal edges.

Optionally, the ring register link includes a plurality of registers that are sequentially cascaded, each stage of the registers is used to provide different data bits in the indicating data, each stage of the registers is adapted to provide an output signal of the stage of the registers according to the signal to be detected and an input signal of the register, and provide a corresponding data bit in the indicating data according to the signal to be detected and the input signal of the stage of the registers and/or according to the output signal of the register, where, in the plurality of registers that are sequentially cascaded: the first stage register obtains the input signal of the current stage of the first stage register according to the inverted signal of the output signal provided by the last stage register; and each stage of registers except the first stage of registers respectively obtains the input signals of the stage of registers according to the output signals provided by the registers cascaded at the previous stage.

Optionally, each stage of the register updates a corresponding first data bit in the indication data according to a rising edge of the signal to be detected, and updates a corresponding second data bit in the indication data according to a falling edge of the signal to be detected.

Optionally, each stage of the register includes: the cascade sample-hold module chain comprises at least a first-stage sample-hold module and a second-stage sample-hold module, wherein the first-stage sample-hold module samples an input signal of the stage register in a sampling state to generate a transfer signal, and the second-stage sample-hold module samples the transfer signal in the sampling state to generate an output signal of the stage register; and the buffer module provides the first data bit according to the transmission signal and provides the second data bit according to the output signal, wherein the first-stage sample-and-hold module and the second-stage sample-and-hold module alternately enter a sampling state according to the level state of the signal to be detected.

Optionally, the detection result data includes a first bit result value, and the processing circuit includes: a sampling unit, configured to sample the indication data at a start time and an end time of the detection interval to obtain the start value and the end value of the indication data in the detection interval; a storage unit, configured to store a relationship lookup table in advance to indicate sequence numbers respectively corresponding to a plurality of state values of the indication data in an output logic sequence of the ring register link, where the plurality of state values include the start value and the end value, and the sequence numbers include a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and a first judging unit, configured to obtain the measurement value according to a difference between the first sequence number and the second sequence number, and judge whether the offset is greater than a first threshold, if yes, the first judging unit sets the first result value to be in an effective state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not satisfy the expected range, and if not, the first judging unit sets the first result value to be in an ineffective state to indicate that the average value of the frequency of the signal to be detected in the detection interval satisfies the expected range.

Optionally, the preset expected value is: calculating the obtained data value based on the total number of the plurality of state values and the expected occurrence number of signal edges of the signal to be detected in the detection interval.

Optionally, for each detection interval: the measured value is equal to the difference value, the preset expected value is equal to a remainder obtained by dividing twice of a set value corresponding to the detection interval by the total number of the plurality of state values, and the set value is equal to a product of an expected average value of the frequency of the signal to be detected in the detection interval and the duration of the detection interval.

Optionally, the processing circuit further includes: a counter for providing a count value in accordance with the first bit result value, the counter being responsive to the first bit result value in an active state to increment the count value by 1 and responsive to the first bit result value in an inactive state to reset the count value to an initial value; and the comparator is used for judging whether the count value is larger than a second threshold value or not, if so, the comparator sets a second bit result value of the detection result data to be in an effective state to represent that the frequency change of the signal to be detected is in an abnormal state, and if not, the comparator sets the second bit result value to be in an ineffective state to represent that the frequency change of the signal to be detected is in a normal state.

Optionally, the signal to be detected is a frequency modulated continuous wave signal having a frame period, the signal to be detected changes linearly in a linear interval of each frame period and is reset to an initial level in a waiting interval of each frame period, each detection interval is included in the corresponding linear interval, for each detection interval, the processing circuit samples the signal to be detected according to a sampling clock signal to obtain the start value and the end value of the indication data in the detection interval, and the start time and the end time of the detection interval correspond to two adjacent and same-direction clock edges in the sampling clock signal respectively.

Optionally, the signal detection apparatus further includes: the frequency reducing circuit is cascaded in front of the annular register link and is used for reducing the frequency of the signal to be detected according to a set frequency dividing ratio; and/or a shaping circuit, which is cascaded in front of the annular register link and is used for shaping the signal to be detected into a square wave, wherein the annular register link provides the indication data according to the signal to be detected after frequency reduction, or the signal to be detected after shaping, or the signal to be detected after frequency reduction and shaping.

According to a second aspect of embodiments of the present invention, there is provided a radar system including: the phase-locked loop structure comprises a voltage-controlled oscillator, wherein the voltage-controlled oscillator generates a frequency sweeping signal according to frequency control voltage, and the frequency of the frequency sweeping signal changes along with the voltage value of the frequency control voltage; the signal detection device disclosed in any embodiment of the present invention is configured to use the frequency sweep signal or the clock signal as the signal to be detected, where the frequency of the clock signal is in a set proportion to the frequency of the frequency sweep signal; and a radar transceiver providing a transmit signal and/or processing an echo signal according to the frequency sweep signal.

For example, when the calculated offset is smaller than or equal to the first threshold, the signal detection apparatus disclosed in the embodiment of the present invention may determine that the phase-locked loop structure is in a normal operating state, otherwise, the phase-locked loop structure is in an abnormal operating state; in order to improve the judgment accuracy, the signal detection device disclosed in the embodiment of the present invention may respectively perform judgment processing on a plurality of detection intervals, and only when the offset is less than or equal to the first threshold and a certain regular change or a smaller change amplitude is exhibited in all or a preset proportion of the detection intervals, the phase-locked loop structure is judged to be in a normal operating state. Wherein, the judgment of the magnitude of the variation amplitude can be set based on the actual precision requirement.

In addition, for the phase-locked loop structure in the abnormal working state, the signal detection apparatus provided in the embodiment of the present invention may further determine whether the phase-locked loop structure is in the locked state or in the unstable state by further analyzing and judging the change rule of the offset obtained in the different detection intervals (that is, in the embodiment of the present application, the abnormal working state may include the locked state and the unstable state). For example, when the offset obtained in adjacent sampling periods (corresponding to adjacent detection intervals) changes randomly or the change amplitude is large, it may be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it may be considered that some devices in the phase-locked loop structure may be damaged at this time; otherwise, the phase-locked loop structure may be considered to be in a locked state in the abnormal state.

According to a third aspect of the embodiments of the present invention, there is also provided a signal detection method, including: providing a signal to be detected, wherein the frequency of the signal to be detected linearly changes in a detection interval; providing indicating data with a plurality of data bits, and updating corresponding data bits in the indicating data according to the signal edge of the signal to be detected; sampling the indication data at the starting time and the ending time of the detection interval to obtain a starting value and an ending value of the indication data in the detection interval; and for each detection interval, obtaining a measured value according to the starting value and the ending value of the indication data in the detection interval, and obtaining detection result data according to the offset between a preset expected value corresponding to the detection interval and the measured value, wherein the detection result data represents whether the average value of the frequency of the signal to be detected in the detection interval meets an expected range.

Optionally, each rising edge and/or each falling edge of the signal to be detected is the signal edge, and the step of updating the corresponding data bit in the indication data according to the signal edge of the signal to be detected includes: circularly updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and updating the value of a respective one of the data bits in the indicating data triggered by each of the signal edges.

Optionally, for each detection interval, the step of obtaining a measurement value according to the start value and the end value of the indication data in the detection interval, and obtaining detection result data according to an offset between a preset expected value corresponding to the detection interval and the measurement value includes: obtaining a relationship lookup table indicating sequence numbers respectively corresponding to a plurality of state values of the indicating data in an output logical order, the plurality of state values including the start value and the end value, the sequence numbers including a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; obtaining the measurement value according to the difference value between the first sequence number and the second sequence number; and judging whether the offset is larger than a first threshold value, if so, setting a first bit result value of the detection result data to be in an effective state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not meet the expected range, and if not, setting the first bit result value to be in an invalid state to indicate that the average value of the frequency of the signal to be detected in the detection interval meets the expected range.

Optionally, the signal detection method provided in the embodiment of the present invention further includes: and calculating the obtained preset expected value based on the total number of the state values and the expected occurrence number of the signal edge of the signal to be detected in the detection interval.

Optionally, for each detection interval: the measured value is equal to the difference value, the preset expected value is equal to a remainder obtained by dividing twice of a set value corresponding to the detection interval by the total number of the plurality of state values, and the set value is equal to a product of a preset frequency average value of the signal to be detected in the detection interval and the duration of the detection interval.

Optionally, for each detection interval, the step of obtaining a measurement value according to the start value and the end value of the indication data in the detection interval, and obtaining detection result data according to an offset between a preset expected value corresponding to the detection interval and the measurement value further includes: providing a count value according to the first bit result value, adding 1 to the count value when the first bit result value is in an effective state, and restoring the count value to an initial value when the first bit result value is in an ineffective state; and judging whether the count value is larger than a second threshold value, if so, setting a second bit result value of the detection result data to be in an effective state to represent that the frequency change of the signal to be detected is in an abnormal state, and if not, setting the second bit result value to be in an ineffective state to represent that the frequency change of the signal to be detected is in a normal state.

Optionally, the signal to be detected changes linearly in a linear interval of each frame period and is reset to an initial level in a waiting interval of each frame period, each detection interval is included in the corresponding linear interval, and the step of obtaining the start value and the end value of the indication data in the detection interval includes: and sampling the signal to be detected according to a sampling clock signal to obtain the initial value and the end value of the indication data in the detection interval, wherein the initial time and the end time of the detection interval respectively correspond to adjacent and same-direction clock edges in the sampling clock signal.

Optionally, the step of providing the signal to be detected and the indication data includes: carrying out frequency reduction on the signal to be detected according to a set frequency division ratio; and/or shaping the signal to be detected into square waves, wherein the indication data is generated according to the signal to be detected after frequency reduction, or the signal to be detected after shaping, or the signal to be detected after frequency reduction and shaping.

According to the radar system, the signal detection device and the signal detection method provided by the embodiment of the invention, each data bit in the indication data is updated according to the signal edge of the signal to be detected, so that whether the average value of the frequency of the signal to be detected in the detection interval accords with the expected range or not can be judged according to the initial value and the end value of the indication data in the detection interval, and the real-time monitoring of the frequency change of the signal to be detected is realized. In the radar system of the embodiment of the invention, because the frequency of the signal to be detected changes in proportion to the frequency sweeping signal generated by the signal source, the detection result data provided by the signal detection device can indicate whether the signal source works abnormally or not and whether the radar system works abnormally or not.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a radar system of an embodiment of the present invention;

FIG. 2 shows a schematic block diagram of one embodiment of the signal source of FIG. 1;

FIG. 3 is a waveform diagram of a frequency sweep signal and a frequency control voltage according to an embodiment of the present invention;

FIG. 4 shows a schematic block diagram of a signal detection arrangement of an embodiment of the present invention;

fig. 5 shows a schematic block diagram of a signal detection apparatus of a further embodiment of the present invention;

FIG. 6 shows a schematic diagram of a ring register link of an embodiment of the present invention;

FIG. 7 is a circuit diagram of the registers of FIG. 6;

FIG. 8 shows a schematic block diagram of one implementation of the processing circuit of FIG. 4 or 5;

FIG. 9 shows a schematic block diagram of another implementation of the processing circuit of FIG. 4 or 5;

fig. 10 is a flowchart illustrating a signal detection method according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

Overview of the System

Fig. 1 shows a schematic structural diagram of a radar system of an embodiment of the present invention. Fig. 2 shows a schematic structural diagram of an embodiment of the signal source in fig. 1. Fig. 3 shows waveforms of the signal to be detected and the frequency control voltage in the embodiment of the invention.

As shown in fig. 1, a radar system of an embodiment of the present invention includes: the device comprises a transceiving antenna, a receiving channel, a transmitting channel, a signal source, a signal processing module and a signal detection device. The radar transceiver provides a transmitting signal and/or processes an echo signal according to a frequency sweeping signal provided by a signal source.

The following describes each part of the radar system based on the frequency modulated continuous wave system according to the present embodiment with reference to fig. 1 to 3. However, the present embodiment is not limited thereto, and a/some conventional structure/modules not mentioned may also be included in the radar system of the present embodiment.

(1) Transceiver antenna

The transceiving antenna comprises a transmitting antenna 1 and a receiving antenna 2. The transmitting antenna 1 provides a space radiation electromagnetic wave based on the transmitting signal, the electromagnetic wave is reflected on the surface of the target object, the reflected electromagnetic wave is captured by the receiving antenna, so that the receiving antenna 2 obtains an echo signal. Since the transmitting signal in the radar system 100 according to the embodiment of the present invention is a frequency modulated continuous wave with a constantly changing frequency, the radar system 100 in the frequency modulated continuous wave system may obtain information such as a distance and a speed of the target object according to a frequency difference between the transmitting signal and the echo signal, where the speed of the target object may be obtained by calculating distance measurements for multiple times, for example.

(2) Signal source

The signal source 6 is used for generating a frequency-sweep signal SFM with a frequency varying continuously, the frequency of the frequency-sweep signal varies in a trend such as a triangular wave or a sawtooth wave, and the frequency of the frequency-sweep signal varies in a linear trend within the detection area. The frequency sweep signal SFM may be a periodic signal or a non-periodic signal, which is not limited in this application.

As an alternative embodiment, the signal source 6 is, for example, a Phase Locked Loop (PLL) shown in fig. 2, and includes modules such as a Charge Pump (CP) 610, a Loop Filter (LP) 620, a Voltage Controlled Oscillator (VCO) 630, a feedback Frequency divider 640, and a Phase Frequency Detector (PFD) 650.

The phase frequency detector 650, the charge pump 610, the loop filter 620, and the voltage controlled oscillator 630 are sequentially cascaded, and the output end of the voltage controlled oscillator 630 provides an output sweep frequency signal SFM. The feedback frequency divider 640 receives the frequency sweep signal SFM output by the vco 630, divides the frequency of the frequency sweep signal SFM to obtain a down-conversion scanning signal SFM _ div, and provides the down-conversion scanning signal SFM _ div to the phase frequency detector 650, thereby forming a feedback control loop in a phase-locked loop structure.

The feedback frequency Divider 640 is, for example, a Multi-Modulus Divider (MMD), and the Multi-Modulus Divider can divide the frequency of the sweep frequency signal SFM according to a frequency division ratio set by the mode control signal to obtain a down-converted sweep frequency signal SFM _ div, so as to implement a programmable frequency division function. The frequency of the scanning signal SFM may be continuously varied when the frequency division ratio set by the mode control signal is continuously varied.

The phase frequency detector 650 compares the frequency and phase of the reference signal Fref with those of the down-swept signal SFM _ div to generate the first and second state signals Qa and Qb representing the comparison result. As an example, the reference signal Fref may be provided by a crystal oscillator, or may be provided by other circuits or modules, which are not limited in this application.

The charge pump 610 generates the analog voltage signal Vo according to the received first and second state signals Qa and Qb, which are respectively used for up-and down-regulating the voltage value of the analog voltage signal Vo.

The analog voltage signal Vo is filtered by the loop filter 620 to obtain a frequency control voltage Vc, so that the voltage-controlled oscillator 630 generates a frequency sweep signal SFM under the control of the frequency control voltage Vc, and the frequency of the frequency sweep signal SFM corresponds to the voltage value of the frequency control voltage Vc. Under the control of the above phase-locked loop structure, as shown in fig. 3, the voltage value of the frequency control voltage Vc has a linear variation trend within each linear interval Tchrip _ up, for example: the frequency control voltage Vc is linearly increased in an increasing manner from a preset voltage at the starting moment of each linear interval, and the frequency sweep signal provided by the voltage-controlled oscillator 630 under the action of the preset voltage has the minimum frequency FL; at the end of each linear interval, the frequency control voltage Vc reaches the highest voltage, and the frequency sweep signal provided by the voltage controlled oscillator 630 under the action of the highest voltage has the maximum frequency FH; in the waiting interval between every two adjacent linear intervals, the frequency control voltage Vc is reset to a preset voltage. Therefore, the frequency of the frequency sweep signal SFM provided by the voltage controlled oscillator 630 varies linearly with the frequency control voltage Vc within each linear interval.

In some optional embodiments, the time lengths of the linear intervals Tchrip _ up are equal, and the time lengths of the waiting intervals are equal, and the linear intervals and the waiting intervals are alternately distributed in a time domain, so that the frequency control voltage Vc has a frame period and is in a triangular wave or a sawtooth wave in each frame period.

In the embodiment, the signal source 6 is described by taking the phase-locked loop structure as an example, however, the signal source of the embodiment of the present invention is not limited thereto, and the signal source 6 may also be implemented by other circuits capable of generating a frequency sweep signal.

When the radar system works, the phase-locked loop structure including the voltage-controlled oscillator must be ensured to be in a normal working state, so how to detect the working state of the phase-locked loop structure (or a signal source of other structures) is the key for ensuring the normal operation of the radar system. The invention monitors whether the phase-locked loop structure is in a normal working state or not by detecting the frequency sweeping signal or the frequency reducing signal of the frequency sweeping signal, thereby ensuring the normal operation of the radar system.

(3) Receiving channel and transmitting channel

The transmit path 3 and the receive path 4 are coupled to the transmit antenna 1 and the receive antenna 2, respectively. The transmit channel 3 is connected to the signal source 6 for receiving the frequency sweep signal SFM, and the transmit channel 3 provides the transmit signal to the transmit antenna 1 according to the frequency sweep signal SFM and processes the frequency sweep signal SFM to generate the first signal S1. The receiving channel 4 is connected to the receiving antenna 2 to receive the echo signal, and performs filtering and the like on the echo signal, thereby generating a second signal S2.

(4) Frequency mixing unit

The mixing unit 5 is connected to the transmit channel 3 and the receive channel 4 to receive the first signal S1 and the second signal S2 to obtain the beat signal SD from the first signal S1 and the second signal S2. The frequency of the beat signal SD is the difference between the frequency of the first signal S1 and the frequency of the second signal S2, so that the difference between the time when the echo signal is received and the time when the emission signal is emitted can be represented, and the difference is related to the information of the distance, the speed, and the like of the target object. The frequency of the beat signal SD is, for example, proportional to the distance between the target object and the radar.

(5) Signal processing module

The signal processing block 8 receives the beat signal SD supplied from the mixing unit 5, thereby obtaining a detection result Sdata including information of a distance, a speed, and the like of the target with respect to the radar system from the frequency of the beat signal SD.

The signal processing module 8 includes, for example, an analog-to-digital converter for generating a corresponding digital signal from the beat signal SD, and an arithmetic unit for performing calculation processing on the digital signal.

(6) Signal detection device

The radar system of the embodiment of the present invention further includes a signal detection device 7, where the signal detection device 7 detects a signal to be detected STST provided by the signal source 6, and the signal to be detected STST (as shown in fig. 3) may be a frequency sweep signal SFM or a frequency reduction signal of the frequency sweep signal SFM.

As an example, the signal to be detected STST is for example the down-scan signal SFM _ div provided by the feedback frequency divider 640 in the signal source 6.

As another example, as shown in fig. 2, the signal source 6 further includes a frequency divider 660, where the frequency divider 660 is coupled to the output end of the voltage controlled oscillator 630 to receive the frequency sweep signal SFM, and is used to down-convert the frequency sweep signal SFM to obtain the signal to be detected STST, so as to make the frequency of the signal to be detected STST conform to the operating frequency range of the signal detection apparatus 7.

It should be noted that the frequency divider 660 may be disposed in a hardware module for implementing the signal source 6, may be disposed in a hardware module different from components included in the signal source 6, such as the voltage controlled oscillator 630, and may be disposed in the same hardware module as the signal detection device 7, or exist in other forms, which is not limited in this embodiment of the present invention.

The signal detection device 7 is configured to provide the indication data Dstate, and update the indication data Dstate according to each signal edge of the signal to be detected STST (i.e., a level change edge of the signal to be detected STST, which may include each rising edge and/or each falling edge) in a detection interval, so as to determine whether an average value of the frequency of the signal to be detected STST in the detection interval meets an expected range according to a start value and an end value of the indication data Dstate in the detection interval. For example, the signal detection device 7 may update the corresponding data bits in the indicating data Dstate at each rising edge and each falling edge of the signal to be detected STST, or may update the corresponding data bits in the indicating data Dstate only at each rising edge or each falling edge of the signal to be detected STST.

It should be noted that, in the embodiment of the present invention, the linear interval Tchrip _ up shown in fig. 3 may be directly used as the detection interval. However, the embodiments of the present invention are not limited thereto, and in other embodiments, the detection interval may be a part of the linear interval Tchrip _ up.

Fig. 4 shows a schematic block diagram of a signal detection apparatus of an embodiment of the present invention. The signal detection device 7 of the present embodiment will be described in detail below with reference to fig. 4.

As shown in fig. 4, the signal detection device 7 includes a ring register link 7100 and a processing circuit 7200.

The ring register link 7100 is used for providing indication data Dstate with a plurality of data bits, and updating each data bit D1-Dn in the indication data Dstate according to the signal edge of the signal to be detected STST, wherein n is a natural number greater than 1.

For example, when the signal to be detected STST has a rising edge, the logic state of a corresponding one of the data bits Di in the indication data Dstate changes (from 1 to 0 or from 0 to 1, abbreviated as "i-th update"), and then, when the signal to be detected STST has a falling edge, the logic state of another data bit Dj in the indication data Dstate after the i-th update changes (abbreviated as "j-th update"), and so on, it can be known that: in each frame period, the signal to be detected STST has a rising edge and a falling edge, and the indication data Dstate can be updated 2 times, i.e. the indication data Dstate has two corresponding data bits updated. Wherein i and j are respectively non-zero natural numbers less than or equal to n.

In some alternative embodiments, j is equal to i +1 when i is smaller than n, and j is equal to 1 when i is equal to n, so that each data bit D1 to Dn in the indication data Dstate can be cyclically updated according to the signal edge of the signal to be detected STST.

In the above description, the ith update of the indication data Dstate occurs when the rising edge of the to-be-detected signal STST occurs, it should be noted that, in some other equivalent embodiments, the ith update of the indication data Dstate may occur when the falling edge of the to-be-detected signal STST occurs, and correspondingly, the jth update of the indication data Dstate may occur when the rising edge of the to-be-detected signal STST occurs. Further, in the description of the embodiments of the present invention, the update of one data bit in the indication data Dstate means that the logical value of the data bit is updated from 1 to 0 or from 0 to 1.

The various data values that the indicating data Dstate may provide during the course of continuous update are referred to herein as the respective state values of the indicating data Dstate.

The processing circuit 7200 is connected to the output of the ring register link 7100 to receive the indication data Dstate. The processing circuit 7200 is configured to obtain preset expected values of the indication data Dstate corresponding to the detection intervals, and determine whether an average value of the frequency of the signal to be detected STST in the detection interval meets an expected range according to a start value and an end value of the indication data Dstate in each detection interval and the preset expected value corresponding to the detection interval.

As an alternative embodiment, within the linear interval, the processing circuit 7200 may sample the indicating data Dstate triggered by a clock edge (rising edge or falling edge) of the sampling clock signal to obtain a start value and an end value of the indicating data Dstate within each detection interval. In this case, each detection interval corresponds to a respective one of the sampling periods in the sampling clock signal, and the start time and the end time of each detection interval correspond to two adjacent and co-directional clock edges of the sampling clock signal. This embodiment will be described in detail below, however, the embodiment of the present invention is not limited thereto, and each detection interval is not limited to correspond to one sampling period of the sampling clock signal, may correspond to a plurality of consecutive sampling periods, and may be related to other signals for indicating the start time and the end time of the detection interval.

Specifically, in each detection interval, the processing circuit 7200 may sample a start value of the indication data Dstate at a start time of the detection interval, and each data bit D1-Dn in the indication data Dstate is updated cyclically along with the occurrence of a signal edge of the signal to be detected STST; the processing circuit 7200 obtains an end value of the indication data Dstate at the end time of the detection interval, and it is known that the difference between the end value and the start value is related to the number of times the indication data Dstate is updated, that is, the total number of signal edges of the signal to be detected STST occurring in the detection interval. The difference between the start value and the end value of the indicating data Dstate within the detection interval is thus related to the average frequency of the signal to be detected STST within the detection interval. Based on this, the processing circuit 7200 may obtain a measurement value according to a difference between a start value and an end value of the indication data Dstate in each detection interval, and provide the detection result data Sout according to a preset expected value of the measurement value corresponding to the sampling period, so that the detection result data Sout can represent whether an average value of the frequency of the signal to be detected STST in each detection interval meets an expected range.

The "start value" disclosed herein is a data value indicating data Dstate at the start time of the detection interval; the "end value" is a data value indicating data Dstate at the end time of the detection interval. Wherein the start value and the end value are each one of the respective state values of the indicating data Dstate.

In some alternative embodiments, the predetermined expected value may be indicative of an expected number of occurrences of a signal edge of the to-be-detected signal STST within the detection interval, for example, an expected average value of a frequency of the to-be-detected signal STST within the detection interval. Based on this, the processing circuit 7200 may calculate a predicted end value of the indicating data Dstate in the detection interval according to a start value of the indicating data in the detection interval, a preset expected value corresponding to the detection interval, and a duration of the detection interval; subsequently, the processing circuit 7200 may compare the sampled end value with the predicted end value obtained by calculation, and if the two values are consistent within the error tolerance range, it indicates that the average value of the frequency of the signal to be detected STST within the detection interval satisfies the expected range, and if the two values are inconsistent within the error tolerance range, it indicates that the average value of the frequency of the signal to be detected STST within the detection interval does not satisfy the expected range, the signal source 6 (as shown in fig. 1), and the radar system are abnormal in operation.

In other alternative embodiments, the preset expected value may be a value obtained by calculation according to the total number of state values that may be provided by the specific data Dstate and the expected number of occurrences of the signal edge of the signal to be detected STST within the detection interval. Based on this, for each detection interval, the processing circuit 7200 may determine, according to a difference between a start value and an end value of the to-be-detected signal STST within the detection interval and a preset expected value corresponding to the detection interval, whether an average value of the frequency of the to-be-detected signal STST within the detection interval meets an expected range. The following detailed description of the embodiments will be omitted.

In the embodiment shown in fig. 4, the ring register link 7100 has a clock terminal that directly receives the signal to be detected STST, so that the ring register link takes the signal to be detected STST as the clock signal clk. As described above, since the signal to be detected STST is the frequency-swept signal SFM or the frequency-swept signal SFM, it can be known whether the average value of the frequency-swept signal SFM in the detection interval meets the expected frequency range according to the known frequency ratio between the signal to be detected STST and the frequency-swept signal SFM and the detection result data Sout provided by the processing circuit 7200, that is: the detection result data Sout provided by the processing circuit 7200 can also characterize whether the average value of the frequency sweep signal SFM in the detection interval meets the expected range. When the detection result data Sout indicates that the average value of the frequency of the signal to be detected STST in the detection interval meets the expected range, the signal source works normally, the frequency change of the sweep frequency signal SFM is correct, and at the moment, the radar system can work normally; when the detection result data indicate that the average value of the frequency of the signal to be detected STST in the detection interval does not conform to the expected range, the signal source works abnormally, the frequency change of the sweep frequency signal SFM does not conform to the expected range, and at the moment, the radar system works abnormally.

Fig. 5 shows a schematic block diagram of a signal detection apparatus of a further embodiment of the present invention.

In the above description, the ring register link 7100 directly uses the signal to be detected STST as the clock signal clk, however, the embodiment of the present invention is not limited thereto, and the clock terminal of the ring register link 7100 may receive any signal whose frequency is related to the frequency of the sweep signal SFM. For example, in some alternative embodiments, as shown in fig. 5, the signal detection apparatus 7 further includes a driving circuit 7300, which is configured to down-convert and/or shape the signal to be detected STST and use the down-converted and/or shaped signal to be detected STST as the clock signal clk of the ring register link 7100.

As shown in fig. 5, the driving circuit 7300 includes, for example, a shaping circuit, and the shaping circuit is configured to buffer and/or shape a signal to be detected, so that the signal to be detected input to the ring register link 7100 is a square wave signal, and thus the detection accuracy of the ring register link 7100 for the signal to be detected can be improved.

The driving circuit 7300 may further include a frequency-down circuit (for example, implemented by a frequency-dividing circuit structure), and the frequency-down unit may be cascaded before the shaping circuit or cascaded after the shaping circuit, and is configured to reduce the frequency of the signal to be detected according to a set frequency-dividing ratio, so as to further improve the detection accuracy of the ring register link 7100 for the signal to be detected, and reduce the performance requirement on the ring register link 7100.

It should be noted that the frequency divider 660 (shown in fig. 2) and the frequency down-converter circuit in the driving circuit 7300 (shown in fig. 5) both function as described above, so that the frequency of the signal to be detected input to the ring register link 7100 is reduced to the operating frequency range of the ring register link 7100. Therefore, the frequency divider 660 (shown in fig. 2) and the frequency down circuit in the driving circuit 7300 (shown in fig. 5) may exist at the same time or alternatively, and the present application is not limited thereto.

Take millimeter-wave radar applications as an example: the form of the frequency sweep signal SFM in the time domain is a Frequency Modulated Continuous Wave (FMCW), the frequency of which varies in a frequency range of 30GHz to 300GHz, for example, and the operating frequency of each register in the ring register link 7100 is in the order of megahertz, so that the frequency sweep signal SFM needs to be down-converted to obtain a signal to be detected, so that the frequency of the clock signal clk input to the ring register link 7100 falls within the operating frequency range of the ring register link 7100, and the down-conversion process can be implemented by the frequency divider 660 shown in fig. 2 and/or the frequency dividing circuit in the driving circuit 7300 shown in fig. 5; meanwhile, each register in the ring register link 7100 is usually triggered by a square-wave clock signal clk, when the sweep frequency signal SFM is a frequency modulated continuous wave in the form of a sine wave, a signal to be detected input to the ring register link 7100 can be shaped into a square wave and then used as the clock signal clk, and the shaping process can be realized by a shaping circuit in the driving circuit 7300 shown in fig. 5. As mentioned above, the shaping process proposed herein may be performed before the down-conversion process or after the down-conversion process, which is not limited in this application.

In the embodiment shown in fig. 5, the ring register link 7100 and the processing circuit 7200 are the same as or similar to the embodiment shown in fig. 4, and thus are not described again.

The ring register link 7100 and the processing circuit 7200 of the embodiment of the present invention are described in detail below.

Ring register link

Fig. 6 shows a schematic structural diagram of a ring register link according to an embodiment of the present invention. Fig. 7 shows a schematic circuit diagram of each register in fig. 6. The ring register link of the embodiment of the present invention is described in detail below with reference to fig. 6 and 7.

As shown in fig. 6, the ring register link 7100 includes a plurality of registers 7110 cascaded in sequence, with the last level registers cascaded before the first level registers to form the ring link.

Each stage of register 7110 generates the output signal DOUT of the stage and the corresponding data bit in the indicating data Dstate according to the clock signal clk, the inverted clock signal clkb and the input signal DIN of the stage, respectively, and each stage of register 7110 corresponds to different data bits in the indicating data Dstate.

The ring register chain 7100 further comprises an odd number of inverters INV1 cascaded between the first stage register and the last stage register, so that the first stage register can obtain the input signal of the present stage according to the inverted signal of the output signal provided by the last stage register. And each stage of registers except the first stage of registers respectively obtains the input signal of the stage according to the output signal provided by the register cascaded at the previous stage.

The ring register link 7100 also comprises an odd number of inverters INV0 for generating an inverted clock signal clkb from the clock signal clk, such that the inverted clock signal clkb is the inverted signal of the clock signal clk.

In an alternative embodiment, as shown in fig. 6, the number n of data bits of the indicating data Dstate is an even number different from zero, and each stage of the register 7110 corresponds to two adjacent data bits of the indicating data Dstate, for example, the first stage register 7110 is used for outputting the data bit D1 and the data bit D2 in the indicating data Dstate, the second stage register 7110 is used for outputting the data bit D3 and the data bit D4 in the indicating data Dstate, and so on.

As an example, each stage register 7110 may update a corresponding first data bit Dk (output by the DF1 terminal of the stage register) in the indicating data Dstate according to a rising edge of the clock signal clk, and update a corresponding second data bit Dp (output by the DF2 terminal of the stage register) in the indicating data Dstate according to a falling edge of the clock signal clk. Where k and p are respectively non-zero natural numbers of n or less, and p is preferably k + 1.

In other embodiments, each stage of the register 7110 may update the corresponding first data bit Dk in the indicating data Dstate according to the falling edge of the clock signal clk, and update the corresponding second data bit Dp in the indicating data Dstate according to the rising edge of the clock signal clk, which has the same principle as the above embodiments and is not described again.

It should be noted that "updating a certain data bit" as described herein refers to resetting the corresponding data bit according to the current state of each relevant signal, that is, updating the corresponding data bit in the indication data Dstate may or may not change the logic state of the data bit.

As an alternative embodiment, each stage of registers 7110 includes at least two stages of sample and hold modules as shown in fig. 7. The number of sample-and-hold blocks cascaded in each stage of registers 7110 may be the same as the number of bits of the indicating data corresponding to each stage of registers. In this embodiment, 2 data bits are corresponding to each stage of register, and each stage of register includes a first stage sample-and-hold module and a second stage sample-and-hold module.

As shown in fig. 7, the first stage sample-and-hold block 7111 samples the input signal DIN of the present stage register in the sample state to generate the transfer signal DZ, and the second stage sample-and-hold block 7112 samples the transfer signal DZ in the sample state to generate the output signal DOUT of the present stage register.

The first stage sample and hold module 7111 has a sample state and a hold state and alternately enters the sample state and the hold state according to a clock signal clk. In a sampling state, the first stage sample-and-hold module 7111 updates the transfer signal DZ according to the input signal DIN of the present stage register; in the hold state, the first stage sample and hold module 7111 holds the pass signal unchanged.

As an alternative embodiment, the first stage sample and hold module 7111 may include a transmission gate controlled by the clock signal clk. The transmission gate includes, for example, field effect transistors M11 and M12, sources of the field effect transistors M11 and M12 are connected to receive the input signal DIN of the present stage register 7110, and drains of the field effect transistors M11 and M12 are connected to provide the transfer signal DZ; the gates of field effect transistors M11 and M12 receive clock signal clk and inverted clock signal clkb, respectively.

The first stage sample-and-hold block 7111 may further include an even number of inverters (not gates) for buffering the input signal DIN input to the transmission gate and/or buffering the transfer signal DZ output from the transmission gate.

The second stage sample-and-hold block 7112 and the first stage sample-and-hold block 7111 may have the same circuit structure, the second stage sample-and-hold block 7112 may include, for example, a transmission gate formed by field effect transistors M21 and M22, sources of the field effect transistors M21 and M22 may be coupled to receive the transfer signal DZ provided by the first stage sample-and-hold block 7111, drains of the field effect transistors M21 and M22 may be coupled to provide the output signal DOUT of the present stage register, and gates of the field effect transistors M21 and M22 may receive the clock signal clk and the inverted clock signal clkb, respectively. The second stage sample and hold block 7112 may also include an even number of inverters to buffer the pass signal DZ input to the transmission gate and/or to buffer the output signal DOUT provided by the present stage register.

In an alternative embodiment, the transmission gate in the first stage sample-and-hold block 7111 is cascaded between two inverters, and the transmission gate in the second stage sample-and-hold block 7112 is cascaded between two other inverters, so that a simple circuit structure can be used to implement an accurate sample-and-hold function.

In order to make the second stage sample-and-hold module 7112 and the first stage sample-and-hold module 7111 operate in different states at the same time, that is, the first stage sample-and-hold module 7112 and the first stage sample-and-hold module 7111 alternately enter a sampling state and a holding state, the transmission gate in the second stage sample-and-hold module 7112 and the transmission gate in the first stage sample-and-hold module 7111 are alternately turned on under the control of the clock signal clk.

As an alternative embodiment, the gates of the field effect transistors M12 and M21 receive the inverted clock signal clkb, the gates of the field effect transistors M11 and M22 receive the clock signal clk, the field effect transistors M11 and M21 are for example PMOS transistors, and the field effect transistors M12 and M22 are for example NMOS transistors. Therefore, when the clock signal clk is at a low level, the transmission gate in the first stage sample-and-hold module 7111 is turned on, so that the transmission signal DZ is the same as the input signal DIN received by the register of the current stage, and at this time, the first stage sample-and-hold module 7111 operates in a sampling state and the second stage sample-and-hold module 7112 operates in a holding state; when the clock signal clk is at a high level, the transmission gate in the second stage sample-and-hold module 7112 is turned on, so that the output signal DOUT provided by the register of the present stage is the same as the transmission signal DZ provided by the first stage sample-and-hold module 7111, and at this time, the first stage sample-and-hold module 7111 operates in a hold state and the second stage sample-and-hold module 7112 operates in a sampling state.

As shown in fig. 7, each stage of registers 7110 further includes a first stage buffer module 7113 and a second stage buffer module 7114. The first stage buffer module 7113 buffers the transmission signal DZ output by the first stage sample-and-hold module 7111 to drive/shape the first data bit Dk corresponding to the current stage register in the indicating data Dstate, and the second stage buffer module 7114 buffers the output signal DOUT provided by the second stage sample-and-hold module 7112 to drive/shape the second data bit Dp corresponding to the current stage register in the indicating data Dstate. The first-stage buffer module 7113 and the second-stage buffer module 7114 include, for example, an even number of cascaded inverters (not gates), respectively.

In the above embodiments, each stage of the sample-and-hold module and each stage of the buffer module receive the same power supply voltage, for example, the high-level power supply voltage VDD and the low-level voltage VSS.

Processing circuit

Fig. 8 shows a schematic block diagram of one implementation of the processing circuit of fig. 5 or 4.

The processing circuit according to the embodiment of the present invention is described and illustrated below according to the implementation shown in fig. 8, however, the embodiment of the present invention is not limited to this, and other implementation principles of the processing circuit are described above, and those skilled in the art may also use other determination manners to determine whether the average value of the frequency of the signal to be detected in the detection interval is within the desired range.

As shown in fig. 8, the processing circuit 7200 includes a sampling unit 7210, a storage unit 7220, and a first determination unit 7230.

The sampling unit 7210 is configured to sample the indicating data Dstate provided by the ring register link 7100 at a start time of a detection interval to obtain a start value Dstate _ ini of the indicating data within the detection interval, and sample the indicating data Dstate provided by the ring register link 7100 at an end time of the detection interval to obtain an end value Dstate _ end of the indicating data within the detection interval. The sampling unit 7210 receives a sampling clock signal clk _ cs, the frequency of the sampling clock signal clk _ cs is smaller than that of the clock signal clk of the ring register link 7100, and the sampling period Tsample of the sampling clock signal clk _ cs corresponds to a detection interval, so that the sampling unit 7210 can obtain the start value Dstate _ ini and the end value Dstate _ end under the control of the sampling clock signal clk _ cs.

The storage unit 7220 is configured to store in advance various status values Dstate _1 to Dstate _2n of the indication data, and store corresponding sequence numbers of the respective status values of the indication data in the output logic sequence of the ring register link, so as to establish a relationship lookup table between different status values and the sequence numbers, for example, the relationship lookup table shown in table 1 below.

Table 1 prestored relation lookup table between different state values and sequence numbers

In each detection interval, the first determining unit 7230 is configured to obtain a difference Δ a between the sequence number a2 corresponding to the end value Dstate _ end of the indication data in the detection interval and the sequence number a1 corresponding to the start value Dstate _ ini of the indication data in the detection interval according to the relationship lookup table, and obtain the measurement value of the detection interval according to the difference Δ a. Further, the first determining unit 7230 may be configured to determine whether an offset a _ os between the measurement value of the detection interval and the preset expected value a _ ref is greater than a first threshold, if so, set the first bit result value Sout [0] of the detection result data Sout to be in an active state (e.g., 1, or 0 in other embodiments), and if not, set the first bit result value Sout [0] of the detection result data Sout to be in an inactive state (e.g., 0, or 1 in other embodiments), so that the first bit result value Sout [0] may represent whether an average value of the frequency of the signal to be detected in the detection interval satisfies an expected range, for the following reasons:

as described above, the clock signal clk of the ring register link 7100 is the signal to be detected, the down-converted signal of the signal to be detected, the square-wave shaped signal to be detected, or the square-wave shaped and down-converted signal to be detected, and so on, and therefore a set ratio Ndiv is provided between the frequency of the sweep signal provided by the signal source and the frequency of the clock signal clk, and the set ratio is usually a positive real number greater than or equal to 1.

Assuming that the frequency of the sweep frequency signal SFM is fixed at f0 in the detection interval, and the duration of the detection interval is equal to one sampling period Tsample of the sampling clock signal clk _ cs, the frequency of the clock signal clk is f0/Ndiv in the detection interval, and the number of times the indication data Dstate provided by the ring register link 7100 is updated in the detection interval is equal to:

2*Tsample/[1/(f0/N_div)]

however, since the frequency sweep signal SFM is actually linearly increasing in each detection interval, the expected number of times the indication data Dstate output by the loop register link 7100 is updated between each two adjacent sampling points is equal to:

{2*Tsample/[1/(F_y-1/N_div)]+2*Tsample/[1/(F_y/N_div)]}/2

namely:

Tsample*(F_y-1+F_y)/N_div

where y is a natural number greater than or equal to 1, and Fy-1 are respectively the expected frequency of the sweep signal SFM corresponding to the current sampling point (the current clock edge of the sampling clock signal clk _ cs) and the expected frequency of the sweep signal SFM corresponding to the adjacent previous sampling point (the next clock edge of the sampling clock signal clk _ cs). Fy-1 and Fy correspond, for example, to frequencies F1 and F2, respectively, as shown in FIG. 3.

Table 1 illustrates 16 (i.e., 2n) state values for ring register link 7100 as an example of 8-bit indicating data Dstate (i.e., n-8), which in this example may comprise 4 stages of registers, each stage of registers corresponding to a corresponding 2 data bits in the indicating data. The ring register link 7100 cyclically outputs 16 state values indicating data Dstate in output logic order with 16 outputs as one cycle, and the 16 state values are sequentially numbered from 1 to 16 in order according to the output logic order of the ring register link 7100.

As can be seen from the above analysis, two adjacent clock edges in the sampling clock signal may define a detection interval, and a remainder obtained by dividing 16 by the expected number of times that the indication data Dstate is updated in the detection interval may be calculated to obtain a preset expected value a _ ref corresponding to the detection interval, where the preset expected value represents an ideal value of the difference Δ a calculated by the first determining unit 7230.

Based on this, the first determination unit 7230 may determine whether an offset amount a _ os between the difference Δ a (i.e., the measured value) and the preset desired value a _ ref is greater than a first threshold value. If so, it indicates that the deviation between the difference Δ a and the preset expected value a _ ref is too large and exceeds the allowable range determined by the first threshold, at this time, the first determining unit 7230 may set the first result value Sout [0] of the detection result data Sout to an effective state to indicate that the average value of the frequency of the signal to be detected STST in the detection interval does not conform to the expected range, so that the signal source and the radar system are in an abnormal working state according to the first result value Sout [0] of the effective state; if not, it indicates that the deviation between the difference Δ a and the preset expected value a _ ref is within the allowable range determined by the first threshold, at this time, the first determining unit 7230 may set the first result value Sout [0] of the detection result data Sout to an invalid state, so as to indicate that the average value of the frequency of the signal to be detected STST in the detection interval meets the expected range, so that the signal source and the radar system are in the normal operating state according to the first result value Sout [0] of the invalid state.

As an alternative embodiment, the first judgment unit 7230 may include: a search module for searching the corresponding sequence numbers a1 and a2 in the storage unit 7220 according to the start value and the end value provided by the sampling unit 7210; the calculating module is used for calculating a difference value delta a according to the sequence numbers a1 and a2 and calculating the offset between the difference value delta a and a preset expected value a _ ref; a comparison module for comparing the offset with a first threshold to generate a first bit result value Sout [0 ].

Fig. 9 shows a schematic block diagram of yet another implementation of the processing circuit of fig. 6.

As a further optimized embodiment, as shown in fig. 9, the processing circuit 7200 may further include a second determination unit 7240 in addition to the sampling unit 7210, the storage unit 7220, and the first determination unit 7230 described in the above-described embodiment. The second determining unit 7240 is configured to provide a second bit result value Sout [1] in the detection result data Sout, so as to further provide the detection result information of the signal to be detected.

As shown in FIG. 9, the second determining unit 7240 is configured to generate a second bit result value Sout [1] according to the first bit result value Sout [0], and the second determining unit 7240 includes a counter 7241 and a comparator 7242.

The counter 7241 is configured to provide a count value num according to the first bit result value Sout [0 ]. When the first bit result Sout [0] is in the valid state, the counter 7241 increments the count value num by 1; when the first bit result Sout [0] received by the counter 7241 is in an invalid state, the counter 7241 resets the count value num to the initial value. Therefore, the count value num can represent the number of sampling cycles of the first result value Sout [0] that continuously represents the abnormal operating state, i.e. the number of sampling cycles for which the frequency of the frequency sweep signal SFM does not continuously meet the preset frequency.

The comparator 7242 is configured to compare the count num provided by the counter 7241 with a second threshold max _ ref to obtain a second bit result Sout [1 ]. When the count value num is greater than the second threshold value max _ ref, the comparator 7242 may output a second bit result value Sout [1] in an effective state to indicate that the average value of the frequency of the signal to be detected STST in a plurality of consecutive detection intervals/sampling periods exceeding the expected number does not satisfy the expected range, which indicates that the signal source and the radar system are in an abnormal working state for a long time and are not easy to restore to normal by themselves; when the count num is less than or equal to the second threshold max _ ref, the comparator 7242 outputs a second bit result Sout [1] in an invalid state to indicate that the frequency variation of the signal to be detected and the frequency variation of the frequency sweep signal are expected.

In alternative embodiments, the subsequent stage circuit connected to the comparator 7242 may be triggered by the second bit result value Sout [1] of the valid state to initiate an early warning prompt, which includes but is not limited to an audio prompt, a pop-up prompt, an optical prompt, and the like. When the second bit result value Sout [1] is in an invalid state, the post-stage circuit does not need to initiate early warning prompt.

The present invention further provides a signal detection apparatus according to the above embodiments, configured to determine whether an average value of the frequency of the signal to be detected in each detection interval meets an expected range.

According to the radar system and the signal detection device provided by the embodiment of the invention, each data bit of the indication data is updated according to the signal edge of the signal to be detected, so that whether the average value of the frequency of the signal to be detected in each detection interval meets the expected range or not can be judged according to the initial value and the end value of the indication data in the detection interval, and the frequency of the signal to be detected is monitored in real time. In the radar system of the embodiment of the invention, because the frequency of the signal to be detected changes in proportion to the frequency sweeping signal generated by the signal source, the detection result data provided by the signal detection device can be used for indicating whether the signal source and the radar system are in a normal working state.

In some optional embodiments, the signal detection device may sample the indication data by using a sampling clock signal, so as to obtain a start value of the indication data at a start time of the detection interval, obtain an end value of the indication data at an end time of the detection interval, and obtain corresponding measurement values according to the start value and the end value, so that whether an average value of the frequency of the signal to be detected in the detection interval meets an expected range can be determined according to an offset between the measurement value corresponding to each detection interval and a preset expected value, so as to implement real-time monitoring of the frequency of the signal to be detected.

For example, for a signal source including a phase-locked loop structure, when the calculated offset is smaller than or equal to a first threshold, it may be determined that the phase-locked loop structure is in a normal operating state, otherwise, it is in an abnormal operating state; in order to improve the accuracy of the judgment, the signal detection device and the radar heartache of the embodiment of the invention can respectively perform judgment processing on a plurality of detection intervals, and only when the offset is smaller than or equal to the first threshold value and shows a certain regular change or a smaller change amplitude in all or a preset proportion of the detection intervals, the phase-locked loop structure is judged to be in a normal working state. Wherein, the judgment of the magnitude of the variation amplitude can be set based on the actual precision requirement.

In addition, for the phase-locked loop structure in the abnormal working state, the signal detection apparatus and the radar system disclosed in the embodiment of the present invention may further determine whether the phase-locked loop structure is in the locked state or the unstable state by further analyzing and judging the change rule of the offset obtained in the different detection intervals (that is, in the embodiment of the present application, the abnormal working state may include the locked state and the unstable state). For example, when the offset obtained in adjacent sampling periods (for example, corresponding to adjacent detection intervals) changes randomly or the change amplitude is large, it may be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, it may be considered that some devices in the phase-locked loop structure may be damaged at this time; otherwise, the phase-locked loop structure may be considered to be in a locked state in the abnormal state.

Fig. 10 is a flowchart illustrating a signal detection method according to an embodiment of the present invention. Including steps S810 through S850. The method is applied to the signal detection device and the radar system of each of the above embodiments, for example.

In step S810, a signal to be detected is provided according to the frequency sweep signal, such that the frequency of the signal to be detected and the frequency of the frequency sweep signal are in a set proportion. The frequency of the sweep frequency signal changes linearly in the detection interval, so that the frequency of the signal to be detected also changes linearly in the detection interval.

In step S820, indication data having a plurality of data bits is provided, and corresponding data bits in the indication data are updated according to signal edges of the signal to be detected.

As an alternative embodiment, each rising edge and/or each falling edge of the signal to be detected may be used as a signal edge for updating the indication data. Step S820 may include: circularly updating the value of each data bit of the indicating data under the triggering of each signal edge in turn; and updating a value indicative of a respective one of the data bits upon triggering of each signal edge.

In step S830, the indication data is sampled at the start time and the end time of the detection interval to obtain a start value and an end value of the indication data within the detection interval, and a measurement value corresponding to the detection interval is obtained according to the start value and the end value.

In step S840, for each detection interval, a corresponding preset expected value is calculated, and an offset between a measured value corresponding to the detection interval and the preset expected value is obtained.

In step S850, detection result data is obtained according to the offset to represent whether the average value of the frequencies of the signal to be detected and the frequency sweep signal in the detection interval meets the expected range.

It should be noted that the signal detection method provided in the embodiments of the present invention may include the technical details and features provided in the foregoing description of the signal detection device and the radar system of each embodiment, and the same parts are not described herein again.

According to the signal detection method provided by the embodiment of the invention, each data bit in the indication data is updated according to the signal edge of the signal to be detected, so that whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range or not can be judged according to the initial value and the end value of the indication data in the detection interval, and the frequency of the signal to be detected is monitored in real time. Because the frequency of the signal to be detected changes in proportion to the frequency sweeping signal, the detection result data generated by the signal detection method of the embodiment of the invention can be used for indicating whether the signal source and the radar system are in a normal working state.

In some optional embodiments, the signal detection method may sample the indication data by using a sampling clock signal, so as to obtain a start value of the indication data at a start time of the detection interval, obtain an end value of the indication data at an end time of the detection interval, and obtain corresponding measurement values according to the start value and the end value, so that whether an average value of the frequency of the signal to be detected in the detection interval conforms to an expected range may be determined according to an offset between the measurement value corresponding to each detection interval and a preset expected value, so as to implement real-time monitoring of the frequency of the signal to be detected.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (20)

1. A signal detection device, comprising:

the loop register link is used for updating the value of a corresponding data bit in the indication data according to each signal edge of the signal to be detected, and the frequency of the signal to be detected changes linearly in a detection interval; and

and the processing circuit is used for obtaining a measured value according to the starting value and the ending value of the indication data in the detection interval and obtaining detection result data according to the offset between the measured value and a preset expected value corresponding to the detection interval, so that the detection result data represents whether the average value of the frequency of the signal to be detected in the detection interval meets an expected range or not.

2. The signal detection apparatus according to claim 1, wherein each rising edge and/or each falling edge of the signal to be detected is the signal edge,

for each of the detection intervals, the ring register link is adapted to:

circularly updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and

updating the value of a respective one of the data bits in the indicating data triggered by each of the signal edges.

3. The signal detection device according to claim 1, wherein the ring-shaped register chain comprises a plurality of registers cascaded in sequence, each register is used for providing different data bits in the indication data, each register is adapted to provide an output signal of the register according to the signal to be detected and an input signal of the register, and provide a corresponding data bit in the indication data according to the signal to be detected and the input signal of the register and/or the output signal of the register,

wherein, in the plurality of registers cascaded in sequence:

the first stage register obtains the input signal of the current stage of the first stage register according to the inverted signal of the output signal provided by the last stage register; and

and each stage of registers except the first stage of registers respectively obtains the input signals of the registers of the stage according to the output signals provided by the registers of the previous stage in cascade connection.

4. The signal detection device of claim 3, wherein each stage of the register updates a corresponding first data bit in the indication data according to a rising edge of the signal to be detected and updates a corresponding second data bit in the indication data according to a falling edge of the signal to be detected.

5. The signal detection device according to claim 4, wherein each stage of the register includes:

the cascade sample-hold module chain comprises at least a first-stage sample-hold module and a second-stage sample-hold module, wherein the first-stage sample-hold module samples an input signal of the stage register in a sampling state to generate a transfer signal, and the second-stage sample-hold module samples the transfer signal in the sampling state to generate an output signal of the stage register; and

a buffer module to provide the first data bit according to the transfer signal and to provide the second data bit according to the output signal,

and the first-stage sampling and holding module and the second-stage sampling and holding module alternately enter a sampling state according to the level state of the signal to be detected.

6. The signal detection device of claim 1, wherein the detection result data comprises a first bit result value, and the processing circuit comprises:

a sampling unit, configured to sample the indication data at a start time and an end time of the detection interval to obtain the start value and the end value of the indication data in the detection interval;

a storage unit, configured to store a relationship lookup table in advance to indicate sequence numbers respectively corresponding to a plurality of state values of the indication data in an output logic sequence of the ring register link, where the plurality of state values include the start value and the end value, and the sequence numbers include a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and

a first judgment unit configured to obtain the measurement value according to a difference between the first sequence number and the second sequence number, and judge whether the offset is greater than a first threshold,

if so, the first judgment unit sets the first bit result value to be in a valid state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not meet the expected range,

if not, the first judgment unit sets the first bit result value to be in an invalid state so as to indicate that the average value of the frequency of the signal to be detected in the detection interval meets the expected range.

7. The signal detection device of claim 6, wherein the preset desired value is: calculating the obtained data value based on the total number of the plurality of state values and the expected occurrence number of signal edges of the signal to be detected in the detection interval.

8. The signal detection apparatus according to claim 7, wherein for each of the detection intervals:

the measured value is equal to the difference value,

the preset expected value is equal to a remainder obtained by dividing twice of a set value corresponding to the detection interval by the total number of the plurality of state values,

the set value is equal to the product of the expected average value of the frequency of the signal to be detected in the detection interval and the duration of the detection interval.

9. The signal detection device of claim 6, wherein the processing circuit further comprises:

a counter for providing a count value in accordance with the first bit result value, the counter being responsive to the first bit result value in an active state to increment the count value by 1 and responsive to the first bit result value in an inactive state to reset the count value to an initial value; and

a comparator for determining whether the count value is greater than a second threshold value,

if so, the comparator sets the second bit result value of the detection result data to be in an effective state to represent that the frequency change of the signal to be detected is in an abnormal state,

if not, the comparator sets the second bit result value to be in an invalid state so as to represent that the frequency change of the signal to be detected is in a normal state.

10. The signal detection apparatus according to claim 1,

the signal to be detected is a frequency modulated continuous wave signal having a frame period, the signal to be detected varies linearly within a linear interval of each frame period and is reset to an initial level within a waiting interval of each frame period, each of the detection intervals is included in the corresponding linear interval,

for each detection interval, the processing circuit samples the signal to be detected according to a sampling clock signal to obtain the start value and the end value of the indication data in the detection interval, and the start time and the end time of the detection interval respectively correspond to two adjacent clock edges in the same direction in the sampling clock signal.

11. The signal detection device according to claim 1, further comprising:

the frequency reducing circuit is cascaded in front of the annular register link and is used for reducing the frequency of the signal to be detected according to a set frequency dividing ratio; and/or

A shaping circuit cascaded in front of the annular register link and used for shaping the signal to be detected into square waves,

and the annular register link provides the indication data according to the signal to be detected after frequency reduction, or the signal to be detected after shaping, or the signal to be detected after frequency reduction and shaping.

12. A method of signal detection, comprising:

providing a signal to be detected, wherein the frequency of the signal to be detected linearly changes in a detection interval;

providing indicating data with a plurality of data bits, and updating corresponding data bits in the indicating data according to the signal edge of the signal to be detected;

sampling the indication data at the starting time and the ending time of the detection interval to obtain a starting value and an ending value of the indication data in the detection interval; and

for each detection interval, obtaining a measurement value according to the starting value and the ending value of the indication data in the detection interval, and obtaining detection result data according to the offset between a preset expected value corresponding to the detection interval and the measurement value,

and the detection result data represents whether the average value of the frequency of the signal to be detected in the detection interval meets an expected range.

13. The signal detection method according to claim 12, wherein each rising edge and/or each falling edge of the signal to be detected is the signal edge, and the step of updating the corresponding data bit in the indication data according to the signal edge of the signal to be detected comprises:

circularly updating the value of each data bit of the indication data in sequence under the triggering of each signal edge; and

updating the value of a respective one of the data bits in the indicating data triggered by each of the signal edges.

14. The signal detection method of claim 12, wherein for each detection interval, obtaining a measurement value according to the start value and the end value of the indication data in the detection interval, and obtaining detection result data according to an offset between a preset expected value and the measurement value corresponding to the detection interval comprises:

obtaining a relationship lookup table indicating sequence numbers respectively corresponding to a plurality of state values of the indicating data in an output logical order, the plurality of state values including the start value and the end value, the sequence numbers including a first sequence number corresponding to the start value and a second sequence number corresponding to the end value;

obtaining the measurement value according to the difference value between the first sequence number and the second sequence number;

determining whether the offset is greater than a first threshold,

if so, setting a first bit result value of the detection result data as a valid state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not meet the expected range,

if not, setting the first bit result value as an invalid state to indicate that the average value of the frequency of the signal to be detected in the detection interval meets the expected range.

15. The signal detection method according to claim 14, further comprising:

and calculating the obtained preset expected value based on the total number of the state values and the expected occurrence number of the signal edge of the signal to be detected in the detection interval.

16. The signal detection method of claim 15, wherein for each of the detection intervals:

the measured value is equal to the difference value,

the preset expected value is equal to a remainder obtained by dividing twice of a set value corresponding to the detection interval by the total number of the plurality of state values,

the set value is equal to the product of the preset frequency average value of the signal to be detected in the detection interval and the duration of the detection interval.

17. The signal detection method of claim 15, wherein for each detection interval, obtaining a measurement value according to the start value and the end value of the indication data in the detection interval, and obtaining detection result data according to an offset between a preset expected value and the measurement value corresponding to the detection interval further comprises:

providing a count value according to the first bit result value, adding 1 to the count value when the first bit result value is in an effective state, and restoring the count value to an initial value when the first bit result value is in an ineffective state; and

determining whether the count value is greater than a second threshold value,

if so, setting a second bit result value of the detection result data as a valid state to represent that the frequency change of the signal to be detected is in an abnormal state,

and if not, setting the second bit result value as an invalid state to represent that the frequency change of the signal to be detected is in a normal state.

18. The signal detection method according to claim 12, wherein the signal to be detected changes linearly in a linear interval of each of the frame periods and is reset to an initial level in a waiting interval of each of the frame periods, each of the detection intervals is included in the corresponding linear interval, and the step of obtaining the start value and the end value of the indication data in the detection interval comprises:

and sampling the signal to be detected according to a sampling clock signal to obtain the initial value and the end value of the indication data in the detection interval, wherein the initial time and the end time of the detection interval respectively correspond to adjacent and same-direction clock edges in the sampling clock signal.

19. The signal detection method of claim 12, wherein the step of providing the signal to be detected and the indication data comprises:

carrying out frequency reduction on the signal to be detected according to a set frequency division ratio; and/or

Shaping the signal to be detected into a square wave,

the indication data is generated according to the signal to be detected after frequency reduction, or the signal to be detected after shaping, or the signal to be detected after frequency reduction and shaping.

20. A radar system, comprising:

the phase-locked loop structure comprises a voltage-controlled oscillator, wherein the voltage-controlled oscillator generates a frequency sweeping signal according to frequency control voltage, and the frequency of the frequency sweeping signal changes along with the voltage value of the frequency control voltage;

the signal detection device according to any one of claims 1 to 11, configured to use the frequency sweep signal or a clock signal as the signal to be detected, wherein the frequency of the clock signal is proportional to the frequency of the frequency sweep signal; and

and the radar transceiver provides a transmitting signal and/or processes an echo signal according to the frequency sweep signal.

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