CN111009521A - Multi-chip packaging module - Google Patents

Multi-chip packaging module Download PDF

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Publication number
CN111009521A
CN111009521A CN201911406314.0A CN201911406314A CN111009521A CN 111009521 A CN111009521 A CN 111009521A CN 201911406314 A CN201911406314 A CN 201911406314A CN 111009521 A CN111009521 A CN 111009521A
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CN
China
Prior art keywords
chips
chip
sub
substrate
package module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911406314.0A
Other languages
Chinese (zh)
Inventor
卢耀普
卢振华
陈斌
黄治国
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yuehu Crystal Core Circuit (suzhou) Co Ltd
Original Assignee
Yuehu Crystal Core Circuit (suzhou) Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yuehu Crystal Core Circuit (suzhou) Co Ltd filed Critical Yuehu Crystal Core Circuit (suzhou) Co Ltd
Priority to CN201911406314.0A priority Critical patent/CN111009521A/en
Publication of CN111009521A publication Critical patent/CN111009521A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a multi-chip packaging module, comprising: the chip-packaging structure comprises a main substrate, a plurality of sub-substrates and a plurality of chips, wherein the plurality of sub-substrates are sequentially arranged on the main substrate in the same direction, each sub-substrate comprises an inclined surface, one chip is arranged on each inclined surface, the chips are electrically connected with one another, and the chips are electrically connected with the main substrate. According to the invention, the plurality of chips are obliquely arranged on the sub-substrate, so that the area and the distance between the chips can be greatly reduced, a certain distance can be kept between the chips, and the heat dissipation performance of the chips is ensured.

Description

Multi-chip packaging module
Technical Field
The invention relates to a chip packaging technology, in particular to a multi-chip packaging module.
Background
The miniaturization of the chip is approaching the limit, moore's law is no longer applicable to the development trend of the chip, and the chip used by the current electronic product is basically packaged by a single chip. It is likely that a chip module that packages a plurality of chips with different functions together to realize a stronger function will be a development trend in the future. The method not only can reduce the volume, but also can reduce the distance between different ICs, and improves the calculation speed of the chip.
The chip module industry that forms a plurality of different chips of function encapsulation together has studied, and present research direction has: and the packaging mode is that a plurality of chips are horizontally spread and packaged together and are 3D stacked and packaged in the vertical direction. The packaging material and the packaging process are reasonably selected according to different chips and product design requirements. The chip spacing can be reduced to a large extent by horizontally spreading and packaging a plurality of chips together, but when the number of chips is large, the tiled area is large. It is also feasible to stack and package a plurality of chips in the vertical direction in 3D, but the heat dissipation is seriously affected by the stacking, and the number of stacked layers is not suitable, otherwise the packaged chips would be highly affected by the mounting and difficult to dissipate heat.
Disclosure of Invention
The invention aims to provide a multi-chip packaging module which is small in size and good in heat dissipation.
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
According to an aspect of the present invention, there is provided a multi-chip package module including: the chip-packaging structure comprises a main substrate, a plurality of sub-substrates and a plurality of chips, wherein the plurality of sub-substrates are sequentially arranged on the main substrate in the same direction, each sub-substrate comprises an inclined surface, one chip is arranged on each inclined surface, the chips are electrically connected with one another, and the chips are electrically connected with the main substrate.
In one embodiment, the sub-substrate and the main substrate of the multi-chip package module are connected by an adhesive member.
In one embodiment, the inclined surface of the sub-substrate of the multi-chip package module forms an angle of 30-60 degrees with the main substrate.
In one embodiment, each of the sub-substrates of the multi-chip package module includes an inclined portion and a connection portion, the chip is disposed on an upper surface of the inclined portion, and the connection portion is adhered to the main substrate.
In one embodiment, a groove is formed at the front end of the connecting portion of the multi-chip package module, a protrusion is formed at the rear end of the connecting portion, and the protrusion of the rear sub-substrate is inserted into the groove of the front sub-substrate.
In one embodiment, a heat spreader is disposed on each of the chips of the multi-chip package module.
In one embodiment, the other surface of the main substrate of the multi-chip package module is provided with a ball pad, and the ball pad is connected with a connecting terminal.
In one embodiment, the chip of the multi-chip package module is provided with a bonding pad, the main substrate is provided with a connection pad, and the bonding pad is electrically connected with the connection pad.
In one embodiment, the chips of the multi-chip package module have different functions.
In one embodiment, at least one of the chips of the multi-chip package module is a control chip, and the rest of the chips are memory chips.
The embodiment of the invention has the beneficial effects that: the plurality of chips are obliquely arranged on the sub-substrate, so that the area and the distance between the chips can be reduced to a large extent, a certain distance can be kept between the chips, and the heat dissipation performance of the chips is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
The above features and advantages of the present disclosure will be better understood upon reading the detailed description of embodiments of the disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components having similar relative characteristics or features may have the same or similar reference numerals.
FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of another embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of yet another embodiment of the present invention;
FIG. 4 is a schematic perspective view of the submount of the present invention;
fig. 5 is a schematic perspective view of an embodiment of the present invention.
Wherein: 100-chip; 101-a submount; 101 a-inclined plane; 102-a connection terminal; 103-connection pads; 104-bond pads; 105-ball pads; 106-an adhesive member; 107-main substrate; 201-solder balls; 202-solder balls; 301-a heat sink; 401-an inclined portion; 402-a connecting portion; 402 a-bumps; 402 b-groove.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. It is noted that the aspects described below in connection with the figures and the specific embodiments are only exemplary and should not be construed as imposing any limitation on the scope of the present invention.
As shown in fig. 1, the present invention discloses a multi-chip package module, comprising: the chip packaging structure comprises a main substrate 107, a plurality of sub-substrates 101 and a plurality of chips 100, wherein the plurality of sub-substrates 101 are sequentially arranged on the main substrate 107 in the same direction, each sub-substrate 101 comprises an inclined surface 101a, each inclined surface 101a is provided with one chip 100, the chips 100 are electrically connected, and the chips 100 are electrically connected with the main substrate 107. Different from the vertical stacking mode and the horizontal spreading mode in the prior art, the chip packaging module has the advantages that the plurality of chips are obliquely arranged on the sub-substrate, so that the whole area of the chip packaging module can be greatly reduced, a certain distance can be kept between the chips, and the heat dissipation performance of the chips is ensured.
Preferably, the sub-substrate 101 and the main substrate 107 are connected by an adhesive member 106. Each of the sub-substrates 101 includes an inclined portion 401 and a connection portion 402, the chip 100 is disposed on an upper surface of the inclined portion 401, and the connection portion 402 is bonded to the main substrate 107. The angle between the inclined portion 401 and the main substrate 107 is 30 to 60 degrees. The tilt angle can be determined according to the thickness requirement and the area requirement of the packaging module. If the thickness requirement of the package module is high, the inclined portion 402 may be set to be flat. In this embodiment, in order to balance the heat dissipation effect and the horizontal area, the included angle is set to 45 degrees.
In order to further reduce the distance between the sub-substrates 101, a groove 402b may be provided at the front end of the connection part 402, a protrusion 402a may be provided at the rear end of the connection part 402, and the protrusion 402a of the sub-substrate 101 disposed behind may be inserted into the groove 402b of the sub-substrate disposed in front. Such a structure can reduce the distance between the sub-substrates 101 while maintaining the supporting area of the connection part 402, thereby reducing the entire area of the chip packaging module. For supporting the chip, the sub-substrate 101 cannot be made of flexible material, and should preferably be made of silicon material.
The electrical connection between the chip 100 and the main substrate 107 can be achieved in various ways, for example, as shown in fig. 1, the bonding pads 104 on the chip and the connection pads 103 on the main substrate are electrically connected through wires, or as shown in fig. 2, the chip 100 and the connection pads on the sub-substrate 101 are connected through solder balls 201 or bumps, and then the sub-substrate 101 and the connection pads of the main substrate 107 are connected, and the connection pads on the sub-substrate 101 can be connected through circuit traces arranged in the sub-substrate. Similarly, the connection between the submount 101 and the main substrate 107 may be formed by connecting the respective connection pads with the solder balls 202, and then wrapping the adhesive member 106 around the solder balls 202. The structure has higher wiring density and shorter transmission distance.
Further, as shown in fig. 3, a heat sink 301 (or heat sink) is provided on the upper surface of each chip 100 to further improve the heat dissipation performance of the chip 100.
Further, a ball pad 105 is provided on the other surface of the main substrate 107, and the connection terminal 102 is connected to the ball pad 105.
The multiple chips have different functions. For example, one of the chips may be a control chip and the remaining chips may be memory chips. A plurality of independent chips with different functions are packaged together, so that the product requirement can be met, the distance between different ICs can be shortened, and the calculation speed of the chips is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The above description is only a preferred example of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present application should be included in the scope of the present application.

Claims (10)

1. A multi-chip package module, comprising: the chip-packaging structure comprises a main substrate, a plurality of sub-substrates and a plurality of chips, wherein the plurality of sub-substrates are sequentially arranged on the main substrate in the same direction, each sub-substrate comprises an inclined surface, one chip is arranged on each inclined surface, the chips are electrically connected with one another, and the chips are electrically connected with the main substrate.
2. The multi-chip package module of claim 1, wherein the submount and the host substrate are coupled by an adhesive member.
3. The multi-chip package module of claim 2, wherein: the included angle between the inclined surface of the sub-substrate and the main substrate is 30-60 degrees.
4. The multi-chip package module of claim 3, wherein: each of the sub-substrates includes an inclined portion and a connection portion, the chip is disposed on an upper surface of the inclined portion, and the connection portion is bonded to the main substrate.
5. The multi-chip package module of claim 4, wherein: the front end of the connecting part is provided with a groove, the rear end of the connecting part is provided with a bulge, and the bulge of the sub-substrate arranged behind is inserted into the groove of the sub-substrate arranged in front.
6. The multi-chip package module of claim 4, wherein: each chip is provided with a radiator.
7. The multi-chip package module of claim 1, wherein: and a ball bonding pad is arranged on the other surface of the main substrate, and a connecting terminal is connected to the ball bonding pad.
8. The multi-chip package module of claim 1, wherein: the chip is provided with a bonding pad, the main substrate is provided with a connecting pad, and the bonding pad is electrically connected with the connecting pad.
9. The multi-chip package module of claim 1, wherein the plurality of chips have different functions.
10. The multi-chip package module of claim 9, wherein at least one of the plurality of chips is a control chip and the remaining chips are memory chips.
CN201911406314.0A 2019-12-31 2019-12-31 Multi-chip packaging module Pending CN111009521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911406314.0A CN111009521A (en) 2019-12-31 2019-12-31 Multi-chip packaging module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911406314.0A CN111009521A (en) 2019-12-31 2019-12-31 Multi-chip packaging module

Publications (1)

Publication Number Publication Date
CN111009521A true CN111009521A (en) 2020-04-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911406314.0A Pending CN111009521A (en) 2019-12-31 2019-12-31 Multi-chip packaging module

Country Status (1)

Country Link
CN (1) CN111009521A (en)

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