CN111008167A - Distributed computer bus back plate - Google Patents
Distributed computer bus back plate Download PDFInfo
- Publication number
- CN111008167A CN111008167A CN201911189280.4A CN201911189280A CN111008167A CN 111008167 A CN111008167 A CN 111008167A CN 201911189280 A CN201911189280 A CN 201911189280A CN 111008167 A CN111008167 A CN 111008167A
- Authority
- CN
- China
- Prior art keywords
- interface
- board card
- bus interface
- synchronization
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Human Computer Interaction (AREA)
- Multi Processors (AREA)
Abstract
The invention discloses a distributed computer bus back plate, which comprises a switching board card, a functional board card and a back plate; the switching board card comprises an Ethernet switching interface, an SRIO switching interface, a USB bus interface, an asynchronous serial bus interface, a CAN bus interface, a management processor, a clock synchronization circuit and a connector; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface and the CAN bus interface are respectively connected with a functional board card with the same interface, and the clock synchronization circuit is respectively connected with the connected functional board card; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface, the CAN bus interface, the clock synchronization circuit and the connector are respectively connected with the management processor and the connector. The invention can flexibly expand and cut different numbers of functional modules according to the requirements, meet different functional and performance requirements, save functional board card bridge pieces, improve the board card size utilization rate and further reduce the cost.
Description
Technical Field
The invention belongs to the technical field of reinforced computer design, and particularly relates to a distributed computer bus back plate.
Background
In the current ruggedized computer architecture, the CPCI/CPCI-e, PXI/PXIe and VPX buses are taken as mainstream, and the architecture takes a system controller/card as a center, and corresponding functional modules are expanded to form a centralized computer bus backplane architecture. Overall performance of such architecture computers is mainly dependent on the system controller/card, which needs to be updated to meet further needs when computing power and performance are not satisfied, and may cause performance excess when the need is low, resulting in wasted investment. Moreover, the function board must exchange data with the system controller/card through the expensive bridge, which also causes the size and cost of the function board to increase greatly. Therefore, it is very important to construct a distributed computer backplane bus architecture that can be flexibly expanded and cut and has low cost.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a computer bus backboard which can flexibly expand and cut different numbers of functional modules according to requirements and meet different functional and performance requirements. The backboard can save the bridge piece of the functional board card and improve the size utilization rate of the board card, thereby achieving the effect of reducing the cost.
The purpose of the invention is realized by the following technical scheme: a distributed computer bus backboard comprises a switching board card, a function board card and a backboard, wherein the switching board card and the function board card are arranged on the backboard;
the switching board card provides Ethernet, SRIO, USB bus, asynchronous serial bus and CAN bus switching management and control, and comprises an Ethernet switching interface, an SRIO switching interface, a USB bus interface, an asynchronous serial bus interface, a CAN bus interface, a management processor, a clock synchronization circuit and a connector; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface and the CAN bus interface are respectively connected with a function board card with the same interface, the clock synchronization circuit is respectively connected with the connected function board card, and the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface, the CAN bus interface, the clock synchronization circuit and the connector are respectively connected with the management processor and the connector.
Furthermore, the clock synchronization circuit comprises hardware synchronization and software synchronization, the hardware synchronization comprises a 100MHz synchronization pulse, so that all the functional board cards realize data acquisition and processing synchronization through hardware synchronization signals and software synchronization of the backboard, and the rising edge T of the synchronization pulse signal is less than or equal to 1 ns; software synchronization adopts heartbeat packets for synchronization, and synchronization is carried out by a synchronous scheduling function board card communication protocol specified by a user.
Further, the backplane comprises a single switch backplane, a distributed dual switch backplane, or a distributed ring switch backplane.
The invention has the beneficial effects that: the invention can flexibly expand and cut different numbers of functional modules according to the requirements, meet different functional and performance requirements, save functional board card bridge pieces, improve the board card size utilization rate and further reduce the cost; the invention can improve the data exchange reliability by 50-100%, meet the requirements of high-reliability computers, and meet the requirements of functions and performances of ruggedized computers in the fields of measurement, industrial control and military industry.
Drawings
FIG. 1 is a single switching topology of a distributed computer bus backplane architecture of the present invention;
FIG. 2 is a diagram of a distributed computer bus backplane architecture dual-switch topology of the present invention;
FIG. 3 is a ring switching topology of a distributed computer bus backplane architecture of the present invention;
FIG. 4 is a schematic diagram of a switch board card according to the present invention;
FIG. 5 is a diagram of a distributed computer architecture of the present invention.
Detailed Description
The technical scheme of the invention is further explained by combining the drawings and the specific embodiment.
Example one
As shown in fig. 1, 4 and 5, the distributed computer bus backplane of the present embodiment includes a switch board, a function board and a backplane, where the switch board and the function board are both disposed on the backplane; the backplane of the embodiment adopts a single-switch backplane, single-path network link is realized through a single-switch network, and the distributed single-switch backplane is used as a data exchange path carrier of the switch board card and the function board card and forms a complete single-switch distributed computer architecture with the function board card.
The switching board card provides Ethernet, SRIO, USB bus, asynchronous serial bus and CAN bus switching management and control, and comprises an Ethernet switching interface, an SRIO switching interface, a USB bus interface, an asynchronous serial bus interface, a CAN bus interface, a management processor, a clock synchronization circuit and a connector; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface and the CAN bus interface are respectively connected with a function board card with the same interface, the clock synchronization circuit is respectively connected with the connected function board card, and the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface, the CAN bus interface, the clock synchronization circuit and the connector are respectively connected with the management processor and the connector. A plurality of slots are arranged on the back plate, and various interfaces and corresponding function board cards are in communication connection through the slots on the back plate.
Example two
As shown in fig. 2, 4 and 5, the distributed computer bus backplane of the present embodiment includes a switch board, a function board and a backplane, where the switch board and the function board are both disposed on the backplane; the backplane of the embodiment adopts a double-switch architecture, and realizes double-path network link through a double-switch network; the distributed double-exchange back board is used as a data exchange path carrier of the exchange board card and the function board card and forms a complete double-exchange type distributed computer architecture with the function board card. Compared with single-switching performance, the reliability of the double-switching distributed architecture provides switching link redundancy, the reliability is improved by about 1 time, and the method can be generally applied to scenes with the highest reliability requirement.
The switching board card provides Ethernet, SRIO, USB bus, asynchronous serial bus and CAN bus switching management and control, and comprises two groups of Ethernet switching interfaces, SRIO switching interfaces, USB bus interfaces, asynchronous serial bus interfaces, CAN bus interfaces, a management processor, a clock synchronization circuit and a connector; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface and the CAN bus interface are respectively connected with a function board card with the same interface, the clock synchronization circuit is respectively connected with the connected function board card, and the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface, the CAN bus interface, the clock synchronization circuit and the connector are respectively connected with the management processor and the connector.
EXAMPLE III
As shown in fig. 3, 4 and 5, the distributed computer bus backplane of the present embodiment includes a switch board, a function board and a backplane, where the switch board and the function board are both disposed on the backplane; the backplane of the embodiment adopts a ring exchange type architecture, ring network link is realized through a ring exchange type network, and the distributed ring exchange backplane is used as a data exchange path carrier of the exchange board card and the function board card and forms a complete ring exchange type distributed computer architecture with the function board card. The complexity of the ring exchange distributed architecture is between that of a single exchange type and that of a double exchange type, and the reliability is improved by 50%.
The switching board card provides Ethernet, SRIO, USB bus, asynchronous serial bus and CAN bus switching management and control, and comprises an Ethernet switching interface, an SRIO switching interface, a USB bus interface, an asynchronous serial bus interface, a CAN bus interface, a management processor, a clock synchronization circuit and a connector; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface and the CAN bus interface are respectively connected with a function board card with the same interface, the clock synchronization circuit is respectively connected with the connected function board card, and the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface, the CAN bus interface, the clock synchronization circuit and the connector are respectively connected with the management processor and the connector.
The exchange bus CAN select one or more of Ethernet, SRIO, USB bus, RS232/485/422 bus and CAN bus according to the data bandwidth and cost requirement, when selecting various buses, the different buses CAN be used as exchange links to back up each other under the scheduling of software, thereby improving the reliability of the computer.
The clock synchronization circuit is used for realizing clock synchronization required by data acquisition and processing of each connection master control card and each function board card; the clock synchronization circuit comprises hardware synchronization and software synchronization, the hardware synchronization comprises a 100MHz synchronization pulse, all the functional board cards realize data acquisition and processing synchronization through hardware synchronization signals and software synchronization of the back board, and the rising edge T of the synchronization pulse signal is less than or equal to 1 ns; software synchronization adopts heartbeat packets for synchronization, and synchronization is performed by a communication protocol of a synchronous scheduling function board card (a main control board card and a function board card can be appointed by a system) specified by a user.
The mechanical structure form of the back plate can be selected from 3U (100mm multiplied by 160mm) and 6U (233.35mm multiplied by 160mm) dimension specifications defined by European standards IEC 60297-3 and IEC 60297-4, and the back plate slot connector form of the distributed back plate can be selected from CPCI slot connectors defined by European standards IEC60917 and IEC61076-4-101 or VPX slot connectors defined by European standard VITA 48.0. I.e., mechanically compatible with current CPCI and VPX structures to facilitate the adaptation to standard ruggedized chassis and structural components.
The functional board card is adapted by corresponding manufacturers according to the structure and electrical definition required by users, such as a scheduling function, a processing function, a storage function and the like.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (3)
1. A distributed computer bus backboard is characterized by comprising a switching board card, a functional board card and a backboard, wherein the switching board card and the functional board card are arranged on the backboard;
the switching board card provides Ethernet, SRIO, USB bus, asynchronous serial bus and CAN bus switching management and control, and comprises an Ethernet switching interface, an SRIO switching interface, a USB bus interface, an asynchronous serial bus interface, a CAN bus interface, a management processor, a clock synchronization circuit and a connector; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface and the CAN bus interface are respectively connected with a functional board card with the same interface, and the clock synchronization circuit is respectively connected with the connected functional board card; the Ethernet exchange interface, the SRIO exchange interface, the USB bus interface, the asynchronous serial bus interface, the CAN bus interface, the clock synchronization circuit and the connector are respectively connected with the management processor and the connector.
2. The distributed computer bus backplane according to claim 1, wherein the clock synchronization circuit comprises hardware synchronization and software synchronization, the hardware synchronization comprises a 100MHz synchronization pulse, so that all the functional boards achieve data acquisition and processing synchronization through hardware synchronization signals and software synchronization of the backplane, and a rising edge T of the synchronization pulse signal is less than or equal to 1 ns; software synchronization adopts heartbeat packets for synchronization, and synchronization is carried out by a synchronous scheduling function board card communication protocol specified by a user.
3. The distributed computer bus backplane of claim 1, wherein the backplane comprises a single switch backplane, a distributed dual switch backplane, or a distributed ring switch backplane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911189280.4A CN111008167A (en) | 2019-11-28 | 2019-11-28 | Distributed computer bus back plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911189280.4A CN111008167A (en) | 2019-11-28 | 2019-11-28 | Distributed computer bus back plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111008167A true CN111008167A (en) | 2020-04-14 |
Family
ID=70112980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911189280.4A Pending CN111008167A (en) | 2019-11-28 | 2019-11-28 | Distributed computer bus back plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111008167A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113612742A (en) * | 2021-07-23 | 2021-11-05 | 中国人民解放军军事科学院国防科技创新研究院 | Multi-mode search and rescue signal processing device based on VPX framework |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120265912A1 (en) * | 2011-04-13 | 2012-10-18 | International Business Machines Corporation | Out of band location information retrieval |
| CN102929365A (en) * | 2012-10-29 | 2013-02-13 | 北京航天测控技术有限公司 | PXI/PXIe (Pedpherd Component Interconnect eXtensions for Instrumentation/Pedpherd Component Interconnect eXtensions for Instrumentation Express) bus-based panel instrument platform |
| CN103236991A (en) * | 2013-03-29 | 2013-08-07 | 华为技术有限公司 | Communication system |
| CN103716201A (en) * | 2013-12-12 | 2014-04-09 | 中国科学院信息工程研究所 | Open wireless sensing network performance test method and open wireless sensing network performance test system |
| CN104391177A (en) * | 2014-11-17 | 2015-03-04 | 南车青岛四方机车车辆股份有限公司 | System and method for grid-side harmonic testing of CRH unit |
| CN104572534A (en) * | 2014-12-06 | 2015-04-29 | 呼和浩特铁路局科研所 | Locomotive information monitoring equipment and operating method thereof |
| CN108337577A (en) * | 2018-02-11 | 2018-07-27 | 中国电子科技集团公司第五十四研究所 | A kind of integrated backboards of novel VPX |
| CN109240960A (en) * | 2018-10-26 | 2019-01-18 | 天津光电通信技术有限公司 | A kind of power board circuit and its implementation based on VPX framework |
| CN209044488U (en) * | 2018-12-27 | 2019-06-28 | 山东超越数控电子股份有限公司 | A kind of super fusion calculation platform that can configure based on VPX framework |
-
2019
- 2019-11-28 CN CN201911189280.4A patent/CN111008167A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120265912A1 (en) * | 2011-04-13 | 2012-10-18 | International Business Machines Corporation | Out of band location information retrieval |
| CN102929365A (en) * | 2012-10-29 | 2013-02-13 | 北京航天测控技术有限公司 | PXI/PXIe (Pedpherd Component Interconnect eXtensions for Instrumentation/Pedpherd Component Interconnect eXtensions for Instrumentation Express) bus-based panel instrument platform |
| CN103236991A (en) * | 2013-03-29 | 2013-08-07 | 华为技术有限公司 | Communication system |
| CN103716201A (en) * | 2013-12-12 | 2014-04-09 | 中国科学院信息工程研究所 | Open wireless sensing network performance test method and open wireless sensing network performance test system |
| CN104391177A (en) * | 2014-11-17 | 2015-03-04 | 南车青岛四方机车车辆股份有限公司 | System and method for grid-side harmonic testing of CRH unit |
| CN104572534A (en) * | 2014-12-06 | 2015-04-29 | 呼和浩特铁路局科研所 | Locomotive information monitoring equipment and operating method thereof |
| CN108337577A (en) * | 2018-02-11 | 2018-07-27 | 中国电子科技集团公司第五十四研究所 | A kind of integrated backboards of novel VPX |
| CN109240960A (en) * | 2018-10-26 | 2019-01-18 | 天津光电通信技术有限公司 | A kind of power board circuit and its implementation based on VPX framework |
| CN209044488U (en) * | 2018-12-27 | 2019-06-28 | 山东超越数控电子股份有限公司 | A kind of super fusion calculation platform that can configure based on VPX framework |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113612742A (en) * | 2021-07-23 | 2021-11-05 | 中国人民解放军军事科学院国防科技创新研究院 | Multi-mode search and rescue signal processing device based on VPX framework |
| CN113612742B (en) * | 2021-07-23 | 2023-04-18 | 中国人民解放军军事科学院国防科技创新研究院 | Multi-mode search and rescue signal processing device based on VPX framework |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101594235B (en) | Method for managing blade server based on SMBUS | |
| CN102724093A (en) | Advanced telecommunications computing architecture (ATCA) machine frame and intelligent platform management bus (IPMB) connection method thereof | |
| CN109669901A (en) | A kind of server | |
| CN111008167A (en) | Distributed computer bus back plate | |
| US20240045821A1 (en) | Multi-path server and multi-path server signal interconnection system | |
| CN100389569C (en) | Data communication apparatus | |
| CN103793003A (en) | Exchange plate and blade server | |
| EP2555477A2 (en) | Advanced telecommunications computing architecture data exchange system, exchange board and data exchange method | |
| CN214851260U (en) | Intelligent network card out-of-band connection system | |
| CN111313869B (en) | Clock switching circuit of gigabit Ethernet transceiver | |
| CN101894055A (en) | Method for realizing blade mainboard interface with redundancy function | |
| WO2013013540A1 (en) | Atca machine frame system, construction method and rear board | |
| CN211149445U (en) | High-speed data processing platform | |
| CN106249838B (en) | Method, backboard and server for server power supply | |
| CN205091663U (en) | Modularization server backplate based on CPCI framework | |
| CN104460890A (en) | High-expansibility 1U server case | |
| CN101217380B (en) | An ATCA machine dimensions frame and machine dimensions frame system | |
| CN111371613A (en) | Blade server mixed insertion topological structure and system | |
| CN202887074U (en) | Advanced telecommunications computing architecture (ATCA) chassis capable of achieving bulk-storage memory | |
| CN108733610B (en) | Exchange board and blade server | |
| CN111030950B (en) | Topology construction method and device for stacking switch | |
| CN218587194U (en) | CPCI backboard | |
| CN107256070B (en) | Power panel supporting multi-node power supply of server and power switching circuit | |
| CN219533699U (en) | JESD204B interface clock tree, JESD204B interface group and equipment | |
| CN220273788U (en) | AFDX bus exchange equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200414 |
|
| RJ01 | Rejection of invention patent application after publication |