CN110995225A - Drive control circuit and method for optimizing switching characteristics of power semiconductor device - Google Patents
Drive control circuit and method for optimizing switching characteristics of power semiconductor device Download PDFInfo
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- CN110995225A CN110995225A CN201911148239.2A CN201911148239A CN110995225A CN 110995225 A CN110995225 A CN 110995225A CN 201911148239 A CN201911148239 A CN 201911148239A CN 110995225 A CN110995225 A CN 110995225A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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Abstract
The invention discloses a drive control circuit and a method for optimizing the switching characteristic of a power semiconductor device, wherein the method comprises the following steps: acquiring a driving signal; selecting preset selectable graded driving voltage according to graded driving signals in the driving signals, and outputting graded driving voltage signals; and amplifying the graded driving voltage signal and sending the signal to the power semiconductor device. The drive control circuit and the method for optimizing the switching characteristic of the power semiconductor device provided by the invention take drive control as an entry point, select the hierarchical drive voltage according to the hierarchical drive signal, output the hierarchical drive voltage signal, and then send the hierarchical drive voltage signal to the power semiconductor device to enable the power semiconductor device to make corresponding action response, so that the aim of optimizing the switching characteristic is fulfilled, and the design difficulty of drive protection is reduced.
Description
Technical Field
The invention relates to the technical field of power electronics and control, in particular to a drive control circuit and a method for optimizing switching characteristics of a power semiconductor device.
Background
When the SiC MOSFET is applied to a high-voltage large-capacity power electronic device of a power system as a novel wide and tight third-generation power semiconductor device, the cascade quantity of power modules can be greatly reduced, the topological structure of the system is simplified, the weight, the occupied area and the capacity of the power electronic device are reduced, and the power density and the efficiency of the device are improved. However, during the switching process of the SiCMOSFET, high on and off speeds may cause significant voltage and current surges, waveform oscillation phenomena, electromagnetic interference and other problems, which seriously affect the safety and reliability of the power system equipment.
Disclosure of Invention
In view of this, embodiments of the present invention provide a driving control circuit and method for optimizing switching characteristics of a power semiconductor device, so as to solve the problem in the prior art that an obvious voltage current surge and waveform oscillation are caused due to an excessively high switching speed.
In a first aspect, an embodiment of the present invention provides a driving control circuit for optimizing switching characteristics of a power semiconductor device, including: the micro-processing module is used for generating a driving signal; the level selection module is used for selecting preset selectable graded driving voltage according to the driving signal and outputting a driving voltage signal; and the power amplification module is used for amplifying the driving voltage signal and sending the driving voltage signal to the power semiconductor device.
In one embodiment, the stepped driving voltage includes: the step drive voltage is turned on and the step drive voltage is turned off.
In a second aspect, an embodiment of the present invention provides a driving control method for optimizing switching characteristics of a power semiconductor device, including: acquiring a driving signal; selecting preset optional hierarchical driving voltage according to hierarchical driving signals in the driving signals, and outputting hierarchical driving voltage signals; and amplifying the graded driving voltage signal and sending the signal to a power semiconductor device.
In one embodiment, the stepped driving voltage includes: the step drive voltage is turned on and the step drive voltage is turned off.
In one embodiment, the hierarchical driving signal comprises: and the power semiconductor device switch turns on the grading drive signal and turns off the grading drive signal.
In one embodiment, the characteristics of the stepped drive voltage include: a step drive voltage amplitude and/or a hold time of the step drive voltage amplitude. In an embodiment, the selecting a preset selectable stepped driving voltage according to the driving signal and outputting a driving voltage signal includes: when the driving signal is the switching-on hierarchical driving signal, selecting a hierarchical driving voltage in a switching-on process according to the switching-on hierarchical driving signal; and when the driving signal is the turn-off grading driving signal, selecting grading driving voltage in a turn-off process according to the turn-off grading driving signal.
In an embodiment, the step of selecting the gradation driving voltage of the turn-on process according to the turn-on gradation driving signal includes: at a first preset moment, according to the opening grading driving signal, converting the grid voltage of the power semiconductor device from a negative driving voltage into the opening grading driving voltage; maintaining the turn-on hierarchical driving voltage to a second preset time, wherein the drain current of the power semiconductor device in the turn-on process reaches the load current in the time period from the first preset time to the second preset time; and at the second preset moment, converting the grid voltage of the power semiconductor device from the opening grading driving voltage into a forward driving voltage, and maintaining the forward driving voltage until the moment of acquiring the next grading driving signal.
In one embodiment, the step of selecting the step driving voltage of the turn-off process according to the turn-off step driving signal comprises: at a third preset moment, converting the grid voltage of the power semiconductor device from the forward driving voltage into the turn-off grading driving voltage according to the turn-off grading driving signal; maintaining the turn-off hierarchical driving voltage to a fourth preset time, wherein the drain voltage of the power semiconductor device in the turn-off process reaches the direct-current bus voltage in a time period from the third preset time to the fourth preset time; and at the fourth preset moment, converting the grid voltage from the turn-off grading driving voltage into the negative driving voltage, and maintaining the negative driving voltage until the moment of acquiring the next grading driving signal.
The technical scheme of the invention has the following advantages:
1. the drive control circuit and the method for optimizing the switching characteristic of the power semiconductor device provided by the invention take drive control as an entry point, select the hierarchical drive voltage according to the hierarchical drive signal, output the hierarchical drive voltage signal, and then send the hierarchical drive voltage signal to the power semiconductor device to enable the power semiconductor device to make corresponding action response, so that the aim of optimizing the switching characteristic is fulfilled, and the design difficulty of drive protection is reduced.
2. According to the drive control circuit and the method for optimizing the switching characteristic of the power semiconductor device, influence analysis is carried out on the transient behavior process of the power semiconductor device according to the amplitude of the drive voltage and the holding time of the drive voltage in the switching-on and switching-off processes of the power semiconductor device, and a stepped middle graded drive voltage is designed in the process that the traditional drive voltage is directly changed from negative drive voltage to positive drive voltage, so that voltage and current peaks are reduced, the oscillation time of voltage and current is reduced, the electromagnetic interference characteristic is improved, the switching characteristic is optimized, and the safety of power system equipment is further protected.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a drive control circuit for optimizing the switching characteristics of a power semiconductor device provided in an embodiment of the present invention;
fig. 2 is a flowchart of a specific example of a driving control method for optimizing switching characteristics of a power semiconductor device according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a specific example of selecting a preset selectable stepped driving voltage according to a driving signal according to an embodiment of the present invention;
fig. 4 is a flowchart of a specific example of selecting the gradation driving voltage of the turn-on process according to the turn-on gradation driving signal according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of the operation of the step drive provided by the embodiment of the present invention;
fig. 6 is a schematic diagram of a step-driving turn-on process according to an embodiment of the present invention;
fig. 7 is a flowchart of a specific example of selecting the step driving voltage of the turn-off process according to the turn-off step driving signal according to the embodiment of the present invention;
fig. 8 is a schematic diagram of a step-drive shutdown process according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
An embodiment of the present invention provides a driving control circuit for optimizing switching characteristics of a power semiconductor device, as shown in fig. 1, including:
and the micro-processing module 1 is used for generating a driving signal. In the embodiment of the invention, the micro-processing module 1 generates the driving signal through the MCU, wherein the MCU properly reduces the frequency and the specification of the central processing unit, and integrates a memory (memory), a counter (Timer), a USB (universal serial bus), an A/D (analog/digital) converter, a UART (universal asynchronous receiver transmitter), a PLC (programmable logic controller), a DMA (direct memory access) and other peripheral interfaces, even an LCD (liquid crystal display) driving circuit on a single chip to form a chip-level computer, so that different combination control can be carried out on different application occasions. It should be noted that, in the embodiment of the present invention, only the MCU is taken as an example for description, in practical applications, other microcontrollers may be selected to generate the driving signal, and the present invention is not limited thereto.
And the level selection module 2 is used for selecting preset selectable graded driving voltage according to the driving signal and outputting a driving voltage signal. In the embodiment of the present invention, the level selection module 2 controls the level selection module 2 to select a preset selectable hierarchical driving voltage according to the driving signal sent by the microprocessor module 1, where the hierarchical driving voltage includes: the step drive voltage is turned on and the step drive voltage is turned off. After the level selection module 2 selects the hierarchical driving voltage, a driving voltage signal is output, and the driving voltage signal applies a section of stepped hierarchical driving voltage to the grid drive of the device in the process of switching on or switching off the power semiconductor device, so that a buffer process is provided for transient change of the power semiconductor device, di/dt of drain current in the switching-on process and dv/dt of drain-source voltage in the switching-off process can be effectively reduced, peak of current and voltage is reduced, oscillation time of the current and voltage is reduced, and switching characteristics of the device are improved.
And the power amplification module 3 is used for amplifying the driving voltage signal and sending the driving voltage signal to the power semiconductor device. In the embodiment of the invention, the power amplification module 3 converts the power of a power supply into the current which changes according to the input signal by using the current control function of the triode or the voltage control function of the field effect transistor, completes the amplification of the power through continuous current amplification, and sends the amplified signal to the power semiconductor device.
The drive control circuit for optimizing the switching characteristic of the power semiconductor device provided by the embodiment of the invention performs drive protection through a simple control circuit, reduces the design difficulty of drive protection, and further improves the safety and reliability of power system equipment.
Example 2
An embodiment of the present invention provides a drive control method for optimizing a switching characteristic of a power semiconductor device, as shown in fig. 2, the drive control method for optimizing the switching characteristic of the power semiconductor device includes:
step S1: a drive signal is acquired.
In the embodiment of the invention, the driving signal can be generated by the MCU for controlling voltage classification, reducing the amplitude of instantaneous voltage and current and noise conducted into the output and input ends, and further reducing electromagnetic interference, wherein the classification driving voltage comprises: the step driving voltage is turned on and the step driving voltage is turned off, it should be noted that, in the embodiment of the present invention, only the MCU is taken as an example for description, in practical applications, other microcontrollers may be selected to generate the driving signal, and the present invention is not limited thereto.
Step S2: and selecting preset selectable hierarchical driving voltage according to the hierarchical driving signals in the driving signals, and outputting a hierarchical driving voltage signal.
In the embodiment of the present invention, after the driving signal is obtained, a preset selectable hierarchical driving voltage is selected according to a hierarchical driving signal in the driving signal, where the hierarchical driving signal includes: the power semiconductor device is provided with an on-stage driving signal and an off-stage driving signal, and each stage driving signal comprises a stage driving voltage amplitude and/or a maintaining time of the stage driving voltage amplitude. After the graded driving voltage is selected, a graded driving voltage signal is output, and the graded driving voltage signal applies a stepped graded driving voltage to the grid drive of the device in the switching-on or switching-off process of the power semiconductor device, so that a buffer process is provided for transient change of the power semiconductor device, di/dt of drain current in the switching-on process and dv/dt of drain-source voltage in the switching-off process can be effectively reduced, peak of current and voltage is reduced, oscillation time of the current and voltage is reduced, noise conducted into output and input ends is reduced, electromagnetic interference is reduced, and switching characteristics of the device are improved.
Step S3: and amplifying the graded driving voltage signal and sending the signal to the power semiconductor device.
In the embodiment of the invention, the power amplifier is utilized to amplify the output graded driving voltage signal and then send the amplified signal to the power semiconductor device, and the power semiconductor device makes a corresponding response.
The drive control method for optimizing the switching characteristic of the power semiconductor device provided by the embodiment of the invention takes drive control as an entry point, selects the hierarchical drive voltage according to the hierarchical drive signal, outputs the hierarchical drive voltage signal, and then sends the hierarchical drive voltage signal to the power semiconductor device to enable the power semiconductor device to make corresponding action response, so that the aim of optimizing the switching characteristic is fulfilled, and the design difficulty of drive protection is reduced.
In a specific embodiment, as shown in fig. 3, the process of executing step S2 may specifically include the following steps:
step S21: and when the grading driving signal is an opening grading driving signal, selecting the grading driving voltage in the opening process according to the opening grading driving signal.
In practical application, when the obtained hierarchical driving signal is an opening hierarchical driving signal, the corresponding hierarchical driving voltage amplitude and/or the maintenance time of the hierarchical driving voltage amplitude in the opening process is/are selected according to the opening hierarchical driving signal. It should be noted that the amplitude of the stepped driving voltage and/or the holding time of the amplitude of the stepped driving voltage are set in advance according to the actual needs of the system, and may be adjusted according to the actual needs, which is not limited in the present invention.
Step S22: and when the grading driving signal is the shutdown grading driving signal, selecting the grading driving voltage in the shutdown process according to the shutdown grading driving signal.
In practical application, when the obtained graded driving signal is an off graded driving signal, the graded driving voltage amplitude and the maintaining time of the graded driving voltage amplitude in the off process are selected according to the off graded driving signal.
In a specific embodiment, as shown in fig. 4, the process of executing step S21 may specifically include the following steps:
step S211: and at a first preset moment, according to the turn-on grading driving signal, converting the grid voltage of the power semiconductor device from a negative driving voltage into a turn-on grading driving voltage.
In the embodiment of the present invention, a power semiconductor device SiC MOSFET is illustrated as shown in FIG. 5, wherein UgIs the gate voltage, VgoffIs a negative driving voltage, VgonIs a forward driving voltage, VmidAnd TmidThe amplitude of the stepped driving voltage and the sustain time of the stepped driving voltage, respectively. Before the first preset moment (T1) when the SiC MOSFET is turned on, the gate voltage is controlled by the MCU to be the negative driving voltage (V)goff) The SiC MOSFET is maintained in a stable OFF state, and at time T1, the MCU switches the gate voltage from Vgoff to an ON hierarchical driving voltage (V) in accordance with the hierarchical driving signalmid1) Instead of changing directly to VgonThis corresponds to a buffering procedure being provided for the switching-on procedure.
Step S212: and maintaining the turn-on hierarchical driving voltage to a second preset time, and enabling the drain current of the power semiconductor device in the turn-on process to reach the load current within the time period from the first preset time to the second preset time.
In the embodiment of the present invention, the above Vmid1Will maintain Tmid1Time during which the drain current of the power semiconductor device during turn-on reaches the load current, i.e. the drain current i, during a period of time from a first preset time (T1) to a second preset time (T2)dHas substantially reached the load current I0By the pair Vmid1And Tmid1To achieve slow down idThe change speed of the SiC MOSFET is improved, and the purpose of improving the switching characteristic of the SiC MOSFET in the switching-on process is achieved.
Step S213: and at a second preset moment, converting the grid voltage of the power semiconductor device from the opening graded driving voltage into a forward driving voltage, and maintaining the forward driving voltage until the moment of acquiring the next graded driving signal.
In the embodiment of the invention, at the time T2, idThe rising process of (1) is substantially completed, and the gate voltage is then changed from Vmid1Becomes VgonAnd maintaining the forward driving voltage until the time of acquiring the next gradation driving signal, that is, maintaining the gate voltage at V all the timegonAnd the completion of the opening process is accelerated.
In practical applications, the step-drive turn-on process is illustrated by way of an example of a SiC MOSFET power semiconductor device, as shown in fig. 6, where the SiC MOSFET remains in a stable off-state until time t1, UgHeld at a negative drive voltage control signal, gate-source voltage (V)gs) Is maintained at a negative driving voltage (V)goff) Drain-source voltage (V)ds) Is kept at UdcWithout drain current (i)d) Generating; at stage t 1-t 2: v of SiC MOSFETgsFrom VgoffUp to VthAt time t1, drive control signal UgFrom a negative drive control signal to a stepped drive voltage control signal and is maintained at the control voltage signal, V, during this phasegsFrom VgoffGradually rises to VthDue to Vgs＜VthAt this stage the MOSFET is not conducting, VdsAnd idNo change is made; at stage t 2-t 3: u shapegIs still at VmidControl voltage signal of the phase Vgs＞VthThe MOSFET is gradually turned on, idWith VgsRises rapidly of (V)dsThe voltage drop is generated on the parasitic inductance due to the change of the current, and the voltage is reduced to some extent, but still is similar to the voltage of a direct current bus; at stage t 3-t 4: at time t3, UgFrom a stepped drive voltage signal to a forward drive voltage control signal, during which stage VgsContinuously rising to the Miller plateau voltage, VdsWith the conduction of the MOSFET, the voltage of the nearly direct current bus is rapidly reduced until the voltage is reduced to the end of on-state voltage reduction; at stage t 4-t 5: vgsFrom the Miller plateau voltage to the forward drive voltage (V)gon)，VdsAnd idAnd tends to be stable.
In a specific embodiment, as shown in fig. 7, the process of executing step S22 may specifically include the following steps:
step S221: and at a third preset moment, according to the turn-off grading driving signal, converting the grid voltage of the power semiconductor device from the forward driving voltage into the turn-off grading driving voltage.
In the embodiment of the invention, as shown in fig. 5, before the third preset time (T3) when the SiC MOSFET is turned off, the MCU controls the gate voltage to be VgonThe SiC MOSFET is maintained in a stable ON state, and at time T3, the MCU transitions the gate voltage from Vgon to an OFF graded drive voltage (V) in response to an OFF graded drive signalmid2) This corresponds to a buffering procedure being provided for the shut down procedure.
Step S222: and maintaining the turn-off step driving voltage to a fourth preset time, and in the time period from the third preset time to the fourth preset time, the drain voltage of the power semiconductor device in the turn-off process reaches the direct-current bus voltage.
In the embodiment of the present invention, the above Vmid2Will maintain Tmid2Time, during the time period (T4) from the third preset time (T3) to the fourth preset time, the drain voltage of the turn-off process reaches the direct current bus voltage, namely the drain-source voltage VdsHas substantially reached the DC bus voltage UdcBy the pair Vmid2And Tmid2To slow down VdsThe change speed of the SiCMOS MOSFET is improved, and the purpose of improving the switching characteristic of the SiCMOS MOSFET in the turn-off process is achieved.
Step S223: and at a fourth preset moment, converting the grid voltage from the turn-off grading driving voltage into a negative driving voltage, and maintaining the negative driving voltage until the moment of acquiring the next grading driving signal.
In the embodiment of the invention, V is at the time of T3dsThe rising process of (1) is substantially completed, and the gate voltage is then changed from Vmid2Becomes VgoffAnd maintaining the forward driving voltage until the time of acquiring the next gradation driving signal, that is, maintaining the gate voltage at VgoffThe completion of the shutdown process is accelerated.
In practical applications, the step-drive turn-off process is illustrated by taking a SiC MOSFET power semiconductor device as an example, and as shown in fig. 8, until time t6, the SiC MOSFET remains in a stable on-state, UgHeld at the positive drive voltage control signal, gate-source voltage (V)gs) Is maintained at a forward driving voltage (V)gon) Drain current (i)d) Is maintained at I0No leakage source voltage (V)ds) Generating; at stage t 6-t 7: v of SiC MOSFETgsFrom VgonDown to the miller plateau voltage VmilAt time t6, drive control signal UgIs changed from a forward drive control signal to a stepped drive voltage control signal and is maintained at the control voltage signal, V, during this phasegsFrom VgonGradually decrease to VmilDue to Vgs＞VmilAt this stage the MOSFET is not switched off, VdsAnd idNo change is made; at stage t 7-t 8: u shapegIs still at VmidControl voltage signal of the phase Vgs＜VmilThe MOSFET is gradually turned off idWith VgsIs gradually decreased, VdsThe voltage change is generated on the parasitic inductance due to the change of the current and then rises rapidly; at stage t 8-t 9: at time t8, UgFrom a stepped drive voltage signal to a negative drive voltage control signal, during which phase VgsContinuously drops to Vth，VdsWith the MOSFET switched off, the voltage rises rapidly; at stage t 9-t 10: vgsFrom VthDown to a negative driving voltage (V)goff)，VdsAnd idAnd tends to be stable.
According to the drive control method for optimizing the switching characteristic of the power semiconductor device, in the process of switching on and switching off the power semiconductor device, according to the influence analysis of the amplitude of the drive voltage and the holding time of the drive voltage on the transient behavior process of the power semiconductor device, in the process that the traditional drive voltage is directly changed from negative drive voltage to positive drive voltage, a step middle grading drive voltage is designed, so that the voltage and current peak is reduced, the oscillation time of voltage and current is reduced, the electromagnetic interference characteristic is improved, the switching characteristic is optimized, and the safety of power system equipment is further protected.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (9)
1. A drive control circuit for optimizing switching characteristics of a power semiconductor device, comprising:
the micro-processing module is used for generating a driving signal;
the level selection module is used for selecting preset selectable graded driving voltage according to the driving signal and outputting a driving voltage signal;
and the power amplification module is used for amplifying the driving voltage signal and sending the driving voltage signal to the power semiconductor device.
2. The drive control circuit for optimizing switching characteristics of a power semiconductor device according to claim 1, wherein said stepped drive voltage comprises: the step drive voltage is turned on and the step drive voltage is turned off.
3. A drive control method for optimizing switching characteristics of a power semiconductor device, comprising:
acquiring a driving signal;
selecting preset optional hierarchical driving voltage according to hierarchical driving signals in the driving signals, and outputting hierarchical driving voltage signals;
and amplifying the graded driving voltage signal and sending the signal to a power semiconductor device.
4. The drive control method for optimizing switching characteristics of a power semiconductor device according to claim 3, wherein said step driving voltage comprises: the step drive voltage is turned on and the step drive voltage is turned off.
5. The drive control method for optimizing switching characteristics of a power semiconductor device according to claim 4, wherein said step driving signal comprises: and the power semiconductor device switch turns on the grading drive signal and turns off the grading drive signal.
6. The drive control method for optimizing switching characteristics of a power semiconductor device according to claim 5, wherein the characteristics of the stepped drive voltage comprise: a step drive voltage amplitude and/or a hold time of the step drive voltage amplitude.
7. The driving control method for optimizing the switching characteristics of the power semiconductor device according to claim 6, wherein the selecting a preset selectable stepped driving voltage according to the stepped driving signal and outputting a stepped driving voltage signal comprises:
when the grading driving signal is the opening grading driving signal, selecting grading driving voltage in an opening process according to the opening grading driving signal;
and when the grading driving signal is the shutdown grading driving signal, selecting the grading driving voltage in the shutdown process according to the shutdown grading driving signal.
8. The driving control method for optimizing switching characteristics of a power semiconductor device according to claim 7, wherein said step of selecting a graded driving voltage for a turn-on process according to said turn-on graded driving signal comprises:
at a first preset moment, according to the opening grading driving signal, converting the grid voltage of the power semiconductor device from a negative driving voltage into the opening grading driving voltage;
maintaining the turn-on hierarchical driving voltage to a second preset time, wherein the drain current of the power semiconductor device in the turn-on process reaches the load current in the time period from the first preset time to the second preset time;
and at the second preset moment, converting the grid voltage of the power semiconductor device from the opening grading driving voltage into a forward driving voltage, and maintaining the forward driving voltage until the moment of acquiring the next grading driving signal.
9. The driving control method for optimizing switching characteristics of a power semiconductor device according to claim 8, wherein said step of selecting a step driving voltage for a turn-off process according to said turn-off step driving signal comprises:
at a third preset moment, converting the grid voltage of the power semiconductor device from the forward driving voltage into the turn-off grading driving voltage according to the turn-off grading driving signal;
maintaining the turn-off hierarchical driving voltage to a fourth preset time, wherein the drain voltage of the power semiconductor device in the turn-off process reaches the direct-current bus voltage in a time period from the third preset time to the fourth preset time;
and at the fourth preset moment, converting the grid voltage from the turn-off grading driving voltage into the negative driving voltage, and maintaining the negative driving voltage until the moment of acquiring the next grading driving signal.
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| CN113659967B (en) * | 2021-08-23 | 2024-06-04 | 华北电力大学 | Driving circuit and method for optimizing silicon carbide MOSFET switching characteristics |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111614235A (en) * | 2020-06-01 | 2020-09-01 | 武汉理工大学 | Wide bandgap MOSFET drive circuit |
| CN111614235B (en) * | 2020-06-01 | 2023-09-12 | 武汉理工大学 | Wide bandgap MOSFET driving circuit |
| CN112600394A (en) * | 2020-12-07 | 2021-04-02 | 国网江苏省电力有限公司宿迁供电分公司 | Multi-step driving control method of wide bandgap power device |
| CN113659967A (en) * | 2021-08-23 | 2021-11-16 | 华北电力大学 | Drive circuit and method for optimizing silicon carbide MOSFET switching characteristics |
| CN113659967B (en) * | 2021-08-23 | 2024-06-04 | 华北电力大学 | Driving circuit and method for optimizing silicon carbide MOSFET switching characteristics |
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