CN111628633B - SiC MOSFET drive circuit based on auxiliary pulse - Google Patents
SiC MOSFET drive circuit based on auxiliary pulse Download PDFInfo
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- CN111628633B CN111628633B CN202010433826.2A CN202010433826A CN111628633B CN 111628633 B CN111628633 B CN 111628633B CN 202010433826 A CN202010433826 A CN 202010433826A CN 111628633 B CN111628633 B CN 111628633B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses an auxiliary pulse-based SiC MOSFET (metal oxide semiconductor field effect transistor) driving circuit, which comprises a main driving module, an auxiliary logic circuit module, a low-power MOS (metal oxide semiconductor) transistor Q1 and a current-limiting resistor R1, wherein the main driving module converts an original driving signal VPWM (virtual pulse width modulation) into a gate driving voltage V with powerGAnd is connected to the G pole of the SiC-MOS tube Qm; the original driving signal VPWM is simultaneously connected to the auxiliary logic circuit module, the output end of the auxiliary logic circuit module is sequentially connected with the low-power MOS transistor Q1 and the current-limiting resistor R1, the downstream of the current-limiting resistor R1 is connected to the G pole of the SiC-MOS transistor Qm, and the main gate charging and discharging current is provided for the gate pole of the main driving module, so that the time of each stage of the driving process is controlled. The SiC MOSFET drive circuit based on the auxiliary pulse adopts the auxiliary logic circuit, the low-power MOS tube Q1 and the current-limiting resistor R1 to complete the adjustment of the drive signal, and realizes the independent sectional control of the switching-on and switching-off processes, so that the SiC MOSFET drive circuit is simple and exquisite, and is convenient to popularize and apply.
Description
Technical Field
The invention relates to the electric element driving technology, in particular to a SiC MOSFET driving circuit based on auxiliary pulses.
Background
A Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is a Field-Effect Transistor (Field-Effect Transistor) that can be widely used in analog circuits and digital circuits. A typical power MOSFET operating circuit is shown in fig. 1, and the MOSFET switching process is shown in fig. 2.
VPWMThe high level is used for controlling the MOS tube to be switched on, and the low level is used for controlling the MOS tube to be switched off. The voltage actually applied to the gate is VGDue to the charging and discharging of the capacitor junction capacitance, the gate voltage is not an ideal square wave, presenting several charging periods: wherein, the gate capacitance is charged to the threshold voltage V in the period of t1-t2THAt this time, the mos tube does not act. the gate reaches the threshold voltage V during the period from t2 to t3THRear, main circuitThe current of the freewheeling diode from above is transferred to the MOS tube.
In the conventional driving circuit, since the driving voltage and the resistance are fixed, the time of each step is determined after the parameters of the driving circuit are set. However, such a driving waveform is not optimal, and particularly for SiC MOSFETs, it is difficult to achieve both of the switching loss and EMI (Electromagnetic Interference, EMI for short). Therefore, the prior art considers a method of segment driving, and the basic idea is as follows.
1. The time from t1 to t2 is shortened, and the opening delay is reduced.
2. Increasing the time from t2 to t3 decreases the rate of current increase to reduce current overshoot.
3. The time from t3 to t4 is shortened, and the switching loss is reduced.
4. And the time from t5 to t6 is reduced, and the turn-off delay is reduced.
5. The time from t6 to t7 is shortened, the voltage rising speed is accelerated, and the turn-off loss is reduced.
6. And the time from t7 to t8 is increased, the current change rate is reduced, and the voltage overshoot is reduced.
These time periods may be considered as charging and discharging times for the gate capacitance. Therefore, the measure to control these time periods is to change the gate current. Increasing the gate current may decrease the duration of the phase, whereas decreasing the gate current increases the duration of the phase.
There are many ways to vary the gate current, one is open loop, such as using switches to switch in different drive resistances at different stages; there are also methods of changing the gate current using a feedback mechanism, such as feedback control by sensing the drain current, or feedback control by sensing the DS voltage.
For the driving method of the switching resistor, the complexity of the driving loop is increased, and additional parasitic inductance is introduced, thereby causing additional resonance. The feedback method needs to add a sensor with extremely high sampling speed, and the practical effect is limited by sampling delay and sampling interference.
Disclosure of Invention
To overcome the deficiencies of the prior art, it is an object of the present invention to provide an auxiliary pulse based SiC MOSFET driver circuit that addresses the above-mentioned deficiencies of conventional improved gate currents.
The purpose of the invention is realized by adopting the following technical scheme:
the utility model provides a SiC MOSFET drive circuit based on auxiliary pulse, drive circuit includes main drive module, supplementary logic circuit module, miniwatt MOS pipe Q1 and current limiting resistance R1, main drive circuit of main drive module includes positive voltage VCC, negative supply VEE and original drive signal V1PWMThe original driving signal V is driven by the main driving modulePWMConversion to a gate drive voltage V with powerGAnd is connected to the G pole of the SiC-MOS tube Qm; the original drive signal VPWMThe auxiliary logic circuit module is connected to the auxiliary logic circuit module, the output end of the auxiliary logic circuit module is sequentially connected with the low-power MOS transistor Q1 and the current-limiting resistor R1, the downstream of the current-limiting resistor R1 is connected to the G pole of the SiC-MOS transistor Qm, and the main gate pole charging and discharging current is provided for the gate pole of the main driving module, so that the time of each stage of the driving process is controlled.
Preferably, the logic circuits of the auxiliary logic circuit module include a first rising edge delay circuit, a rising edge delay second circuit, a falling edge first delay circuit, a second falling edge delay circuit, two exclusive OR logic circuits XOR and one OR logic circuit OR; the first rising edge delay circuit, the rising edge delay second circuit and an exclusive-OR logic circuit XOR and OR are sequentially connected in a telecommunication way, and the output end of the first rising edge delay circuit is also connected to the input end of the exclusive-OR logic circuit XOR; the falling edge first delay circuit, the falling edge delay second circuit, the other exclusive-OR logic circuit XOR and OR logic circuit OR are in turn telecommunication connected, and the output of the falling edge first delay circuit is also connected to the input of the other exclusive-OR logic circuit XOR.
Preferably, the first square pulse signal Va1 is generated by a first rising edge delay circuit, a rising edge delay second circuit and one of the XOR logic circuits XOR, and the gate charging time is extended by shunting a part of the charging current, thereby reducing the current change rate and reducing the current overshoot.
Preferably, the second square pulse signal Va2 is generated by the falling edge first delay circuit, the second falling edge delay circuit and another one of the XOR logic circuits XOR, and the gate discharge time is reduced, the current change rate is increased, and the loss is reduced by increasing a part of the discharge current.
Preferably, the gate of the low-power MOS transistor Q1 is connected to the output terminal of the auxiliary logic circuit module, the S-pole of the low-power MOS transistor Q1 is connected to the negative power supply VEE, and the D-pole of the low-power MOS transistor Q1 is connected to the upstream end of the current-limiting resistor R1.
Preferably, when the auxiliary logic circuit module is suitable for driving a high-speed logic device, the auxiliary logic circuit module adopts a logic circuit powered by 5V or 3.3V; when the drive control of the charging current is adapted, the auxiliary logic circuit module adopts a logic circuit powered by 20V.
Compared with the prior art, the invention has the beneficial effects that: the SiC MOSFET drive circuit based on the auxiliary pulse adopts the auxiliary logic circuit, the low-power MOS tube Q1 and the current-limiting resistor R1 to complete the adjustment of the drive signal, and realizes the independent sectional control of the switching-on and switching-off processes, so that the SiC MOSFET drive circuit is simple and exquisite, and is convenient to popularize and apply.
Drawings
FIG. 1 is a circuit diagram of a conventional power MOSFET;
FIG. 2 is a schematic diagram of driving waveforms of a conventional power MOSFET switching process;
FIG. 3 is a SiC MOSFET driver circuit based on auxiliary pulses according to the present application;
FIG. 4 is a schematic diagram of an auxiliary pulse based SiC MOSFET drive waveform;
FIG. 5 is a schematic diagram of an auxiliary logic circuit and its detection;
fig. 6 shows waveforms corresponding to the auxiliary logic circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 3-6, the drive circuit of the SiC MOSFET based on auxiliary pulse comprises a main drive module, an auxiliary logic circuit module, a low-power MOS transistor Q1 and a current-limiting resistor R1.
The main drive circuit of the main drive module adopts a conventional drive circuit and comprises a positive voltage VCC, a negative power supply VEE and an original drive signal VPWMThe original driving signal V is driven by the main driving modulePWMConversion to a gate drive voltage V with powerGAnd is connected to the G pole of the SiC-MOS tube Qm.
The main driving circuit of the main driving module may take many existing forms, which are not limited herein.
Original drive signal VPWMThe auxiliary logic circuit module is connected to the auxiliary logic circuit module, the output end of the auxiliary logic circuit module is sequentially connected with the low-power MOS transistor Q1 and the current-limiting resistor R1, the downstream of the current-limiting resistor R1 is connected to the G pole of the SiC-MOS transistor Qm, and the main gate pole charging and discharging current is provided for the gate pole of the main driving module, so that the time of each stage of the driving process is controlled.
The gate of the low-power MOS transistor Q1 is connected to the output terminal of the auxiliary logic circuit module, the S-pole of the low-power MOS transistor Q1 is connected to the negative power VEE, and the D-pole of the low-power MOS transistor Q1 is connected to the upstream end of the current-limiting resistor R1.
See FIG. 4, VPWMVa is a control signal of a low-power MOS tube Q1 generated by an auxiliary logic circuit, VG is a G electrode voltage of an actual SiC MOSFET, and VD and Id are a voltage across the DS of the SiC MOSFET and a current passing through the D electrode respectively.
Referring to fig. 5, the logic circuits of the auxiliary logic circuit block include a first rising edge delay circuit, a rising edge delay second circuit, a falling edge first delay circuit, a second falling edge delay circuit, two exclusive OR logic circuits XOR, and one OR logic circuit OR. Here, the signal waveform may be monitored by an oscilloscope Scope (not included in the scheme).
Specifically, the logic circuit is divided into two paths, as shown in fig. 5.
The first path is as follows: the first rising edge delay circuit, the rising edge delay second circuit, an exclusive OR logic circuit XOR and OR logic circuit OR are in turn telecommunication connected, and the output of said first rising edge delay circuit dt1 is also connected to the input of one of said exclusive OR logic circuits XOR.
The first rectangular pulse signal Va1 shown in fig. 6 is generated by delaying the circuit delay time dt1 by the first rising edge, delaying the second circuit delay dt2 by the rising edge, and by the exclusive or logic circuit XOR. The first square pulse signal Va1 corresponds to the stages t2-t3 in fig. 4, and is used for prolonging the gate charging time by shunting a part of the charging current, thereby reducing the current change rate and reducing the current overshoot.
And a second path: the falling edge first delay circuit, the falling edge delay second circuit, the further XOR logic circuit XOR and OR logic circuit OR are in turn telecommunication connected, and the output of said falling edge first delay circuit dt3 is also connected to the input of the further said XOR logic circuit XOR.
The second rectangular pulse signal Va2 shown in fig. 6 is generated by the falling edge first delay circuit delay time dt3, the second falling edge delay circuit delay time dt4 and another exclusive-or logic circuit XOR, wherein the second rectangular pulse signal Va2, corresponding to the stages t7-t8 in fig. 4, functions to reduce the gate discharge time by increasing a part of the discharge current, accelerate the current change rate, reduce the time, and reduce the loss.
Specifically, the delay circuit may adopt an RC delay circuit, and utilize the inverting characteristic of the JK flip-flop or a holding circuit. The NOP instruction delay of the single chip microcomputer can be used, and the method is not limited here.
Further, when the auxiliary logic circuit module is suitable for driving a high-speed logic device, the auxiliary logic circuit module adopts a logic circuit powered by 5V or 3.3V; when the drive control of the charging current is adapted, the auxiliary logic circuit module adopts a logic circuit powered by 20V.
In summary, the scheme of the application can realize independent sectional control of the switching-on and switching-off processes by only adopting one MOS tube. The circuit is simple and exquisite, and the complexity of a driving loop and the problem of inductance introduced by excessive components are avoided.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (2)
1. A kind of SiC MOSFET drive circuit based on auxiliary pulse, characterized by that:
the driving circuit comprises a main driving module, an auxiliary logic circuit module, a low-power MOS tube Q1 and a current-limiting resistor R1,
the main drive circuit of the main drive module comprises a positive voltage VCC, a negative power supply VEE and an original drive signal VPWMThe original driving signal V is driven by the main driving modulePWMConversion to a gate drive voltage V with powerGAnd is connected to the G pole of the SiC-MOS tube Qm;
the original drive signal VPWMThe output end of the auxiliary logic circuit module is sequentially connected with the low-power MOS transistor Q1 and a current-limiting resistor R1, the downstream of the current-limiting resistor R1 is connected to the G pole of the SiC-MOS transistor Qm, and provides charging and discharging current of a main gate pole for a gate pole of the main driving module, so that the time of each stage of the driving process is controlled;
the logic circuit of the auxiliary logic circuit module comprises a first rising edge delay circuit, a rising edge delay second circuit, a falling edge first delay circuit, a second falling edge delay circuit, two exclusive OR logic circuits XOR and an OR logic circuit OR;
the first rising edge delay circuit, the rising edge delay second circuit and an exclusive-OR logic circuit XOR and OR are sequentially connected in a telecommunication way, and the output end of the first rising edge delay circuit is also connected to the input end of the exclusive-OR logic circuit XOR;
the falling edge first delay circuit, the falling edge delay second circuit and the other XOR logic circuit XOR and OR are sequentially connected in telecommunication, and the output end of the falling edge first delay circuit is also connected to the input end of the other XOR logic circuit XOR;
generating a first rectangular pulse signal Va1 through a first rising edge delay circuit, a rising edge delay second circuit and one exclusive-OR logic circuit XOR, prolonging the gate charging time by shunting a part of the charging current, thereby reducing the current change rate of the SiC MOSFET and reducing the current overshoot thereof;
the second square pulse signal Va2 is generated by the falling edge first delay circuit, the second falling edge delay circuit and another one of the exclusive or logic circuits XOR, and the gate discharge time is reduced, the current change rate is increased and the loss is reduced by increasing a part of the discharge current.
2. The SiC MOSFET driver circuit of claim 1, wherein:
the gate of the low-power MOS tube Q1 is connected with the output end of the auxiliary logic circuit module, the S electrode of the low-power MOS tube Q1 is connected with the negative power supply VEE, and the D electrode of the low-power MOS tube Q1 is connected with the upstream end of the current-limiting resistor R1.
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| CN202010433826.2A CN111628633B (en) | 2020-05-21 | 2020-05-21 | SiC MOSFET drive circuit based on auxiliary pulse |
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| CN202010433826.2A CN111628633B (en) | 2020-05-21 | 2020-05-21 | SiC MOSFET drive circuit based on auxiliary pulse |
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| CN111628633B true CN111628633B (en) | 2021-06-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101325364A (en) * | 2007-06-11 | 2008-12-17 | 日产自动车株式会社 | Drive circuit for voltage driven electronic element |
| CN102315763A (en) * | 2011-09-08 | 2012-01-11 | 周卫国 | Intelligent power module having soft turn off function |
| CN102522070A (en) * | 2011-12-24 | 2012-06-27 | 西安启芯微电子有限公司 | Control circuit for eliminating glittering and shutdown ghosting phenomena of thin film field effect transistor |
| CN102624374A (en) * | 2012-04-18 | 2012-08-01 | 烽火通信科技股份有限公司 | Current-mode logic (CML) level driving circuit with pre-emphasis function |
| JP2017028406A (en) * | 2015-07-17 | 2017-02-02 | トヨタ自動車株式会社 | Gate drive circuit for voltage-driven switching device |
| CN110739950A (en) * | 2018-07-19 | 2020-01-31 | 纳维达斯半导体公司 | Power transistor control signal control |
| CN110838787A (en) * | 2019-11-15 | 2020-02-25 | 湖南大学 | SiC MOSFET active driving circuit for improving driving performance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230258B (en) * | 2016-08-29 | 2018-12-14 | 杰华特微电子（杭州）有限公司 | The driving method and circuit and power-supply system of power switch tube |
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- 2020-05-21 CN CN202010433826.2A patent/CN111628633B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101325364A (en) * | 2007-06-11 | 2008-12-17 | 日产自动车株式会社 | Drive circuit for voltage driven electronic element |
| CN102315763A (en) * | 2011-09-08 | 2012-01-11 | 周卫国 | Intelligent power module having soft turn off function |
| CN102522070A (en) * | 2011-12-24 | 2012-06-27 | 西安启芯微电子有限公司 | Control circuit for eliminating glittering and shutdown ghosting phenomena of thin film field effect transistor |
| CN102624374A (en) * | 2012-04-18 | 2012-08-01 | 烽火通信科技股份有限公司 | Current-mode logic (CML) level driving circuit with pre-emphasis function |
| JP2017028406A (en) * | 2015-07-17 | 2017-02-02 | トヨタ自動車株式会社 | Gate drive circuit for voltage-driven switching device |
| CN110739950A (en) * | 2018-07-19 | 2020-01-31 | 纳维达斯半导体公司 | Power transistor control signal control |
| CN110838787A (en) * | 2019-11-15 | 2020-02-25 | 湖南大学 | SiC MOSFET active driving circuit for improving driving performance |
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