CN110995202B - Digital filtering device and method - Google Patents
Digital filtering device and method Download PDFInfo
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- CN110995202B CN110995202B CN201911368598.9A CN201911368598A CN110995202B CN 110995202 B CN110995202 B CN 110995202B CN 201911368598 A CN201911368598 A CN 201911368598A CN 110995202 B CN110995202 B CN 110995202B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
Abstract
The application discloses a digital filtering device and a digital filtering method, wherein the device comprises a control module, a frequency division module, a single filtering module and a constant filtering module; the application divides the whole filtering system into a control module, a frequency division module, a single filtering module and a constant filtering module, and determines the range of the filtering pulse width by adjusting the frequency division ratio of the frequency division module; the single filtering module is used for filtering unstable signals in a long time, and the common filtering module filters signal burrs, so that burrs generated by signals in the working process of the integrated circuit are filtered, and signal distortion is prevented.
Description
Technical Field
The present application relates to the field of filter circuits, and in particular, to a digital filter device and method.
Background
With the continuous development of integrated circuits, the complexity of chips is also increasing, and the more complex the circuit structure in the chips is. When power management is performed in a chip, the output signal of the analog IP such as the voltage comparator and the analog-to-digital converter may have a certain noise due to the influence of the design of the internal circuit, the influence of the external environment such as temperature, and the interference of the electromagnetic environment.
In an integrated circuit, during an initial period of time or a later use of voltage active or active enable, signal glitches may occur due to signal flipping, resulting in signal distortion.
In summary, in the prior art, the signal may generate a glitch phenomenon during the operation of the integrated circuit, which results in a signal distortion technical problem.
Disclosure of Invention
The application provides a digital filtering device and a digital filtering method, which solve the technical problem that signal distortion exists due to the phenomenon that signals generate burrs in the working process of an integrated circuit in the prior art.
The application provides a digital filtering device, which comprises a control module, a frequency division module, a single filtering module and a constant filtering module, wherein the frequency division module is used for dividing the frequency of the digital filtering module;
the control module is used for controlling the output mode of the output signal of the digital filter device;
the frequency division module is used for providing clock signals for the single filtering module and the constant filtering module, and the single filtering module and the constant filtering module determine the width of the filtering pulse according to the clock signals;
the single filtering module is used for filtering long-time unstable signals in the signals and transmitting the filtered signals to the constant filtering module;
the constant filtering module is used for filtering noise burrs in the received signals and outputting the filtered signals.
Preferably, the single filtering module comprises an enabling signal sending module, a counting module and a plurality of groups of filtering circuits, and the counting module is connected with each group of filtering circuits;
the enabling signal sending module is used for providing enabling signals for each group of filter circuits;
the counting module is used for recording an initial counting state when each group of filter circuits are enabled, and closing enabling signals of each group of filter circuits when the counting of each group of filter circuits reaches the ending moment;
the multi-group filter circuit is used for filtering the unstable signals for a long time and transmitting the filtered unstable signals to the constant filter module.
Preferably, when the multi-group filter circuit does not operate, the counting module stops operating, and the input signal of the single filter module is transmitted to the constant filter module as the output signal.
Preferably, in the single filtering module, when the delay time is too long, the clock signal generated by the frequency dividing module is used as the counting clock of the counting module.
Preferably, the constant filtering module is composed of a plurality of triggers f 0 、f 1 、……f n A plurality of exclusive-or gates X 1 、X 2 ……X n The trigger f is formed by n The input end of the flip-flop fn is used for receiving the signal output by the filter circuit, and the output end of the flip-flop fn is connected with the exclusive-or gate X n-1 Is connected to the first input terminal of the exclusive or gate X n-1 Is connected to the second input terminal of X n-2 The output end of the first power supply is connected; wherein the exclusive-OR gate X 1 For receiving the signal output by the filter circuit.
Preferably, the number of flip-flops and exclusive-or gates is determined by the filtered pulse width and the range of division ratios of the clock signals of the frequency division module.
Preferably, the clock signals provided by the frequency division module for the single filtering module and the constant filtering module comprise synchronous clock signals and asynchronous clock signals.
Preferably, the clock signal of the frequency dividing module designs the frequency dividing ratio according to the filtered pulse width.
Preferably, the output mode of the output signal of the digital filtering device includes forced pull-down, forced pull-up, maintaining the original signal state and maintaining the state when the filtering is terminated.
Setting a frequency division ratio of a clock signal according to the filtered pulse width in a frequency division module, and setting a filtering pulse range of a single filtering module and a constant filtering module according to the frequency division ratio of the clock signal;
transmitting a signal to be filtered to a single filtering module, controlling an enabling signal transmitting module to transmit an enabling signal to a filtering circuit, and starting a counting module to record an initial counting state when each group of the filtering circuits are enabled;
the control module is started, reads the current count value from the count module, calculates the filter termination time according to the filter duration, and selects the output mode of the digital filter device output signal;
the single filtering module is used for filtering long-time unstable signals in the signals and transmitting the filtered signals to the constant filtering module; the constant filtering module filters noise burrs in the received signals, outputs the filtered signals, and outputs the filtered signals according to an output mode set by the control module;
and when the count of each group of filter circuits reaches the ending time, turning off the enabling signals of the group of filter circuits.
Preferably, the output mode of the output signal includes forced pull-down, forced pull-up, maintaining the original signal state and maintaining the state when the filtering is terminated.
From the above technical scheme, the application has the following advantages:
the embodiment of the application provides a digital filtering device and a digital filtering method, wherein a whole filtering system is divided into a control module, a frequency division module, a single filtering module and a constant filtering module, and the range of a filtering pulse width is determined by adjusting the frequency division ratio of the frequency division module; the single filtering module is used for filtering unstable signals in a long time, and the common filtering module filters signal burrs, so that burrs generated by signals in the working process of the integrated circuit are filtered, and signal distortion is prevented.
The embodiment of the application has the following other advantages:
in the embodiment of the application, when the multi-group filter circuit of the single filter module does not operate, the counting module stops operating, and the input signal of the single filter module is used as the output signal to be transmitted to the normal filter module, so that the whole single filter module can be invalidated when not needed, thereby reducing the power consumption and improving the utilization rate of energy sources.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a circuit configuration diagram of a digital filtering apparatus and method according to an embodiment of the present application.
Fig. 2 is a block diagram of a single filtering module of a digital filtering apparatus and method according to an embodiment of the present application.
Fig. 3 is a block diagram of a constant filtering module of a digital filtering apparatus and method according to an embodiment of the present application.
Fig. 4 is a flowchart of a method for providing a digital filtering apparatus and method according to an embodiment of the present application.
Detailed Description
The embodiment of the application provides a digital filtering device and a digital filtering method, which are used for solving the technical problem that signal distortion exists because a signal can generate a burr phenomenon in the working process of an integrated circuit in the prior art.
In order to make the objects, features and advantages of the present application more comprehensible, the technical solutions in the embodiments of the present application are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
Referring to fig. 1, fig. 1 is a circuit diagram of a digital filtering apparatus and a method according to an embodiment of the application.
The application provides a digital filtering device which comprises a control module 1, a frequency division module 2, a single filtering module 3 and a constant filtering module 4, wherein the frequency division module is connected with the single filtering module;
the control module 1 is used for controlling the output mode of the output signal of the digital filter device; after filtering, the output mode of the output signal of the digital filtering device is controlled, so that the output mode of the output signal can be changed according to different requirements;
the frequency division module 2 is used for providing clock signals for the single filtering module 3 and the constant filtering module 4, and the single filtering module 3 and the constant filtering module 4 determine the width of the filtering pulse according to the clock signals; the single filtering module 3 and the constant filtering module 4 can perform the filtering operation only when the width of the filtering pulse is determined, and thus the width of the filtering pulse of the single filtering module 3 and the constant filtering module 4 can be controlled according to the control clock signal.
The single filtering module 3 is configured to filter the long-time unstable signal in the signal, thereby removing an invalid signal generated by the actions such as unstable power supply voltage and inherent problems of the circuit, and transmitting the filtered signal to the constant filtering module 4;
the constant filtering module 4 is used for filtering noise burrs in the received signals, guaranteeing the correctness and stability of the signals, and outputting the filtered signals.
As shown in fig. 2, as a preferred embodiment, the single filtering module 3 includes an enable signal sending module 5, a counting module 6, and a plurality of groups of filtering circuits 7, where the counting module 6 is connected to each group of filtering circuits 7;
the enabling signal sending module 5 is used for providing enabling signals for each group of filter circuits 7; only after receiving the enable signal, each group of filter circuits 7 is turned on and performs the filtering operation, so that the enable signal transmitting module 5 can control the on and off of each group of filter circuits 7.
The counting module 6 is configured to record an initial counting state when each group of filter circuits 7 is enabled, take an initial filtering count as a starting time of filtering, and close an enabling signal of each group of filter circuits 7 when the count of each group of filter circuits 7 reaches a termination time, so as to control a filtering duration of each group of filter circuits 7.
The multiple groups of filtering circuits 7 are used for filtering unstable signals for a long time and transmitting the filtered unstable signals to the constant filtering module 4.
As a preferred embodiment, when the multi-group filter circuit 7 is not operating, the counting module 6 stops operating and transmits the input signal of the single filtering module 3 as the output signal to the constant filtering module 4; when the multi-group filter circuit 7 does not operate, the counting module 6 is turned off, so that the circuit energy consumption is reduced, and the energy utilization rate is improved.
As a preferred embodiment, in the single filtering module 3, when the delay time is too long, the clock signal generated by the frequency dividing module 2 is used as the counting clock of the counting module 6, so that signal distortion caused by the too long delay time is avoided.
As shown in fig. 3, as a preferred embodiment, the constant filtering module 4 is composed of a plurality of flip-flops 9f 0 、f 1 … … fn and a plurality of exclusive-or gates 8X 1 、X 2 ……X n The trigger 9f is constituted by n For receiving the signal output by the filter circuit 7, the output of said flip-flop 9fn being connected to an exclusive or gate 8X n-1 Is connected to the first input terminal of the exclusive or gate 8X n-1 Is connected to the second input terminal of X n-2 The output end of the first power supply is connected; wherein the exclusive-OR gate 8X 1 For receiving the signal output by the filter circuit 7.
As a preferred embodiment, the number of flip-flops 9 and xor gates 8 is determined by the filtered pulse width and the range of division ratios of the clock signals of the frequency dividing module 2. The filtering range is determined by the pulse width and the frequency division ratio of clock signals, so that the number of the selected triggers 9 and the number of the exclusive-OR gates 8 are selected, the influence of the too small number on the filtering effect is avoided, and the too large number causes signal distortion.
As a preferred embodiment, the clock signals provided by the frequency dividing module 2 to the single filtering module 3 and the constant filtering module 4 include synchronous clock signals and asynchronous clock signals. If the filtering frequency bands of the single filtering module 3 and the constant filtering module 4 are required to be different, the asynchronous clock signal can be provided, so that the single filtering module 3 and the constant filtering module 4 finish filtering of different frequency bands.
As a preferred embodiment, the clock signal of the frequency dividing module 2 is designed with a frequency dividing ratio according to the filtered pulse width.
As a preferred embodiment, the output mode of the output signal of the digital filtering device includes forced pull-down, forced pull-up, maintaining the original signal state and maintaining the state when the filtering is terminated. So that the output signal can change the output mode according to different requirements, which makes the present filter circuit 7 suitable for most applications.
Example 2
Referring to fig. 4, fig. 4 is a flowchart of a method for providing a digital filtering apparatus and a method according to an embodiment of the application.
A digital filtering method, the method being based on a digital filtering device, comprising the steps of:
setting a frequency division ratio of a clock signal according to the filtered pulse width in the frequency division module 2, and setting the filtering pulse ranges of the single filtering module 3 and the constant filtering module 4 according to the frequency division ratio of the clock signal;
transmitting the signal to be filtered to the single filtering module 3, controlling the enabling signal transmitting module 5 to transmit the enabling signal to the filtering circuits 7, after receiving the enabling signal, conducting each group of the filtering circuits 7 and performing filtering operation, and starting the counting module 6 to record the initial counting state of each group of the filtering circuits 7 when enabled;
starting the control module 1, wherein the control module 1 reads the current count value from the counting module 6, calculates the filtering termination time according to the filtering duration, and selects the output mode of the output signal of the digital filtering device, wherein the output mode comprises forced pull-down, forced pull-up, original signal state maintenance and filtering termination time state maintenance;
the single filtering module 3 is used for filtering long-time unstable signals in the signals, removing invalid signals generated by actions such as unstable power supply voltage, inherent problems of circuits and the like, and transmitting the filtered signals to the constant filtering module 4; the constant filtering module 4 filters noise burrs in the received signals, ensures the correctness and stability of the signals, outputs the filtered signals, and outputs the filtered signals according to the output mode set by the control module 1.
When the count of each group of filter circuits 7 reaches the termination time, the enable signal of the group of filter circuits 7 is turned off, ending the filtering process.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (9)
1. The digital filtering device is characterized by comprising a control module, a frequency division module, a single filtering module and a constant filtering module;
the control module is used for calculating the filtering time and controlling the output mode of the output signal of the digital filtering device;
the frequency division module is used for providing clock signals for the single filtering module and the constant filtering module, and the single filtering module and the constant filtering module determine the width of the filtering pulse according to the clock signals;
the single filtering module is used for filtering long-time unstable signals in the signals and transmitting the filtered signals to the constant filtering module;
the constant filtering module is used for filtering noise burrs in the received signals and outputting the filtered signals;
the single filtering module comprises an enabling signal sending module, a counting module and a plurality of groups of filtering circuits, and the counting module is connected with each group of filtering circuits in the plurality of groups of filtering circuits;
the enabling signal sending module is used for providing enabling signals for each group of filter circuits;
the counting module is used for recording an initial counting state when each group of filter circuits are enabled, and closing enabling signals of each group of filter circuits when the counting of each group of filter circuits reaches the ending moment;
the multi-group filter circuit is used for filtering the unstable signals for a long time and transmitting the filtered unstable signals to the constant filter module.
2. The digital filter device according to claim 1, wherein the counting module stops operating when the plurality of sets of filter circuits are not operating, and transmits the input signal of the single filtering module as the output signal to the constant filtering module.
3. The digital filtering device according to claim 1, wherein in the single filtering module, when the delay time is too long, the clock signal generated by the frequency dividing module is used as the count clock of the counting module.
4. A digital filtering device according to claim 3, wherein said constant filtering module is formed by a plurality of flip-flops f 0 、f 1 、……f n A plurality of exclusive-or gates X 1 、X 2 ……X n The trigger f is formed by n For receiving the signal output by the filter circuit, the flip-flop f n Output of (2) and exclusive or gate X n-1 Is connected to the first input terminal of the exclusive or gate X n-1 Is connected to the second input terminal of X n-2 The output end of the first power supply is connected; wherein the exclusive-OR gate X 1 For receiving the signal output by the filter circuit.
5. The digital filter device according to claim 4, wherein the number of flip-flops and exclusive-or gates is determined by the pulse width of the filtering and the range of the frequency division ratio of the frequency division module.
6. The digital filter device according to claim 1, wherein the clock signals provided by the frequency dividing module to the single pass filter module and the constant filter module include synchronous clock signals and asynchronous clock signals.
7. The digital filter device according to claim 6, wherein the clock signal of the frequency dividing module is configured to design the frequency dividing ratio according to the filtered pulse width.
8. The digital filter device according to claim 7, wherein the output mode of the output signal of the digital filter device includes being forced to be pulled down, being forced to be pulled up, maintaining the original signal state, and maintaining the state when the filtering is terminated.
9. A digital filtering method based on a digital filtering device according to any of the previous claims 1-7, characterized in that it comprises the following steps:
setting a frequency division ratio of a clock signal according to the filtered pulse width in a frequency division module, and setting a filtering pulse range of a single filtering module and a constant filtering module according to the frequency division ratio of the clock signal;
transmitting a signal to be filtered to a single filtering module, controlling an enabling signal transmitting module to transmit an enabling signal to a filtering circuit, and starting a counting module to record an initial counting state when each group of the filtering circuits are enabled;
the control module is started, reads the current count value from the count module, calculates the filter termination time according to the filter duration, and selects the output mode of the digital filter device output signal;
the single filtering module is used for filtering long-time unstable signals in the signals and transmitting the filtered signals to the constant filtering module; the constant filtering module filters noise burrs in the received signals, outputs the filtered signals, and outputs the filtered signals according to an output mode set by the control module;
and when the count of each group of filter circuits reaches the ending time, turning off the enabling signals of the group of filter circuits.
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| CN201911368598.9A CN110995202B (en) | 2019-12-26 | 2019-12-26 | Digital filtering device and method |
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| US5563532A (en) * | 1994-01-24 | 1996-10-08 | Advanced Micro Devices, Inc. | Double filtering glitch eater for elimination of noise from signals on a SCSI bus |
| DE102005050307A1 (en) * | 2005-10-20 | 2007-04-26 | Rohde & Schwarz Gmbh & Co. Kg | Fixed filter state digital filter during invalid signal ranges in a digital filter cascade |
| CN104065361A (en) * | 2014-06-03 | 2014-09-24 | 北京空间机电研究所 | Serial cascade single-bit filter structure for eliminating burr signals |
| CN104518755A (en) * | 2013-09-27 | 2015-04-15 | 无锡华润微电子有限公司 | Digital circuit noise filter and digital filtering method |
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2019
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5563532A (en) * | 1994-01-24 | 1996-10-08 | Advanced Micro Devices, Inc. | Double filtering glitch eater for elimination of noise from signals on a SCSI bus |
| DE102005050307A1 (en) * | 2005-10-20 | 2007-04-26 | Rohde & Schwarz Gmbh & Co. Kg | Fixed filter state digital filter during invalid signal ranges in a digital filter cascade |
| CN104518755A (en) * | 2013-09-27 | 2015-04-15 | 无锡华润微电子有限公司 | Digital circuit noise filter and digital filtering method |
| CN104065361A (en) * | 2014-06-03 | 2014-09-24 | 北京空间机电研究所 | Serial cascade single-bit filter structure for eliminating burr signals |
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