CN110993621A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN110993621A CN110993621A CN201911272594.0A CN201911272594A CN110993621A CN 110993621 A CN110993621 A CN 110993621A CN 201911272594 A CN201911272594 A CN 201911272594A CN 110993621 A CN110993621 A CN 110993621A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate comprises a source drain layer manufacturing step, wherein the source drain layer comprises a lower blocking layer, a conducting layer and an upper blocking layer which are sequentially stacked from bottom to top, and the source drain layer manufacturing step comprises the following steps: lipophilic treatment of the upper barrier layer and fabrication of a photoresist layer. The invention changes the hydrophilicity of the upper barrier layer forming the source drain layer into lipophilicity, and can avoid the edge of the photoresist from tilting by increasing the adhesiveness between the upper barrier layer and the photoresist, thereby preventing the upper barrier layer from shrinking inwards during etching, effectively avoiding the conductive layer from being oxidized, avoiding developing new materials of the photoresist and purchasing new machines, and saving the production cost.
Description
Technical Field
The invention relates to the field of display, in particular to an array substrate and a manufacturing method thereof.
Background
As shown in fig. 1, a structural schematic diagram of a conventional back channel etching type array substrate 90 is provided, which includes an active layer 91 and a source drain layer 92 located on the active layer 91, where the structure of the source drain layer 92 generally adopts a sandwich structure of a lower barrier layer 921, a conductive layer 922, and an upper barrier layer 923 stacked in sequence from bottom to top, where the conductive layer 922 is preferably made of copper, the upper barrier layer 923 mainly prevents serious oxidation of the conductive layer caused by high temperature treatment and N2O treatment in subsequent SiOx film formation, and the lower barrier layer 921 also plays a role in preventing copper from diffusing into a channel of the array substrate. The upper barrier layer 923 is usually made of metal or alloy, but the adhesion between the upper barrier layer 923 and the photoresist 93 is poor, which causes the edges of the photoresist 93 and the upper barrier layer 923 to tilt up, and the tilting position of the photoresist 93 is etched during the etching of the upper barrier layer 923, resulting in the inward shrinkage of the upper barrier layer 923.
As shown in fig. 2, the schematic view of the array substrate 90 is shown in which the upper blocking layer 923 is shrunk during actual manufacturing, so that the conductive layer 922 cannot be effectively prevented from being oxidized. Currently, the industry usually adopts the method of replacing the photoresist 93 to solve this problem, but this method has high material cost of the photoresist 93 and large loss of productivity.
Disclosure of Invention
The invention aims to provide an array substrate and a manufacturing method thereof, which can prevent the edge of photoresist from tilting by increasing the adhesion between an upper blocking layer and the photoresist, thereby preventing the upper blocking layer from shrinking inwards during etching, effectively preventing a conductive layer from being oxidized, avoiding developing new materials of the photoresist and purchasing new machines, and saving the production cost.
In order to solve the above problems, the present invention provides a method for manufacturing an array substrate, including a step of manufacturing a source drain layer, where the source drain layer includes a lower barrier layer, a conductive layer, and an upper barrier layer, which are sequentially stacked from bottom to top, and the step of manufacturing the source drain layer includes:
the upper barrier layer is subjected to lipophilic treatment, and the hydrophilicity of the upper surface of the upper barrier layer is changed into lipophilicity or hydrophobicity by cleaning the upper barrier layer; and
and manufacturing a light resistance layer, wherein the light resistance layer is manufactured on the upper blocking layer in a mode of coating photoresist, and the light resistance layer is completely attached to the upper blocking layer.
Further, before the step of oleophilic treatment of the upper barrier layer, the method further comprises:
manufacturing a lower barrier layer;
manufacturing a conductive layer, and manufacturing the conductive layer on the lower barrier layer; and
and manufacturing an upper barrier layer on the conductive layer.
Further, before the step S3 of fabricating the source/drain layer, the method further includes:
manufacturing a substrate base plate; and
manufacturing a semiconductor layer, and manufacturing the semiconductor layer on the substrate; and manufacturing the lower barrier layer on the semiconductor layer.
Further, after the step of forming the photoresist layer, the method further comprises:
and patterning the photoresist layer, and etching the photoresist layer to form a patterned photoresist layer.
Further, after the step of fabricating the source/drain layer, the method further includes:
and manufacturing an active layer, and performing patterning and doping treatment by etching the semiconductor layer to manufacture the active layer.
Further, after the step of fabricating the active layer, the method further includes:
removing part of the light resistance layer, arranging a half mask plate and removing the light resistance layer at the half mask plate through dry etching;
manufacturing a source electrode and a drain electrode, and manufacturing a patterned source electrode and a patterned drain electrode by etching the source drain electrode layer; and
all the photoresist layer is removed, and all the photoresist layer is removed by lift-off.
Further, the material of the conductive layer includes Cu or Al.
Furthermore, the material of the lower barrier layer and the upper barrier layer comprises Mo, Ti or Mo alloy.
Further, the material of the semiconductor layer comprises IGZO, IZTO or IGZTO.
The invention also provides an array substrate which comprises a source drain layer, wherein the source drain layer comprises a lower blocking layer, a conducting layer and an upper blocking layer which are sequentially stacked from bottom to top; the conductive layer is arranged on the lower blocking layer; the upper blocking layer is arranged on the conducting layer, and the upper surface of the upper blocking layer is lipophilic.
The invention has the advantages that the hydrophilicity of the upper barrier layer forming the source drain layer is changed into lipophilicity or hydrophobicity, the adhesion between the upper barrier layer and the photoresist is increased, the edge of the photoresist is prevented from tilting, the upper barrier layer is prevented from shrinking inwards during etching, the conducting layer is effectively prevented from being oxidized, a new material of the photoresist is not required to be developed and a new machine is not required to be purchased, and the production cost can be saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly introduced below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic structural diagram of a conventional back channel etching type array substrate;
FIG. 2 is a schematic diagram of a prior art top barrier layer indented array substrate;
FIG. 3 is a flowchart of a step of fabricating a source/drain layer in an embodiment of the present invention;
FIG. 4 is a schematic diagram of the structure after the step of forming the photoresist layer is completed;
fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
fig. 6 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
The components in the figure are identified as follows:
1. a substrate base plate, 2, an active layer, 3, a lower barrier layer, 4, a source drain layer,
5. an upper barrier layer, 6, an insulating layer, 7, a planarization layer, 10, a photoresist layer,
20. a semiconductor layer, 40, a conductive layer, 41, a source electrode, 42, a drain electrode,
100. an array substrate.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 3, 4 and 5, in an embodiment of the present invention, a method for manufacturing an array substrate 100 is provided, including a step S3 of manufacturing a source/drain layer 4, where the source/drain layer 4 includes a lower blocking layer 3, a conductive layer 40 and an upper blocking layer 5, which are sequentially stacked from bottom to top, and the step S3 of manufacturing the source/drain layer 4 includes:
s34, lipophilic treatment is carried out on the upper barrier layer 5, and the hydrophilicity of the upper surface of the upper barrier layer 5 is changed into lipophilicity or hydrophobicity by cleaning the upper barrier layer; when clean water drops are used for testing on the upper barrier layer 5, the contact angle of clean water and the upper barrier layer 5 is 30-60 degrees when the upper barrier layer 5 is not subjected to lipophilic treatment; after the upper barrier layer 5 is subjected to lipophilic treatment, the contact angle of clean water and the upper barrier layer 5 is changed to 110-160 degrees; and
s35, manufacturing a photoresist layer 10, manufacturing the photoresist layer 10 on the upper barrier layer 5 in a photoresist coating mode, and completely attaching the photoresist layer 10 to the upper barrier layer 5. Fig. 4 is a structural diagram after completing the step S35 of forming the photoresist layer 10.
Increase can avoid the edge of photoresist to produce the perk through increasing barrier layer 5 and photoresist adhesion nature when coating photoresist to prevent to go up barrier layer 5 and produce the retraction when the etching, effectively avoid conducting layer 40 to be oxidized, avoid taking place the oxidation and cause the contact impedance increase, and need not develop the new material of photoresist and purchase new board, can practice thrift manufacturing cost.
Referring to fig. 3, in the present embodiment, before the step S34 of lipophilic processing of the upper barrier layer 5, the method further includes:
s31, manufacturing a lower barrier layer 3;
s32, manufacturing a conductive layer 40, and manufacturing the conductive layer 40 on the lower barrier layer 3; and
s33, forming an upper barrier layer 5, and forming the upper barrier layer 5 on the conductive layer 40.
Referring to fig. 4 and fig. 6, in the present embodiment, before the step S3 of fabricating the source/drain layer 4, the method further includes:
s1, manufacturing a substrate base plate 1; and
s2, forming a semiconductor layer 20, and forming the semiconductor layer 20 on the base substrate 1; the lower barrier layer 3 is fabricated on the semiconductor layer 20.
In this embodiment, after step S35, the method further includes:
s36, patterning the photoresist layer 10, and forming the patterned photoresist layer 10 by etching the photoresist layer 10.
In this embodiment, after the step S3 of manufacturing the source/drain layer 4, the method further includes:
and S4, manufacturing the active layer 2, and manufacturing the active layer 2 by etching the semiconductor layer 20, patterning and doping.
In this embodiment, after step S4, the method further includes:
s5, removing part of the light resistance layer 10, setting a half mask plate and removing the light resistance layer 10 at the half mask plate through dry etching;
s6, manufacturing a source electrode 41 and a drain electrode 42, and manufacturing a patterned source electrode 41 and a patterned drain electrode 42 by etching the source drain layer 4;
s7, the entire photoresist layer 10 is removed, and the entire photoresist layer 10 is removed by stripping.
In this embodiment, the material of the conductive layer 40 includes Cu or Al, preferably Cu.
In this embodiment, the material of the lower barrier layer 3 and the upper barrier layer 5 includes Mo, Ti, or Mo alloy.
In this embodiment, the material of the semiconductor layer 20 includes IGZO, IZTO, or IGZTO.
The verification result of an actual production line shows that when the upper blocking layer 5 is not subjected to lipophilic treatment before being coated with photoresist to prepare the photoresist layer 10, the upper blocking layer 5 is obviously retracted and the conductive layer 40 at the lower part is exposed; the upper blocking layer 5 increases the adhesion between the photoresist layer 10 and the upper blocking layer 5 after performing oleophilic treatment before coating the photoresist layer 10 to make the photoresist, and the upper blocking layer 5 does not shrink inward and forms a perfect protection for the lower conductive layer 40.
Referring to fig. 5, an array substrate 100 is further provided according to an embodiment of the present invention, and is manufactured by using the manufacturing method of the array substrate 100. The array substrate 100 includes a substrate 1, an active layer 2, an insulating layer 6, a source drain layer 4, and a planarization layer 7, which are sequentially stacked from bottom to top, where the source drain layer 4 includes a source electrode 41 and a drain electrode 42. As shown in fig. 4, the source/drain layer 4 includes a lower barrier layer 3, a conductive layer 40, and an upper barrier layer 5, which are sequentially stacked from bottom to top; the conductive layer 40 is arranged on the lower barrier layer 3; the upper barrier layer 5 is disposed on the conductive layer 40, and the upper surface of the upper barrier layer 5 is lipophilic.
In this embodiment, the material of the conductive layer 40 includes Cu or Al, preferably Cu.
In this embodiment, the material of the lower barrier layer 3 and the upper barrier layer 5 includes Mo, Ti, or Mo alloy.
In this embodiment, the active layer 2 is formed by etching the semiconductor layer 20, patterning the semiconductor layer 20, and doping the semiconductor layer 20, wherein the material of the semiconductor layer 20 includes IGZO, IZTO, or IGZTO.
It is understood that the array substrate 100 further includes a gate layer (not shown) disposed in the substrate 1 or on the active layer 2 to form a bottom gate or top gate structure.
The invention has the advantages that the hydrophilicity of the upper barrier layer 5 forming the source drain layer 4 is changed into lipophilicity or called hydrophobicity, and the adhesion between the upper barrier layer 5 and the photoresist is increased to avoid the tilting of the edge of the photoresist, so that the upper barrier layer 5 is prevented from shrinking inwards during etching, the conductive layer 40 is effectively prevented from being oxidized, the contact impedance is prevented from being increased due to oxidation, and the development of new materials of the photoresist and the purchase of new machines are not needed, so that the production cost can be saved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The manufacturing method of the array substrate is characterized by comprising a source drain layer manufacturing step, wherein the source drain layer comprises a lower blocking layer, a conducting layer and an upper blocking layer which are sequentially stacked from bottom to top, and the source drain layer manufacturing step comprises the following steps:
the upper barrier layer is subjected to oleophilic treatment, and the upper barrier layer is cleaned to change the hydrophilicity of the upper surface of the upper barrier layer into oleophilic property; and
and manufacturing a light resistance layer, wherein the light resistance layer is manufactured on the upper blocking layer in a mode of coating photoresist, and the light resistance layer is completely attached to the upper blocking layer.
2. The method for manufacturing the array substrate according to claim 1, further comprising, before the step of oleophilic-treating the upper barrier layer:
manufacturing a lower barrier layer;
manufacturing a conductive layer, and manufacturing the conductive layer on the lower barrier layer; and
and manufacturing an upper barrier layer on the conductive layer.
3. The method for manufacturing the array substrate according to claim 1, further comprising, before the step of manufacturing the source and drain layers:
manufacturing a substrate base plate; and
manufacturing a semiconductor layer, and manufacturing the semiconductor layer on the substrate; and manufacturing the lower barrier layer on the semiconductor layer.
4. The method for fabricating the array substrate according to claim 1, further comprising, after the step of fabricating the photoresist layer:
and patterning the photoresist layer, and etching the photoresist layer to form a patterned photoresist layer.
5. The method for fabricating an array substrate according to claim 4, further comprising, after the step of fabricating data traces:
and manufacturing an active layer, and performing patterning and doping treatment by etching the semiconductor layer to manufacture the active layer.
6. The method for manufacturing the array substrate according to claim 5, further comprising, after the step of manufacturing the active layer:
removing part of the light resistance layer, arranging a half mask plate and removing the light resistance layer at the half mask plate through dry etching;
manufacturing a source electrode and a drain electrode, and manufacturing a patterned source electrode and a patterned drain electrode by etching the source drain electrode layer; and
all the photoresist layer is removed, and all the photoresist layer is removed by lift-off.
7. The method of claim 1, wherein the conductive layer comprises Cu or Al.
8. The method of claim 1, wherein the material of the lower barrier layer and the upper barrier layer comprises Mo, Ti or a Mo alloy.
9. The method of claim 1, wherein the semiconductor layer is made of IGZO, IZTO or IGZTO.
10. An array substrate, comprising a source drain layer, wherein the source drain layer comprises:
a lower barrier layer;
a conductive layer disposed on the lower barrier layer; and
and the upper blocking layer is arranged on the conductive layer, and the upper surface of the upper blocking layer is lipophilic.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111650791A (en) * | 2020-06-04 | 2020-09-11 | Tcl华星光电技术有限公司 | Array substrate and preparation method thereof |
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Application publication date: 20200410 |