CN110993562B - Preparation method of thin film device based on full silicon-based mask - Google Patents
Preparation method of thin film device based on full silicon-based mask Download PDFInfo
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- CN110993562B CN110993562B CN201911084206.6A CN201911084206A CN110993562B CN 110993562 B CN110993562 B CN 110993562B CN 201911084206 A CN201911084206 A CN 201911084206A CN 110993562 B CN110993562 B CN 110993562B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The utility model belongs to the technical field of semiconductor processes, and particularly relates to a preparation method of a thin film device based on an all-silicon-based mask. The method comprises the following steps: designing and preparing a silicon-based mask, wherein the silicon-based mask comprises a film plating mask and an etching mask, and an alignment mark is designed on the mask; preparing a device substrate, including selecting materials of the substrate, cleaning and preprocessing; preparing a semiconductor film on a device substrate; and aligning the semiconductor film material with the corresponding mask plate by using a high-precision alignment platform device, and preparing the device on the semiconductor film. The thin film device is prepared by the whole-course silicon-based mask, so that the etching of the device is pollution-free, the cost and the process are simple, and the silicon-based mask has the advantages of high reusability, high precision, high design freedom flexibility and the like, and can realize the integration of the thin film device.
Description
Technical Field
The utility model belongs to the technical field of semiconductor processes, and particularly relates to a preparation method of a thin film device based on an all-silicon-based mask.
Background
Since two-dimensional layered films, organic film materials and the like are developed in the technical field of microelectronics, the performance of the film device is reduced and the integration of the film device is limited due to the change of the structure and the performance of the film material caused by the traditional device process (such as developing solution, lift-off, pattern etching and the like in the photoetching process). In view of this, the technical staff developed a mask without lithography technology (polymer, metal mask, etc.) for thin film device preparation, instead of photolithography and film plating processes in the process to reduce the damage of thin film materials, but the application of the polymer mask in the semiconductor device process was limited due to the defects of intolerance to high temperature, short service life, extremely low precision of metal mask, high cost, etc.
Silicon-based Masks (Si-SMs) have been used in thin film transistor device fabrication due to their high precision, long service life, and high temperature resistance. However, the method is only used for the deposition preparation of metal or organic matters in the thin film device at present, but is not applied to the whole process, and although the method can reduce the pollution of the thin film to a certain extent, the pattern etching can not basically reduce the pollution to the minimum; in addition, for device array fabrication of large area thin films, etching with silicon-based masks is not involved. Accordingly, there is a need for improvements in the fabrication of existing thin film devices that eliminate the above-described problems.
Disclosure of Invention
Aiming at the defects of the existing mask film device preparation process, the utility model aims to provide a preparation method of a film device based on a full silicon-based mask, which has the advantages of no pollution, low cost and simple process and can realize the integration of the film device.
The utility model provides a preparation method of a thin film device based on an all-silicon-based mask, which comprises the following specific steps:
(1) And designing and preparing corresponding silicon-based masks (such as coating films, etching masks and the like).
The corresponding silicon-based mask, such as an evaporation mask and an etching mask, is designed and prepared according to the size and the position of the thin film, the type of the transistor device and the like and the evaporation or etching materials corresponding to the thin film. The specific design steps can refer to the utility model patent of a split pattern structure of a high-precision silicon-based through hole mask (CN 109188858A) and a preparation method of an ultra-high-precision silicon-based through hole pattern structure (CN 105261588A).
The front surface pattern of the silicon-based mask plate comprises at least one pattern and an alignment mark which are required in the processes of evaporation, etching and the like, and the alignment mark is favorable for accurate alignment of a plurality of mask plates.
Preferably, the alignment mark is designed around or in the middle of the whole mask, is in a cross shape, a T shape or other English letters or other regular patterns capable of completing all-round accurate alignment at one time, and the size of the alignment mark can be according to the pattern size of the mask.
(2) Preparing a device substrate, including selecting materials of the substrate, cleaning and preprocessing.
The substrate with different materials and the substrate with different types are selected according to the type of the device, the pollution caused by the processing or other influences of the substrate is removed through cleaning, and the adhesion between the film material and the substrate material or the smoothness of the substrate is improved through pretreatment.
Depending on the transistor type, a different substrate is selected, for example any one of silicon wafer, polymer, plastic, glass, metal, paper substrate; the cleaning can be carried out by using organic solvents, acid, deionized water and the like; the pretreatment can be baking or heating in an oven or a constant temperature heating table, plasma treatment or spin coating of photoresist coating.
(3) And preparing a semiconductor film on the device substrate.
The material of the film can be one of semiconductor films such as graphene, boron nitride, black phosphorus, two-dimensional transition metal chalcogenide (2 DTMDs), oxide or organic matters.
Preferably, the semiconductor film can be prepared by Chemical Vapor Deposition (CVD) growth (with larger area) or by mechanical stripping and film transfer (with smaller area).
(4) And (3) aligning the thin film material with a corresponding mask plate by using a high-precision alignment platform device, and preparing the thin film device on the semiconductor thin film material.
The thin film device can be a single or a plurality of top-bottom gate transistors, inverters, light emitting diodes or corresponding arrays, etc.
Preferably, the thin film material is aligned with the corresponding mask plate by using a high-precision alignment platform device through an alignment mark. The alignment process needs to adopt an alignment device, and reference can be made to the utility model patent of a micro device (CN 203932033U) for aligning a precise mask and a device (CN 109065493A) for assisting in precisely aligning the mask with a sample, wherein the two devices can realize high-precision alignment of the mask and a film material.
Preferably, the thin film device can be prepared by growing metal or organic matters or dielectric layers by using Magnetron Sputtering (MS), electron Beam Evaporation (EBE), organic evaporation coating table (OEC), atomic layer deposition equipment (ALD) and the like, and etching thin film materials and other materials by using reactive plasma etching (RIE), inductively Coupled Plasma Etching (ICPE) and the like.
The preparation method of the thin film device based on the full silicon-based mask plate has the advantages of no pollution, low preparation cost, high flexibility of design and the like, and the silicon-based mask plate can be reused, is high in alignment accuracy, and can meet the requirements of various fields on the preparation of the thin film device.
Drawings
FIG. 1 is a 10X 10 MoS of example 1 of the present utility model 2 4 silicon-based mask front patterns used for preparing the top grid transistor array. Wherein (a) is a Source/Drain electrode metal vapor deposition Mask (Source/Drain-Mask), (b) is a Gate electrode metal vapor deposition Mask (Gate-Mask), (c) and (d) are MoS at reserved channels 2 Etching Mask (horizontal Etching Mask Etching1-Mask, vertical Etching Mask Etching 2-Mask); the two small squares at the four corners are alignment marks.
FIG. 2 is a full 10×10 MoS final synthesis of 4 reticles in example 1 of the present utility model 2 Top gate transistor array front view.
FIG. 3 shows the MoS of example 1 of the present utility model using 4 reticles 2 Thin film top gate transistor array optical microscopy.
Fig. 4 shows a 5×5OLED array according to example 2 of the present utility model. Wherein (a) is an arrangement of three primary colors of luminescent material, and (b) is a structure of a single pixel.
Reference numerals 205, 204, 203 in the figure are sequentially red, green and blue three primary color luminescent materials; 200 The anode, hole injection layer, hole transport layer, light emitting layer (blue, green, red), hole blocking layer, electron transport layer, and cathode are sequentially shown as 201, 202, 203, 204, 205, 206, 207, 208, and 209.
Detailed Description
The present utility model will be described in further detail with reference to the accompanying drawings and detailed description. The accompanying drawings are included to provide a further understanding of the utility model. Specific embodiments of the present utility model and related drawings are shown in the drawings to illustrate the method of fabricating a thin film transistor device using an all-silicon-based mask in accordance with the present utility model. The specific embodiments described herein are to be considered in an illustrative sense only and are not intended to limit the scope of the utility model.
Example 1
In this embodiment, a silicon-based mask is used to prepare a 10×10 MoS in the entire process 2 Top gate transistor array: designing 1 block of 10 multiplied by 10 source drain electrode metal deposition mask plate and 2 blocks of MoS at reserved channel 2 The front design patterns of the etching mask plate and 1 top gate electrode deposition mask plate are shown in figure 1, two small diagonal squares are added at four top corners of the whole mask plate to serve as alignment marks for metal deposition and etching, and other design methods can refer to utility models patent 'a high-precision silicon-based through hole mask plate split pattern structure' (CN 109188858A) and 'a preparation method of an ultra-high-precision silicon-based through hole pattern structure' (CN 105261588A); the preparation method adopts processes such as pattern optimization and deep silicon dry etching, and the specific preparation method can refer to patent preparation method of ultra-high precision silicon-based through hole pattern structure (CN 105261588A), thereby obtaining 1 set of MoS with high precision and longer service life 2 Silicon-based through hole pattern Mask prepared by top Gate transistor array, in particular to Source/Drain metal electrode evaporation Mask (Source/Drain-Mask), gate electrode metal evaporation Mask (Gate-Mask) and 2 MoS at reserved channel 2 Is used for Etching Mask plates (a transverse Etching Mask plate Etching1-Mask and a vertical Etching Mask plate Etching 2-Mask).
By P-type<100>The Si sheet is used as a transistor array substrate, and is respectively ultrasonically cleaned by acetone, isopropanol, deionized water and the like for 5min, and N is used 2 Drying, namely placing the substrate on a heating platform at 100 ℃ to bake for 1min, and further drying the silicon wafer to increase the adhesive force of the film material; in MoO 3 And sulfur powder as raw materials, moO is added 3 Powder (Alfa Aesar, 99.95%) and sulfur powder (Alfa Aesar, 99.999%) were placed in ceramic crucibles, respectively, and placed in high temperature I and low temperature II regions, respectively, of a CVD tube furnace, the sulfur powder crucible being at a distance MoO 3 About 30cm, the Si chip was placed face down in a CVD furnace tube containing MoO 3 The crucible of the powder is provided with sulfur powder and MoO 3 The growth temperature of the powder is 180 ℃ and 650 ℃ respectively, and the whole vulcanization process lasts for about 10min under normal pressure to obtain the wafer-level MoS 2 A film material.
A top gate transistor array is prepared by using a mask plate, and the preparation process is as follows: source/Drain-Mask and MoS grown in advance 2 The Si sheet of the film is attached by an alignment platform, and then is placed in an EBE evaporation cavity to evaporate a 35nm gold (Au) source-drain electrode; the alignment marks of the Etching1-Mask and the Etching2-Mask are aligned with the four corner alignment marks of the Si sheet with the good source and drain electrodes by using an alignment device respectively, and an alignment platform and an alignment method can adopt patents of a micro device for aligning a precise Mask (CN 203932033U) and a device for assisting precise alignment of a hard through hole Mask and a sample (CN 109065493A), and are placed in RIE for Etching for 2 times vertically and horizontally to reserve MoS at a channel 2 The thin film is etched for 2 times to realize that the channels of the transistors are independent; after 2 times of etching, the wafer is put into ALD to grow 25nm Al 2 O 3 A gate dielectric layer; then using Gate-Mask and growing Al 2 O 3 The film is aligned by the alignment mark and then put into an evaporation cavity to evaporate 35nm Au gate electrode; the MoS is obtained through silicon-based mask alignment, 2 times of vapor deposition and 2 times of etching 2 Thin film top gate transistor array, and MoS prepared therefrom 2 An optical microscope image of the thin film top gate transistor array is shown in fig. 3.
Example 2
In this embodiment, a silicon-based mask is used to prepare a 5×5 high-definition Organic Light Emitting Diode (OLED) display pixel array in the whole process: designing 1 evaporation mask plate with 5 multiplied by 5 array and 3 evaporation mask plates with luminous materials of red and yellow Lan Jise, wherein the front design graph synthesized by the 3 evaporation mask plates with the luminous materials of primary colors is shown in fig. 4 (a), a T-shaped symbol is added in the middle of the whole mask plate as an alignment mark, and the rest design methods can refer to the utility model patent of a split graph structure of a high-precision silicon-based through hole mask plate (CN 109188858A) and a preparation method of an ultra-high-precision silicon-based through hole graph structure (CN 105261588A); the preparation method is characterized in that the preparation method comprises the steps of adopting processes such as pattern optimization and deep silicon dry etching, and the like, and the specific preparation method can refer to patent preparation method of ultra-high precision silicon-based through hole pattern structure (CN 105261588A), so that 1 set of high-definition OLED pixel array Mask is obtained, specifically a cathode-anode evaporation Mask (Pad-Mask, front view is square), red, green and Blue luminescent material evaporation masks (Red-Mask, green-Mask and Blue-Mask), and the front view patterns of the Mask are respectively 205, 204 and 203 in square.
Taking polyethylene terephthalate (PET) as an OLED substrate, respectively ultrasonically cleaning the OLED substrate with acetone, isopropanol, deionized water and the like for 5min, and using N 2 And (3) drying, namely placing the substrate on a gumming machine, spin-coating a layer of SU-8 epoxy resin photoresist with the thickness of 0.5um, and drying to improve the smoothness of the PET substrate.
Preparing a high-definition OLED pixel array by using a mask, wherein each OLED pixel structure diagram is shown as 4 (b), indium Tin Oxide (ITO) is used as a target, and a 150nm ITO thin layer is sputtered at room temperature by using magnetron Sputtering (SP), so that a PET/ITO thin film layer 200 is obtained as an anode; the alignment mark ' T ' in the Pad-Mask is aligned with ' T ' in the PET/ITO film layer 200 which is grown in advance, an alignment platform and an alignment method can adopt a miniature device (CN 203932033U) for aligning a precise Mask and a device (CN 109065493A) for assisting precise alignment of the hard through hole Mask and a sample, and then the device and the method are placed in OEC to respectively and sequentially evaporate 20nm 4,4' -cyclohexylbis [ N, N-bis (4-methylphenyl) aniline]/MoO 3 (TAPC:MoO 3 =50:1) thin film layer 201 as hole injection layer, 20nm 4,4' -cyclohexylbis [ N, N-bis (4-methylphenyl) aniline]The (TAPC) thin film layer 202 serves as a hole transport layer; then the Red-Mask, green-Mask and Blue-Mask are respectively and sequentially connected with TAPC: moO on the PET substrate through an alignment platform device 3 The T-shape alignment and OEC evaporation of 25nm of dichloromethane (DCM, red luminescent material) 205, 4- (2-ethylamino) benzene-1, 2-diphenol (DA, green luminescent material) 204, 2P-Nme2 (blue luminescent material) 203 on the film layer, the three-color front-side layout is shown as 4 (b); after alignment of "T" on Pad-Mask and "T" on PET after plating of luminescent material, 50nm of 1,3, 5-tris (1-phenyl-1H-benzimidazol-2-yl) benzene (TPBI) film 206, 20nm of N, N-diphenyl-N, N-bis (4-methylphenyl) -4,4- -The 5 x 5 Organic Light Emitting Diode (OLED) display pixel array can be prepared by using the biphenyl diamine (TPD) film 207 and the 20nm 8-quinolyl alcohol-lithium (Liq) film 208 as a hole blocking layer, an electron transport layer and an electron transport layer respectively, using a metal Al layer 209 grown by SP as a cathode, and coating the films.
Claims (2)
1. A preparation method of a thin film device based on an all-silicon-based mask plate is characterized by comprising the following specific steps:
(1) Designing and preparing a silicon-based mask plate,
designing and preparing a corresponding silicon-based mask plate according to the size and the position of the thin film, the type of the transistor device and the evaporation or etching material corresponding to the transistor device; the silicon-based mask comprises a film plating mask and an etching mask;
the front surface pattern of the silicon-based mask plate comprises a pattern required in the evaporation and etching processes and an alignment mark for accurately aligning a plurality of mask plates when the mask plates are used;
(2) Preparing a device substrate, including selecting materials of the substrate, cleaning and preprocessing;
(3) Preparing a semiconductor film on a device substrate;
(4) Aligning the semiconductor film with a corresponding mask plate by using a high-precision alignment platform device, and preparing a film device on the semiconductor film;
the alignment mark in the step (1) is designed around or in the middle of the whole mask pattern, the shape is 1-4 crisscross, T-shaped or English letters, and the size of the alignment mark is determined according to the minimum precision of the mask;
the substrate in the step (2) is selected from any one of silicon chips, polymers, plastics, glass, metal and paper base materials; the cleaning is to remove pollution caused by processing or other influences of a substrate by adopting an organic solvent, acid, deionized water or ultrasound, and the pretreatment is to increase the adhesiveness between a semiconductor film and a substrate or the smoothness of the substrate by baking or heating a constant-temperature heating table, plasma treatment or spin coating photoresist coating mode;
the semiconductor film in the step (3) is made of a material selected from graphene, boron nitride, black phosphorus and two-dimensional transition metal chalcogenide;
the alignment of the semiconductor film and the corresponding mask in the step (4) is performed through the alignment marks around or in the middle under a microscope; the thin film device is a single or a plurality of top-bottom grid transistors and inverters; the method for preparing the thin film device is to grow a metal or dielectric layer by magnetron sputtering, electron beam evaporation or atomic layer deposition, and etch the semiconductor thin film by adopting a reactive plasma etching method or an inductively coupled plasma etching method.
2. The method of manufacturing a thin film device according to claim 1, wherein the semiconductor thin film manufactured in the step (3) is manufactured by chemical vapor deposition growth or by mechanical lift-off or thin film transfer.
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