CN110993562A - Preparation method of thin film device based on all-silicon-based mask - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention belongs to the technical field of semiconductor processes, and particularly relates to a preparation method of a thin film device based on a full-silicon-based mask. The method comprises the following steps: designing and preparing a silicon-based mask, wherein the silicon-based mask comprises a film coating mask and an etching mask, and an alignment mark is designed on the mask; preparing a device substrate, including material selection, cleaning and pretreatment of the substrate; preparing a semiconductor film on a device substrate; and aligning the semiconductor film material with a corresponding mask by using a high-precision alignment platform device, and preparing a device on the semiconductor film. According to the invention, the thin film device is prepared through the whole silicon-based mask plate, so that the device etching is pollution-free, the cost and the process are simple, the silicon-based mask plate has the advantages of higher reusability, high precision, high design freedom and flexibility and the like, and the integration of the thin film device can be realized.
Description
Technical Field
The invention belongs to the technical field of semiconductor processes, and particularly relates to a preparation method of a thin film device based on a full-silicon-based mask.
Background
Since the development of two-dimensional layered thin films, organic thin film materials and the like in the field of microelectronic technology processes, the performance of thin film devices is reduced and the integration of the thin film devices is limited due to the change of the structure and the performance of the thin film materials caused by the traditional device processes (such as developing solution, lift-off, pattern etching and the like in the photoetching process). In view of this, technicians have developed a mask (polymer, metal mask, etc.) without lithography technology for thin film device fabrication to replace lithography and coating processes in the process to reduce damage of thin film materials, but the polymer mask has disadvantages of low temperature resistance, short service life, extremely low precision and high cost of the metal mask, and thus limits the application of the polymer mask in the semiconductor device process.
Silicon-based Masks (Si-SMs) have been used in the fabrication of thin film transistor devices due to their high precision, long service life, and high temperature resistance. However, the metal or organic deposition preparation in the thin film device is only used at present, and is not applied to the whole process, and although the pollution of the thin film can be reduced to a certain extent, the pollution is not reduced to the minimum in nature by the pattern etching; in addition, for the preparation of a device array with a large-area thin film, silicon-based mask etching is not involved. Therefore, there is a need for improvements in existing thin film device fabrication that eliminate the above-described problems.
Disclosure of Invention
Aiming at the defects of the existing preparation process of the mask film device, the invention aims to provide a preparation method of the film device based on the all-silicon-based mask, which has the advantages of no pollution, low cost and simple process and can realize the integration of the film device.
The invention provides a preparation method of a film device based on a full silicon-based mask, which comprises the following specific steps.
(1) Designing and preparing corresponding silicon-based mask (such as coating film, etching mask, etc.)
Designing and preparing a corresponding silicon-based mask plate such as an evaporation mask plate and an etching mask plate according to the size and the position of the thin film, the type of a transistor device and the like and a corresponding evaporation or etching material; the specific design steps can refer to the invention patents of a high-precision silicon-based through hole mask split graphic structure (CN 109188858A) and a preparation method of an ultra-high precision silicon-based through hole graphic structure (CN 105261588A);
the front pattern of the silicon-based mask comprises at least one pattern and an alignment mark required in the processes of evaporation, etching and the like, and the alignment mark is favorable for accurate alignment of the multiple masks;
preferably, the alignment mark is designed around or in the middle of the whole mask, is in the shape of a cross, a T or other English letters or other regular patterns capable of completing all-around accurate alignment at one time, and the size of the alignment mark can be according to the size of the patterns of the mask.
(2) Preparing device substrate, including selecting, cleaning and pretreating substrate
Selecting substrates of different materials and different types of bases according to the types of devices, removing pollution caused by the substrates in processing or other influences through cleaning, and increasing the adhesion between the film material and the base material or the smoothness of the bases through pretreatment;
selecting different substrates according to the type of the transistor, such as any one of silicon wafers, polymers, plastics, glass, metal and paper substrates; the cleaning can be carried out by ultrasonic cleaning with organic solvent, acid, deionized water and the like; the pretreatment can be baking or heating in an oven or a constant temperature heating table, plasma treatment or spin coating of photoresist.
(3) Preparation of semiconductor thin film on device substrate
The material of the film can be one of semiconductor films such as graphene, boron nitride, black phosphorus, two-dimensional transition metal chalcogenide (2 DTMDs), oxide or organic matter and the like;
preferably, the semiconductor film can be grown by Chemical Vapor Deposition (CVD) (with a large area) or can be prepared by mechanical stripping and film transfer (with a small area).
(4) Aligning the thin film material with a corresponding mask plate by using a high-precision alignment platform device, and preparing a thin film device on the semiconductor thin film material;
the thin film device can be a single or a plurality of top and bottom grid transistors, inverters, light emitting diodes or corresponding arrays and the like;
preferably, the alignment of the film material and the corresponding mask is performed by using a high-precision alignment platform device through an alignment mark; the alignment device is needed in the alignment process, and reference can be made to the utility model patent of miniature device for aligning the precise mask (CN 203932033U) and device for assisting the precise alignment of the hard through hole mask and the sample (CN 109065493A), and the two devices can realize the high-precision alignment of the mask and the thin film material;
preferably, the thin film device can be prepared by growing a metal or organic substance or a dielectric layer by Magnetron Sputtering (MS), Electron Beam Evaporation (EBE), Organic Evaporation Coating (OEC), Atomic Layer Deposition (ALD), etc., and etching a thin film material and other materials by reactive plasma etching (RIE), Inductively Coupled Plasma Etching (ICPE), etc.
The method for preparing the thin film device based on the all-silicon-based mask plate has the advantages of no pollution of the device, low preparation cost, high design freedom and flexibility and the like, and the silicon-based mask plate can be repeatedly used and is aligned with high precision, so that the requirements of various fields on the preparation of the thin film device can be met.
Drawings
FIG. 1 shows a MoS of 10X 10 in example 1 of the present invention2And 4 silicon-based mask front patterns used for preparing the top gate transistor array. Wherein, (a) is Source/Drain electrode metal evaporation Mask (Source/Drain-Mask), (b) is Gate electrode metal evaporation Mask (Gate-Mask), (c) and (d) are MoS at reserved channel2Etching Mask (horizontal Etching Mask 1-Mask, vertical Etching Mask 2-Mask); two small squares at the four corners are alignment marks.
FIG. 2 shows the present inventionThe final synthesis of a full 10 × 10 MoS with 4 masks in example 12A top gate transistor array.
FIG. 3 shows MoS prepared using 4 masks in example 1 of the present invention2Thin film top gate transistor array optical microscopy pictures.
FIG. 4 shows a 5X 5 OLED array in example 2 of the present invention. Wherein, (a) is the arrangement of three primary colors of the luminescent material, and (b) is the structure of a single pixel.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The invention is illustrated in the accompanying drawings by way of example and with reference to the accompanying figures, which are intended to explain the method of fabricating a thin film transistor device using an all silicon-based reticle of the invention. The specific embodiments described herein are merely illustrative of the present invention and do not limit the scope of the invention.
Example 1
In this embodiment, a silicon-based mask is used to prepare a 10 × 10 MoS in a whole process2Top-gate transistor array: designing 1 10 multiplied by 10 source-drain electrode metal deposition mask and 2 MoS reserved channels2The front design patterns of the etching mask plate and the 1 top gate electrode deposition mask plate are shown in figure 1, two small diagonal squares are added at four top corners of the whole mask plate to serve as alignment marks for metal deposition and etching, and other design methods can refer to the invention patents of a high-precision silicon-based through hole mask plate split pattern structure (CN 109188858A) and a preparation method of an ultra-high precision silicon-based through hole pattern structure (CN 105261588A); the silicon-based ultra-high-precision through hole pattern is prepared by adopting processes such as pattern optimization and deep silicon dry etching, and the specific manufacturing method can refer to patent' ultra-high-precision silicon-based through hole patternMethod for preparing Structure (CN 105261588A), thereby obtaining 1 set of MoS with high precision and long service life2A silicon-based through hole pattern Mask prepared by a top Gate transistor array is specifically a Source/Drain metal electrode evaporation Mask (Source/Drain-Mask), a Gate electrode metal evaporation Mask (Gate-Mask) and 2 MoS (MoS) blocks at reserved channels2Etching masks (lateral Etching masks 1-Mask, vertical Etching masks 2-Mask).
In P type<100>Using Si wafer as transistor array substrate, ultrasonic cleaning with acetone, isopropanol, deionized water, etc. for 5min, and cleaning with N2Drying, namely baking the substrate on a heating platform at 100 ℃ for 1min, and further drying the silicon wafer to increase the adhesive force of the thin film material; with MoO3And sulfur powder as raw material, adding MoO3Respectively placing powder (Alfa Aesar, 99.95%) and sulfur powder (Alfa Aesar, 99.999%) in ceramic crucible, and placing them in high-temperature zone I and low-temperature zone II in CVD tube furnace, wherein the sulfur powder crucible is separated from MoO3About 30cm, the Si piece is placed face down in the CVD furnace tube and contains MoO3Sulfur powder and MoO are arranged on a powder crucible3The growth temperature of the powder is 180 ℃ and 650 ℃, respectively, the whole vulcanization process is continued for about 10min under normal pressure, and the wafer-level MoS is obtained2A film material.
The top gate transistor array is prepared by using a mask plate, and the preparation process is as follows: the Source/Drain-Mask and the MoS grown in advance2Attaching the Si sheet of the film by using an alignment platform, and then placing the film in an EBE evaporation chamber for evaporating a 35nm gold (Au) source drain electrode; alignment marks of the Etching1-Mask and the Etching2-Mask are respectively aligned with four corner alignment marks of a Si sheet with a good source and drain electrode by an alignment device, and an alignment platform and an alignment method of the alignment platform can adopt patents of a micro device (CN 203932033U) for aligning a precise Mask and a device (CN 109065493A) for assisting the precise alignment of the hard through hole Mask and a sample, and are placed in RIE for vertical and horizontal 2-time Etching to reserve MoS at a channel2Etching the film for 2 times to realize independence of each transistor channel; after 2 times of etching, the wafer was placed in ALD to grow 25nm Al2O3A gate dielectric layer; reuse ofGate-Mask and growing Al2O3After the alignment of the wafer is carried out through the alignment mark, putting the wafer into an evaporation cavity for evaporating a 35nm Au gate electrode; obtaining MoS through silicon-based mask alignment, 2 times of evaporation and 2 times of etching2Thin film top gate transistor array, MoS prepared thereby2An optical microscope photograph of a thin film top gate transistor array is shown in figure 3.
Example 2
In this embodiment, a 5 × 5 high-definition Organic Light Emitting Diode (OLED) display pixel array is prepared in the whole process by using a silicon-based mask: designing 1 evaporation mask plate with 5 multiplied by 5 array and 3 evaporation mask plates with red, yellow and blue primary colors of luminescent materials, wherein the front design pattern synthesized by the 3 evaporation mask plates with the primary colors of the luminescent materials is shown in fig. 4(a), a T-shaped symbol is added in the middle of the whole mask plate to be used as an alignment mark, and the rest design methods can refer to invention patents of a high-precision silicon-based through hole mask plate split pattern structure (CN 109188858A) and a preparation method of an ultra-high precision silicon-based through hole pattern structure (CN 105261588A); the Mask is prepared by adopting processes such as pattern optimization and deep silicon dry etching, and the specific manufacturing method can refer to a patent 'preparation method of an ultra-high precision silicon-based through hole pattern structure' (CN 105261588A), so that 1 set of high-definition OLED pixel array Mask is obtained, specifically, a cathode-anode evaporation Mask (a Pad-Mask, a front view is square), a Red, Green and Blue luminescent material evaporation Mask (Red-Mask, Green-Mask and Blue-Mask, and front patterns of the Red-Mask, Green-Mask and Blue-Mask are small squares of 205, 204 and 203 respectively).
Taking polyethylene terephthalate (PET) as OLED substrate, ultrasonic cleaning with acetone, isopropanol, deionized water, etc. for 5min, and cleaning with N2And drying, namely placing the substrate on a glue spreader, spin-coating a layer of SU-8 epoxy resin photoresist of 0.5um, and then drying to improve the smoothness of the PET substrate.
Preparing a high-definition OLED pixel array by using a mask, wherein the structure diagram of each OLED pixel is shown as 4 (b), Indium Tin Oxide (ITO) is used as a target material, and a 150nm ITO thin layer is sputtered at room temperature by magnetron Sputtering (SP) to obtain a PET/ITO thin layer 200 as an anode; the alignment mark 'T' in Pad-Mask is aligned with the previously grown PET/IThe alignment platform and alignment method for the "T" alignment in the TO thin film layer 200 can be implemented by a micro device for precise mask alignment (CN 203932033U) and a device for assisting precise alignment between the hard via mask and the sample (CN 109065493A), and then the thin film is placed in an OEC TO sequentially evaporate 20nm 4, 4' -cyclohexyl bis [ N, N-bis (4-methylphenyl) aniline]/MoO3（TAPC: MoO3=50: 1) thin film layer 201 as hole injection layer, 20nm 4, 4' -cyclohexyl bis [ N, N-bis (4-methylphenyl) aniline](TAPC) thin film layer 202 as a hole transport layer; then the Red-Mask, the Green-Mask and the Blue-Mask are respectively connected with TAPC (TaPC: MoO) on the PET substrate in sequence by an alignment platform device3The three-color front layout pattern of the thin film layer is shown as 4 (b), wherein the thin film layer is aligned in a T shape, 25nm of dichloromethane (DCM, red luminescent material) 205, 4- (2-ethylamino) benzene-1, 2-diol (DA, green luminescent material) 204 and 2P-Nme2 (blue luminescent material) 203 are evaporated by OEC; and then, after aligning the T on the Pad-Mask with the T on the PET after the luminescent material is plated, sequentially evaporating 50nm 1, 3, 5-tri (1-phenyl-1H benzimidazole-2-yl) benzene (TPBI) films 206 and 20nmN, N-diphenyl-N, N-bis (4-methylphenyl) -4, 4-biphenyldiamine (TPD) film 207 and 20nm 8-quinolyl-lithium (Liq) film 208 respectively by using OEC to serve as a hole blocking layer, an electron transport layer and an electron transport layer, respectively, using a metal Al layer 209 grown by SP to be 50nm as a cathode, and preparing the 5 x 5 Organic Light Emitting Diode (OLED) display pixel array through the film plating.
Claims (7)
1. A preparation method of a film device based on a full silicon-based mask is characterized by comprising the following specific steps:
(1) designing and preparing a silicon-based mask plate,
designing and preparing a corresponding silicon-based mask according to the size and the position of the thin film, the type of a transistor device and a corresponding evaporation or etching material; the silicon-based mask comprises a film coating mask and an etching mask;
the front pattern of the silicon-based mask comprises a pattern required in the processes of evaporation, etching and the like and an alignment mark for accurate alignment when a plurality of masks are used;
(2) preparing a device substrate, including material selection, cleaning and pretreatment of the substrate;
(3) preparing a semiconductor film on a device substrate;
(4) and aligning the semiconductor film material with a corresponding mask by using a high-precision alignment platform device, and preparing a device on the semiconductor film.
2. The method for manufacturing a thin film device according to claim 1, wherein the alignment marks in step (1) are designed around or in the middle of the whole mask pattern, and have a shape of 1-4 cross, T, or other precisely aligned english letters or patterns, and the size is determined according to the minimum precision of the mask.
3. The method for manufacturing a thin film device according to claim 1, wherein the material selected in step (2) is selected from substrates of different materials and different types of substrates according to the device type, specifically from any one of silicon wafers, polymers, plastics, glass, metals, and paper substrates; the cleaning is to remove the pollution caused by the processing or other influences of the substrate by adopting an organic solvent, acid, deionized water or ultrasound, and the pretreatment is to increase the adhesiveness between the film material and the substrate material or the smoothness of the substrate by baking or heating in an oven or a constant-temperature heating table, plasma treatment or spin-coating a photoresist film and the like.
4. The method of claim 1, wherein the semiconductor thin film in step (3) is made of a material selected from graphene, boron nitride, black phosphorus, two-dimensional transition metal chalcogenide, oxide, and organic material.
5. The method for manufacturing a thin film device according to claim 1, wherein the semiconductor thin film manufactured in step (3) is grown by chemical vapor deposition, or is manufactured by mechanical lift-off or thin film transfer.
6. The method for manufacturing a thin film device according to claim 1, wherein the alignment of the thin film material and the corresponding mask in step (4) is performed under a microscope by using a peripheral or middle alignment mark; the method for preparing the device comprises the steps of growing metal, organic matters or dielectric layers by magnetron sputtering, electron beam evaporation, organic evaporation coating platform or atomic layer deposition, and etching thin film materials and other materials by adopting a reactive plasma etching method or an inductive coupling plasma etching method.
7. The method for preparing a thin film device according to claim 6, wherein the thin film device in step (4) is a single or multiple top-bottom gate transistor, inverter, light emitting diode or corresponding array.
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