CN110993005A - Circuit structure, chip, training method and training device - Google Patents
Circuit structure, chip, training method and training device Download PDFInfo
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- CN110993005A CN110993005A CN201911277841.6A CN201911277841A CN110993005A CN 110993005 A CN110993005 A CN 110993005A CN 201911277841 A CN201911277841 A CN 201911277841A CN 110993005 A CN110993005 A CN 110993005A
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- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
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Abstract
The application provides a circuit structure, a chip, a training method and a training device. The circuit structure includes: a voltage regulation module; the delay line module is used for delaying the time sequence of the pipeline trigger; and the control module is used for controlling the voltage adjustment module to adjust the driving voltage of the search line driver to be lower than a target driving voltage and controlling the delay line module to delay the time sequence of the pipeline trigger by a target time length. According to the method and the device, the delay line module delays the time sequence of the priority coding path of the TCAM addressing structure by the target time length, and then the driving voltage of the search line driver on the search path is reduced, so that the time sequence allowance of the priority coding path is distributed to the search line driver, the search line driver can work at a lower driving voltage, and the purpose of reducing power consumption is achieved.
Description
Technical Field
The application relates to the technical field of TCAM addressing structures, in particular to a circuit structure, a chip, a training method and a training device.
Background
A Ternary Content Addressable Memory (TCAM) is a hardware lookup structure that can complete a lookup operation in one cycle. Therefore, the ternary content addressable memory TCAM is widely used in large routers. Although the speed of the ternary content addressable memory TCAM is fast, the lookup of the whole routing table is completed in one cycle by each comparison node, which results in large power consumption.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
An object of the embodiments of the present application is to provide a circuit structure, a chip, a training method, and a training apparatus, which have the beneficial effect of reducing the power consumption of a TCAM addressing structure.
In a first aspect, an embodiment of the present application provides a circuit structure, which is applied to a TCAM addressing structure of a ternary content addressable memory, where the TCAM addressing structure includes a TCAM array, a search line driver located on a search path of the TCAM array, and at least one pipeline flip-flop located on a priority encoding path of the TCAM array; the circuit structure includes:
a voltage adjusting module for adjusting the driving voltage of the search line driver;
the delay line module is used for delaying the time sequence of the pipeline trigger;
the control module is used for controlling the voltage adjusting module to adjust the driving voltage of the search line driver from an initial driving voltage to a target driving voltage and controlling the delay line module to delay the time sequence of the at least one pipeline trigger by a target time length; wherein a delay time increment generated when the driving voltage of the search line driver is adjusted down from an initial driving voltage to a target driving voltage is less than or equal to the target duration.
According to the embodiment of the application, the delay line module is adopted to delay the time sequence of the priority coding path of the TCAM addressing structure for the target duration, and then the driving voltage of the search line driver on the search path is reduced, so that the time sequence margin of the priority coding path is distributed to the search line driver, the search line driver can work at a lower driving voltage, and the purpose of reducing power consumption is achieved.
Optionally, in the circuit structure according to the embodiment of the present application, the control module includes:
the delay line control register unit is used for storing a delay control word corresponding to the target time length and controlling the delay line module to delay the time sequence of the pipeline trigger by the target time length according to the delay control word when the TCAM addressing structure works;
and the voltage control register is used for storing a voltage control word corresponding to a target driving voltage and controlling the voltage adjusting module to adjust the driving voltage of the search line driver to be a target driving voltage according to the voltage control word when the TCAM addressing structure works.
In the embodiment of the application, the delay line module is controlled by the delay line control register unit to delay the time sequence of the priority coding path of the TCAM addressing structure by a target time length, and then the voltage control register is controlled by the voltage adjustment module to reduce the driving voltage of the search line driver on the search path, so that the time sequence margin of the priority coding path is allocated to the search line driver, and the search line driver can operate at a lower driving voltage, thereby achieving the purpose of reducing power consumption.
Optionally, in the circuit structure according to this embodiment of the present application, the pipeline flip-flop includes at least one stage of pipeline flip-flop;
the delay line control register unit includes at least one delay line control register;
the delay line module comprises at least one delay line unit, the at least one delay line unit is respectively connected with the at least one delay line control register in a one-to-one correspondence mode, the at least one delay line unit is respectively in one-to-one correspondence with the at least one stage of pipeline trigger, the time sequence of the pipeline trigger is delayed by a first time length, and the sum of the first time lengths delayed by the time sequence of each pipeline trigger is the target time length.
Optionally, in the circuit structure according to this embodiment of the present application, the control module further includes a control unit, and the control unit is connected to the at least one delay line control register, the voltage control register, the at least one delay line unit, and the voltage adjustment module, respectively;
the control unit is used for sequentially training the at least one delay line unit and the voltage adjusting module to respectively acquire a first control word corresponding to the first time length and a voltage control word corresponding to the target driving voltage; and storing the first control word in a corresponding delay line control register and the voltage control word in the voltage control register.
In the embodiment of the application, the control unit is used for training the at least one delay line unit and the voltage adjusting module, so that the voltage control word corresponding to the target driving voltage as low as possible is obtained, the power consumption of the TCAM addressing structure during operation is reduced as low as possible, the control unit is used for writing or adjusting the delay line control register and the delay line control register, and the flexibility is higher.
Optionally, in the circuit structure according to the embodiment of the present application, the control module further includes at least one first gating unit;
the at least one first gating unit corresponds to the at least one delay line unit respectively, and the at least one first gating unit corresponds to the at least one first gating unit one to one respectively;
the first input end of each first gating unit is connected with the control unit, the second input end of each first gating unit is connected with the corresponding delay line control register, the output end of each first gating unit is connected with the corresponding delay line unit, and the control end of each first gating unit is connected with the control unit;
the control unit is used for controlling the first gating unit to connect the corresponding delay line unit with the control unit during training and controlling the first gating unit to connect the delay line unit with the corresponding delay line control register after training.
Optionally, in the circuit structure according to the embodiment of the present application, the control module further includes a second gating unit;
the first input end of the second gating unit is connected with the control unit, the second input end of the second gating unit is connected with the voltage parasitic controller, and the output end of the second gating unit is connected with the voltage adjusting module;
the control unit is used for controlling the second gating unit to connect the control unit with the voltage adjusting module during training, and controlling the second gating unit to connect the voltage parasitic controller with the voltage adjusting module after training.
Optionally, in the circuit structure according to this embodiment of the present application, when the control unit trains each of the at least one delay line unit, the delay line unit is sequentially controlled to increase the delay time until a search result of the TCAM addressing structure is erroneous, a first control word of the first duration is calculated based on a case of increasing the delay time, and the first control word is stored in the corresponding delay line control register.
Optionally, in the circuit structure according to the embodiment of the present application, when the control unit trains the delay line unit, the magnitude of the delay time added each time is the same.
Optionally, in the circuit structure according to this embodiment of the present application, when the control unit trains the voltage adjustment module, the control unit sequentially reduces the driving voltage of the search line driver until the search result of the TCAM addressing structure is erroneous, calculates a voltage control word corresponding to the target driving voltage based on a reduction of the driving voltage, and stores the voltage control word in the voltage control register.
Optionally, in the circuit structure according to the embodiment of the present application, when the control unit trains the voltage adjustment module, the amplitude of the driving voltage that is lowered each time is the same.
In a second aspect, an embodiment of the present application provides a chip, where the storage structure is a TCAM addressing structure, and the TCAM addressing structure includes any one of the circuit structures described above.
Optionally, in the chip according to this embodiment of the present application, the TCAM addressing structure further includes: the device comprises a TCAM array, a search line driver, a first-stage pipeline trigger, a sensitive amplifier, a second-stage pipeline trigger, a priority encoder and a third-stage pipeline trigger;
the first-stage pipeline trigger is connected with the search line driver, the search line driver is connected with a search line of the TCAM array, the sense amplifier is connected with a match line of the TCAM array, and the sense amplifier, the second-stage pipeline trigger, the priority encoder and the third-stage pipeline trigger are sequentially connected;
the voltage adjusting module of the circuit structure is connected with the driving voltage end of the search line driver, the delay line module of the circuit structure comprises two delay line units, one delay line unit is connected with the clock signal input end of the second-stage pipeline trigger, and the other delay line unit is connected with the clock signal input end of the third-stage pipeline trigger.
In a third aspect, an embodiment of the present application further provides a training method, which is applied to the above chip or circuit structure, and the method includes the following steps:
setting an initial driving voltage for the voltage adjusting module;
sequentially training each delay line unit of the delay line module to obtain a first control word of a first duration for each delay line unit to delay the time sequence of the corresponding pipeline trigger, wherein the delay line unit connected with the pipeline trigger relatively far away from the TCAM array is trained firstly, and then the delay line unit connected with the pipeline trigger relatively close to the TCAM array is trained;
and training the voltage adjusting module to obtain a target driving voltage, wherein the initial driving voltage of the search line driver is reduced to the delay time increment generated by the target driving voltage, and the delay time increment is less than or equal to the sum of the first time lengths.
Optionally, in the training method according to this embodiment of the present application, the step of sequentially training the delay line units of the delay line module to obtain the first control word of the first duration of the delay of each of the delay line units includes:
when each delay line unit in the at least one delay line unit is trained, the delay line units are controlled to increase the delay time one by one until the search result of the TCAM addressing structure is wrong;
and calculating a first control word of the first duration based on the condition of increasing the delay time.
Optionally, in the training method according to the embodiment of the present application, the magnitude of each increased delay time is the same.
Optionally, in the training method according to the embodiment of the present application, the step of training the voltage adjustment module to obtain the target driving voltage includes:
and when the voltage adjusting module is trained, gradually reducing the driving voltage of the search line driver until the search result of the TCAM addressing structure is wrong, and calculating to obtain a voltage control word corresponding to the target driving voltage based on the reduction condition of the driving voltage.
Optionally, in the training method according to the embodiment of the present application, the amplitude of the driving voltage lowered each time is the same.
In a fourth aspect, an embodiment of the present application further provides a training apparatus, which is applied to the above chip or circuit structure, and the apparatus includes:
the setting module is used for setting an initial driving voltage for the voltage adjusting module;
the first training module is used for sequentially training each delay line unit of the delay line module to obtain a first control word of a first delay duration of each delay line unit, wherein the delay line unit connected with the pipeline trigger relatively far away from the TCAM array is trained firstly, and then the delay line unit connected with the pipeline trigger relatively close to the TCAM array is trained;
and the second training module is used for training the voltage adjusting module to obtain a target driving voltage, wherein the delay time increment generated by reducing the initial driving voltage of the search line driver to the target driving voltage is less than or equal to the sum of the first time lengths.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic block diagram of a circuit structure provided in an embodiment of the present application.
Fig. 2 is a schematic circuit diagram of a first circuit structure of a circuit structure provided in the embodiment of the present application.
Fig. 3 is a flowchart of training a circuit structure according to an embodiment of the present disclosure.
Fig. 4 is a schematic circuit diagram of a second circuit structure of the circuit structure provided in the embodiment of the present application.
Fig. 5 is a schematic diagram of a third circuit structure of the circuit structure according to the embodiment of the present application.
Fig. 6 is a schematic circuit structure diagram of a TCAM addressing structure according to an embodiment of the present application.
Fig. 7 is a flowchart of a training method according to an embodiment of the present application.
Fig. 8 is a structural diagram of an exercise device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a circuit structure in some embodiments of the present application. The circuit structure is applied to addressing of a Ternary Content Addressable Memory (TCAM), and the TCAM addressing structure comprises a TCAM array, a search line driver positioned on a search path of the TCAM array and a pipeline trigger positioned on a priority coding path of the TCAM array. Wherein, this circuit structure 100 includes: a voltage adjusting module 11, a delay line module 12 and a control module 13. The voltage adjustment module 11 is configured to adjust a driving voltage of the search line driver; the delay line module 12 is used for delaying the time sequence of the pipeline trigger; the control module 13 is configured to control the voltage adjustment module 11 to adjust the driving voltage of the search line driver from an initial driving voltage to a target driving voltage, and control the delay line module 12 to delay the timing of the pipeline flip-flop by a target duration; wherein a delay time increment generated when the driving voltage of the search line driver is adjusted from an initial driving voltage to a target driving voltage is less than or equal to the target duration; and, the target duration is less than the total timing margin on the priority encoding path; of course, the delay time increment generated when the driving voltage of the search line driver is decreased from the initial driving voltage to the target driving voltage is equal to the target duration, which is the best state, and the power consumption is most reduced. The initial driving voltage is the driving voltage when the search line driver is introduced into the voltage adjustment module 11, and the TCAM addressing structure can achieve normal operation under the initial driving voltage.
According to the embodiment of the application, the delay line module is adopted to delay the time sequence of the priority coding path of the TCAM addressing structure for the target duration, and then the driving voltage of the search line driver on the path is reduced, so that the time sequence margin of the priority coding path is distributed to the search line driver, the search line driver can work at a lower driving voltage, and the purpose of reducing power consumption is achieved.
The voltage adjustment module 11 is a voltage adjuster commonly known in the art, and can adjust the driving voltage of the search line driver based on an externally input voltage control word.
Referring to fig. 2, the delay line module 12 includes at least one delay line unit 121, and the number of the delay line units 121 may be 1, two, or more. The upper limit on the number of delay line units 121 is the number of pipeline flip-flops on the priority encoding path of the TCAM addressing structure. In the present embodiment, the number of the delay line units 121 is two. The number of pipeline flip-flops on the preferred encoding path of the TCAM addressing structure is also two. Each delay line unit 121 is used to delay the timing of the pipeline flip-flop connected thereto by a certain time period.
The control module 13 includes a control unit 131, a voltage control register 132, a delay line control register unit 133, at least one first strobe unit 134, and a second strobe unit 135.
The delay line control register unit 133 includes at least one delay line control register 1331, the number of the delay line control registers 1331 is the same as that of the first gating units 134, and in this embodiment, the number of the delay line control registers 1331 and that of the first gating units 134 are two. The control unit 131 is respectively connected to the first input terminal of each first gating unit 134, the first input terminal of each second gating unit 135, each voltage control register 132 and each delay line control register 1331, the second input terminal of the first gating unit 134 is connected to the corresponding delay line control register 1331, the output terminal of the first gating unit 134 is connected to the corresponding delay line unit 121, the second input terminal of the second gating unit 135 is connected to the voltage control register 132, and the output terminal of the second gating unit 135 is connected to the voltage adjustment module 11. The control unit 131 is further connected to the control terminal of the first strobe unit 134 and the control terminal of the second strobe unit 135, respectively.
The voltage control register 132 is configured to store a voltage control word corresponding to a target driving voltage, and control the voltage adjustment module 11 to adjust the driving voltage of the search line driver to a target driving voltage according to the voltage control word when the TCAM addressing structure operates.
The delay line control register unit 133 is configured to store a delay control word corresponding to a target time duration, and control the delay line module 12 to delay the time sequence of the pipeline flip-flop by the target time duration according to the delay control word when the TCAM addressing structure operates. Correspondingly, each delay line control register is configured to store a first control word corresponding to a first time length, and control the delay line module 12 to delay the time sequence of the corresponding pipeline flip-flop by a first standard time length according to the first control word when the TCAM address structure operates.
The first gating unit 134 and the second gating unit 135 may both adopt a common two-input one-output gating chip.
When the voltage adjustment module 11 and the delay line module 12 are trained, the control unit 131 is configured to control the first gating unit 134 to connect the control unit 131 with the corresponding delay line unit 121, and control the second gating unit 135 to connect the control unit 131 with the voltage adjustment module 11, so that the voltage adjustment module 11 can receive the voltage control word sent by the control unit 131, and the delay line unit 121 can receive the first control word sent by the control unit 131. When the training is completed and the TCAM addressing structure performs a normal search operation, the control unit 131 controls the first gating unit 134 to connect the delay line control register 1331 with the corresponding delay line unit 121, so that the delay line unit 121 can receive the first control word stored in the delay line control register; the control unit controls the second gating unit 135 to connect the voltage control register 132 and the voltage adjustment module 11, so that the voltage adjustment module 11 can receive the voltage control word stored in the voltage control register 132.
During training, the control unit 131 trains the at least one delay line unit 121 and the voltage adjustment module 11 in sequence to obtain a first control word corresponding to a first time length and a voltage control word corresponding to the target driving voltage, respectively; and stores the first control word in the corresponding delay line control register 1331 and the voltage control word in the voltage control register 132.
When the control unit 131 trains each delay line unit 121 in at least one delay line unit 121, the delay line unit 121 is sequentially controlled to increase the delay time until the search result of the TCAM addressing structure is erroneous, and a first control word of the first duration is calculated based on the increase of the delay time, and is stored in the corresponding delay line control register 1331. When the control unit 131 trains the delay line unit 121, the magnitude of the delay time increased each time is the same. When the two delay line units 121 are trained, the delay line unit 121 connected to the pipeline flip-flop far from the TCAM array is trained, and then the delay line unit 121 connected to the pipeline flip-flop near the TCAM array is trained.
When the control unit 131 trains the voltage adjustment module 11, the driving voltage of the search line driver is gradually decreased until the search result of the TCAM addressing structure is erroneous, and a voltage control word corresponding to the target driving voltage is calculated based on the decrease of the driving voltage and stored in the voltage control register 132. When the control unit 131 trains the voltage adjustment module 11, the driving voltage is reduced by the same magnitude every time.
As shown in fig. 3, the control unit 131 is a flowchart for training the voltage adjustment module 11 and the delay line module 12. The two delay line units are respectively a first delay line unit and a second delay line unit. The first delay line unit is a delay line unit 121 connected away from the pipeline flip-flop of the TCAM array, and the second delay line unit is a delay line unit 121 connected close to the pipeline flip-flop of the TCAM array. Specifically, the training of the control unit 131 comprises the following steps:
s101, setting the driving voltage of the search line driver as the highest output voltage of the voltage regulation module, and setting the first delay line unit and the second delay line unit as the shortest delay.
And S102, adding one step delay to the first delay line unit.
S103, judging whether the search results of the TCAM addressing structure are correct or not; if both are correct, go to step S102, and if not, go to step S104.
And S104, recording the value of the first control word of the first delay line unit before the search error.
And S105, adding one step delay to the second delay line unit.
S106, judging whether the search results of the TCAM addressing structure are correct or not; if both are correct, the process goes to step S105, and if not, the process goes to step S107.
And S107, recording the value of the first control word of the second delay line unit before the search error.
And S108, controlling the voltage adjusting module to enable the driving voltage to be decreased by one voltage step.
S109, judging whether the search results of the TCAM addressing structure are all correct; if both are correct, go to step S108, and if not, go to step S110.
And S110, recording the value of the voltage control word before the search error.
And S111, writing the voltage control word, the first control word of the first delay line unit and the first control word of the second delay line unit into the voltage control register, the first delay line control register and the second delay line control register respectively.
During training, writing data in all storage units of the TCAM array, comparing the data with the data stored in the TCAM array by using different data, judging that the search is correct if the comparison results are both in accordance with the expectation, and judging that the search results are not correct if one comparison is not in accordance with the expectation.
In step S102, the step delay is set in relation to the total timing margin of the priority coding path, for example, the timing margin is w1, and the step delay can be set to w1/x, x is 50 or 100. Of course, it is not limited thereto. In step S104, for example, if the search is erroneous during the nth increment of the step delay, the delay value of the first delay line unit is set to w0+ (n-1) w1/x, where w0 is the initial delay value of the first delay line unit, and thus the first control word corresponding to the first delay line unit corresponds to the delay value w0+ (n-1) w 1/x. It will be appreciated that the incremental step delays may not be equal.
In step S105, the step delay is set in relation to the total timing margin of the priority coding path, for example, the timing margin is w1, and the step delay can be set to w1/x, x is 50 or 100. Of course, it is not limited thereto. In step S106, for example, if the search is erroneous during the nth increment of the step delay, the delay value of the first delay line unit is set to w0+ (n-1) w1/x, where w0 is the initial delay value of the second delay line unit, and thus the first control word corresponding to the first delay line unit corresponds to the delay value w0+ (n-1) w 1/x. It will be appreciated that the incremental step delays may not be equal.
In step S108, the voltage step can be set according to actual conditions, and of course, the smaller the voltage step is set, the closer the obtained final target driving voltage is to the optimal value, so that the power consumption of the TCAM addressing structure is the lowest. In step S109, for example, when the search is wrong at the nth incremental voltage step, the target driving voltage of the output of the voltage adjustment module is set to V0- (n-1) V1/x, where V0 is the initial value of the voltage of the output of the voltage adjustment module, and therefore, the voltage control word corresponding to the control module corresponds to the voltage value V0- (n-1) V1/x. It will be appreciated that the voltage steps for each increase may not be equal.
The control unit 131 may use a chip to write a control program to implement the above functions, but it is understood that the control unit 131 may use a digital logic circuit to implement the above functions.
It is to be understood that, as shown in fig. 4, in some embodiments, although there may be a plurality of pipeline flip-flops in the priority encoding path of the TCAM array of the TCAM addressing structure, the circuit structure provided in this embodiment may train and delay only one of the pipeline flip-flops. Accordingly, the delay line block 12 of the circuit configuration includes only one delay line unit 121 correspondingly, and the delay line control register unit 133 also includes only one delay line control register 1331 correspondingly.
It is to be understood that, as shown in fig. 5, in some embodiments, the control module 13 may not include the control unit, the first gating unit, and the second gating unit. The control module 13 does not train the voltage adjustment module 11 and the delay line module 12, and can realize the training of the voltage adjustment module and the delay line module through an external circuit structure or a chip structure, and only needs to store the trained voltage control word in the voltage control register 132 and store the trained first control word in the corresponding delay line control register 1331; the voltage adjusting modules and the delay line modules of a plurality of circuit structures can be trained by adopting a set of external circuit structure, so that the effects of reducing the number of devices of the circuit structure and reducing the cost are achieved.
The embodiment of the application provides a chip, and a storage structure of the chip is a TCAM addressing structure. Referring to fig. 6, the TCAM addressing structure 200 includes the circuit structure 100 in any of the embodiments described above.
Specifically, the TCAM addressing structure 200 further includes: TCAM array 21, search line driver 22, first stage pipeline flip-flop 23, sense amplifier 24, second stage pipeline flip-flop 25, priority encoder 26, and third stage pipeline flip-flop 27; the first-stage pipeline flip-flop 23 is connected to the search line driver 22, the search line driver 22 is connected to the search lines SL and SLN of the TCAM array 21, the sense amplifier 24 is connected to the match line ML of the TCAM array 21, and the sense amplifier 24, the second-stage pipeline flip-flop 25, the priority encoder 26, and the third-stage pipeline flip-flop 27 are sequentially connected; the voltage adjustment module 11 of the circuit structure 100 is connected to the driving voltage terminal VDD _ SL of the search line driver 22, the delay line module 12 of the circuit structure 100 includes two delay line units 121, one of the delay line units 121 is connected to the clock signal input terminal of the second stage pipeline flip-flop 25, and the other of the delay line units 121 is connected to the clock signal input terminal of the third stage pipeline flip-flop 27.
The search line driver 22 and the first stage pipeline flip-flop 23 form a search path of the TCAM array 21, and the sense amplifier 24, the second stage pipeline flip-flop 25, the priority encoder 26, and the third stage pipeline flip-flop 27 form a priority encoding path of the TCAM array 21. TCAM array 21 may include a plurality of sub-arrays.
The working process of the TCAM addressing structure 200 is that a search key is transmitted to the search driver 22 through the first stage pipeline flip-flop 23, and the search driver outputs differential signals SL and SLN to the TCAM array 21. The match result searched by the TCAM array 21 is amplified by the match line ML via the sensitive amplifier 24 and then locked into the second stage pipeline flip-flop 25. The encoded result is then locked into the third stage pipeline flip-flop 27 via the priority encoder 26 and is finally output.
Wherein, the timing overhead between the first stage pipeline flip-flop and the second stage pipeline flip-flop is denoted as t12, and the timing overhead between the second stage pipeline flip-flop and the third stage pipeline flip-flop is t23, so that the normal operation of the TCAM addressing structure 200 can still be ensured after the driving voltage of the search line driver 22 is reduced by delaying the timings triggered by the second stage pipeline flip-flop and the third stage pipeline flip-flop; since the driving voltage of the search line driver 22 is reduced, the power consumption of the TCAM addressing structure 200 is also reduced accordingly.
Referring to fig. 7, fig. 7 is a flowchart of a training method provided in an embodiment of the present application, and the training method is applied to a TCAM addressing structure in the foregoing embodiment or a circuit structure in the foregoing embodiment, and the training method is integrated in a control unit of the circuit structure in the form of a computer program, and may also be integrated in an external electronic device. The method comprises the following steps:
s201, setting an initial driving voltage for the voltage adjusting module.
S202, sequentially training each delay line unit of the delay line module to obtain a first control word of a first duration for each delay line unit to delay the time sequence of the corresponding pipeline trigger, wherein the delay line unit connected with the pipeline trigger relatively far away from the TCAM array is trained first, and then the delay line unit connected with the pipeline trigger relatively close to the TCAM array is trained.
S203, training the voltage adjusting module to obtain a target driving voltage and a corresponding voltage control word, wherein the initial driving voltage of the search line driver is reduced to be the sum of delay time increment generated by the target driving voltage which is less than or equal to each first duration.
In step S201, the initial driving voltage output by the search line driver is set as the highest output voltage of the voltage adjusting module, and the delay time of each delay line unit is set as the shortest delay, for example, 0. During training, writing data in all the memory cells of the TCAM array, comparing the data with the data in the TCAM array by using different data, judging that the search is correct if the comparison results are both in accordance with expectations, and judging that the search results are not correct if one comparison is not in accordance with expectations.
In step S202, for example, for the TCAM addressing structure shown in fig. 6, the delay time of the delay line unit connected to the third pipeline flip-flop is trained, and then the delay time of the delay line unit connected to the second pipeline flip-flop is trained. The step S202 includes: when each delay line unit in the at least one delay line unit is trained, the delay line units are controlled successively to increase the delay time until the search result of the TCAM addressing structure is wrong; and calculating a first control word of the first duration based on the condition of increasing the delay time. The delay time of each increment of the delay line unit is the same in amplitude, and may be different.
It is understood that, in some embodiments, in order to find the optimal value of each first duration, during training, the step S202 includes:
s2021, when each of the at least one delay line unit is trained, gradually controlling the delay line unit to increase a first delay step until a search result of the TCAM addressing structure is incorrect; s2022, calculating to obtain a first expected duration when the search result is not wrong based on the condition of increasing the first delay step length; s2023, taking the first expected duration as a delay initial value of a delay line unit, and gradually controlling the delay line unit to increase a second delay step until a search result of the TCAM addressing structure is wrong; s2024, calculating a first time length when the search result has no error and a corresponding first control word based on a condition of adding a second delay step, where the second delay step is smaller than the first delay step, for example, the second delay step is half or one tenth of the first delay step. The first step delay is set in relation to the total timing margin of the priority encoded path, e.g., timing margin w1, then the first step delay can be set to w1/x, x being 50 or 100. Of course, it is not limited thereto. For example, if the search is incorrect when the nth increment delay is added, the delay value of the delay line unit is set to w0+ (n-1) w1/x, where w0 is the initial delay value of the second delay line unit, and thus the first control word corresponding to the first delay line unit corresponds to the delay value w0+ (n-1) w 1/x.
Of course, it is understood that a smaller third delay step may be set in turn for positioning.
The embodiment of the application can realize the positioning of the optimal delay time by setting the first delay step and the second delay step, and can extrude the timing sequence margin on the priority coding path as much as possible, so that the voltage of the search line driver can be reduced as much as possible, and the power consumption is further reduced.
In step S203, when the voltage adjustment module is trained, the driving voltage output to the search line driver is gradually reduced until the search result of the TCAM addressing structure is erroneous, and a voltage control word corresponding to the target driving voltage is calculated based on the reduction of the driving voltage. The voltage adjustment module reduces the driving voltage each time with the same amplitude, but may also reduce the driving voltage each time with different amplitudes.
It is to be understood that, in some embodiments, in order to find the optimal value of the target driving voltage, during training, the step S203 includes: s2031, when the voltage adjusting module is trained, the driving voltage of the search line driver is gradually reduced by taking the first voltage step as the amplitude until the search result of the TCAM addressing structure is wrong; s2032, calculating the first expected driving voltage based on the condition of voltage reduction by using the first voltage step. S2033, using the first expected driving voltage as a starting point, and using the second voltage step as an amplitude to gradually decrease the driving voltage of the search line driver until the search result of the TCAM addressing structure is wrong. And S2034, calculating to obtain the target driving voltage and the corresponding voltage control word based on the condition of voltage reduction by using the second voltage step length. The second voltage step is smaller than the first voltage step, for example, the second voltage step is half or one tenth of the first voltage step. The setting of the first voltage step can be set according to actual conditions, and of course, the smaller the voltage step is set, the closer the obtained final target driving voltage is to the optimal value, so that the power consumption of the TCAM addressing structure is the lowest. For example, if the search is erroneous when the first voltage step is increased the nth time, the first expected driving voltage of the output of the voltage adjustment module is set to V0- (n-1) V3, where V0 is the initial driving voltage of the output of the voltage adjustment module and V3 is the first voltage step. Similarly, when calculating the target driving voltage based on the step-down condition of the second voltage step, the same method as that for calculating the first expected driving voltage is adopted. For example, if the search is erroneous when increasing the first voltage step q times, the first expected driving voltage of the output of the voltage adjustment module is set to V0- (n-1) V3- (q-1) V4, wherein V4 is the second voltage step.
The embodiment of the application can realize the positioning of the optimal delay driving voltage by setting the first voltage step length and the second voltage step length, so that the voltage of the search line driver can be reduced as much as possible, and the power consumption is further reduced.
Referring to fig. 8, fig. 8 is a structural diagram of a training apparatus in some embodiments of the present application, in which the apparatus includes, in the above chip or circuit structure: a setup module 301, a first training module 302, and a second training module 303.
The setting module 301 is configured to set an initial driving voltage for the voltage adjustment module.
The first training module 302 is configured to train each delay line unit of the delay line module in sequence to obtain a first control word of a first delay duration of each delay line unit, where a delay line unit connected to a pipeline flip-flop relatively far away from the TCAM array is trained first, and a delay line unit connected to a pipeline flip-flop relatively near to the TCAM array is trained later.
The second training module 303 is configured to train the voltage adjustment module to obtain a target driving voltage, where an initial driving voltage of the search line driver is decreased to a delay time increment generated by the target driving voltage, which is less than or equal to a sum of the first durations.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (18)
1. A circuit arrangement for use in a ternary content addressable memory, TCAM, addressing architecture comprising a TCAM array, a search line driver located in a search path of the TCAM array, and at least one pipeline flip-flop located in a priority encoding path of the TCAM array; characterized in that the circuit arrangement comprises:
a voltage adjusting module for adjusting the driving voltage of the search line driver;
the delay line module is used for delaying the time sequence of the pipeline trigger;
the control module is used for controlling the voltage adjusting module to adjust the driving voltage of the search line driver from an initial driving voltage to a target driving voltage and controlling the delay line module to delay the time sequence of the at least one pipeline trigger by a target time length; wherein a delay time increment generated when the driving voltage of the search line driver is adjusted down from an initial driving voltage to a target driving voltage is less than or equal to the target duration.
2. The circuit arrangement of claim 1, wherein the control module comprises:
the delay line control register unit is used for storing a delay control word corresponding to the target time length and controlling the delay line module to delay the time sequence of the pipeline trigger by the target time length according to the delay control word when the TCAM addressing structure works;
and the voltage control register is used for storing a voltage control word corresponding to a target driving voltage and controlling the voltage adjusting module to adjust the driving voltage of the search line driver to be a target driving voltage according to the voltage control word when the TCAM addressing structure works.
3. The circuit structure of claim 2, wherein said delay line control register unit includes at least one delay line control register;
the delay line module comprises at least one delay line unit, the at least one delay line unit is respectively connected with the at least one delay line control register in a one-to-one correspondence mode, the at least one delay line unit is respectively connected with the at least one pipeline trigger in a one-to-one correspondence mode, the time sequence of the pipeline trigger is delayed by first time length, and the sum of the first time length delayed by the time sequence of each pipeline trigger is equal to the target time length.
4. The circuit structure of claim 3, wherein the control module further comprises a control unit, the control unit being connected to the at least one delay line control register, the voltage control register, the at least one delay line unit, and the voltage adjustment module, respectively;
the control unit is used for sequentially training the at least one delay line unit and the voltage adjusting module to respectively acquire a first control word corresponding to the first time length and a voltage control word corresponding to the target driving voltage; and storing the first control word in a corresponding delay line control register and the voltage control word in the voltage control register.
5. The circuit arrangement according to claim 4, wherein the control module further comprises at least one first gating cell;
the at least one first gating unit corresponds to the at least one delay line unit respectively, and the at least one first gating unit corresponds to the at least one first gating unit one to one respectively;
the first input end of each first gating unit is connected with the control unit, the second input end of each first gating unit is connected with the corresponding delay line control register, the output end of each first gating unit is connected with the corresponding delay line unit, and the control end of each first gating unit is connected with the control unit;
the control unit is used for controlling the first gating unit to connect the corresponding delay line unit with the control unit during training and controlling the first gating unit to connect the delay line unit with the corresponding delay line control register after training.
6. The circuit arrangement of claim 5, wherein the control module further comprises a second gating cell;
the first input end of the second gating unit is connected with the control unit, the second input end of the second gating unit is connected with the voltage parasitic controller, and the output end of the second gating unit is connected with the voltage adjusting module;
the control unit is used for controlling the second gating unit to connect the control unit with the voltage adjusting module during training, and controlling the second gating unit to connect the voltage parasitic controller with the voltage adjusting module after training.
7. The circuit structure according to any of claims 4-6, wherein said control unit, when training each of said at least one delay line unit, successively controls said delay line unit to increase the delay time until the search result of said TCAM addressing structure is erroneous, calculates a first control word of said first duration based on the increase of the delay time, and stores said first control word in the corresponding delay line control register.
8. The circuit structure of claim 7, wherein the control unit trains the delay line units with the same magnitude of delay time added each time.
9. The circuit structure according to any of claims 4-6, wherein the control unit, during training of the voltage adjustment module, sequentially reduces the driving voltage of the search line driver until the search result of the TCAM addressing structure is erroneous, calculates a voltage control word corresponding to the target driving voltage based on the reduction of the driving voltage, and stores the voltage control word in the voltage control register.
10. The circuit arrangement of claim 9, wherein the control unit trains the voltage adjustment module such that the magnitude of the driving voltage that is reduced each time is the same.
11. A chip wherein the memory structure is a TCAM addressing structure, the TCAM addressing structure comprising the circuit structure of any one of claims 1 to 10.
12. The chip of claim 11, in which the TCAM addressing structure further comprises: the device comprises a TCAM array, a search line driver, a first-stage pipeline trigger, a sensitive amplifier, a second-stage pipeline trigger, a priority encoder and a third-stage pipeline trigger;
the first-stage pipeline trigger is connected with the search line driver, the search line driver is connected with a search line of the TCAM array, the sense amplifier is connected with a match line of the TCAM array, and the sense amplifier, the second-stage pipeline trigger, the priority encoder and the third-stage pipeline trigger are sequentially connected;
the voltage adjusting module of the circuit structure is connected with a driving voltage end of the search line driver, the delay line module of the circuit structure comprises two delay line units, one delay line unit is connected with a clock signal input end of the second stage pipeline trigger, and the other delay line unit is connected with a clock signal input end of the third stage pipeline trigger.
13. A training method for use in a circuit arrangement according to any of claims 1 to 10 or a chip according to any of claims 11 to 12, the method comprising the steps of:
setting an initial driving voltage for the voltage adjusting module;
sequentially training each delay line unit of the delay line module to obtain a first control word of a first duration for each delay line unit to delay the time sequence of the corresponding pipeline trigger, wherein the delay line unit connected with the pipeline trigger relatively far away from the TCAM array is trained firstly, and then the delay line unit connected with the pipeline trigger relatively close to the TCAM array is trained;
and training the voltage adjusting module to obtain a target driving voltage and a corresponding voltage control word, wherein the initial driving voltage of the search line driver is reduced to a delay time increment generated by the target driving voltage which is less than or equal to the sum of the first time lengths.
14. The method of claim 13, wherein the step of sequentially training the delay line units of the delay line module to obtain the first control word of the first duration of the delay of each of the delay line units comprises:
when each delay line unit in the at least one delay line unit is trained, the delay line units are controlled successively to increase the delay time until the search result of the TCAM addressing structure is wrong;
and calculating a first control word of the first duration based on the condition of increasing the delay time.
15. The training method of claim 14, wherein the delay time for each increment of the delay line element is the same magnitude.
16. The method of claim 13, wherein the step of training the voltage adjustment module to obtain the target driving voltage and the corresponding voltage control word comprises:
and when the voltage adjusting module is trained, gradually reducing the driving voltage output to the search line driver until the search result of the TCAM addressing structure is wrong, and calculating to obtain the target driving voltage and the corresponding voltage control word based on the reduction condition of the driving voltage.
17. The training method of claim 16, wherein the voltage adjustment module decreases the driving voltage at the same magnitude each time.
18. Training device for use in a circuit arrangement according to any of claims 1-10 or a chip according to any of claims 11-12, the device comprising:
the setting module is used for setting an initial driving voltage for the voltage adjusting module;
the first training module is used for sequentially training each delay line unit of the delay line module to obtain a first control word of a first delay duration of each delay line unit, wherein the delay line unit connected with the pipeline trigger relatively far away from the TCAM array is trained firstly, and then the delay line unit connected with the pipeline trigger relatively close to the TCAM array is trained;
and the second training module is used for training the voltage adjusting module to obtain a target driving voltage and a corresponding voltage control word, wherein the delay time increment generated by reducing the initial driving voltage of the search line driver to the target driving voltage is less than or equal to the sum of the first time lengths.
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Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774403A (en) * | 1997-06-12 | 1998-06-30 | Hewlett-Packard | PVT self aligning internal delay line and method of operation |
| CN1227932A (en) * | 1997-12-19 | 1999-09-08 | 日本电气株式会社 | Cache memory system which assures normal operation in synchronous cache access and access method to cache memory |
| CN1381849A (en) * | 2001-04-03 | 2002-11-27 | 睦塞德技术公司 | Content-addressed memory unit |
| US6944039B1 (en) * | 2003-12-12 | 2005-09-13 | Netlogic Microsystems, Inc. | Content addressable memory with mode-selectable match detect timing |
| CN1757202A (en) * | 2002-08-13 | 2006-04-05 | 英特尔公司 | Free list and ring data structure management |
| CN101840374A (en) * | 2010-04-28 | 2010-09-22 | 福建星网锐捷网络有限公司 | Processing device, information searching system and information searching method |
| CN103366808A (en) * | 2012-03-27 | 2013-10-23 | 瑞萨电子株式会社 | Content addressable memory chip |
| CN103502964A (en) * | 2011-05-06 | 2014-01-08 | 超威半导体公司 | Control circuit and method for testing a memory element |
| CN103730156A (en) * | 2009-08-03 | 2014-04-16 | 瑞萨电子株式会社 | Content addressable memory |
| CN103839573A (en) * | 2012-11-27 | 2014-06-04 | 阿尔特拉公司 | Memory interface circuitry with improved timing margins |
| CN104021246A (en) * | 2014-05-28 | 2014-09-03 | 复旦大学 | Self-adaptive length predictor applied to low power consumption fault-tolerant circuit |
| CN106486159A (en) * | 2015-08-28 | 2017-03-08 | 瑞萨电子株式会社 | Semiconductor device |
| CN106656817A (en) * | 2016-12-29 | 2017-05-10 | 盛科网络（苏州）有限公司 | Method for reducing lookup conflicts caused by read-write of TCAM |
| US9941008B1 (en) * | 2017-03-23 | 2018-04-10 | National Taiwan University | Ternary content addressable memory device for software defined networking and method thereof |
| CN107967925A (en) * | 2017-12-13 | 2018-04-27 | 大连理工大学 | A kind of adaptive low-power consumption CAM matched line sensors of technique change |
| CN108091357A (en) * | 2016-11-21 | 2018-05-29 | 爱思开海力士有限公司 | Semiconductor memory system and its operating method |
| CN108986868A (en) * | 2017-05-30 | 2018-12-11 | 瑞萨电子株式会社 | Content addressable memory and semiconductor device |
| CN109002647A (en) * | 2018-08-17 | 2018-12-14 | 郑州轻工业学院 | A kind of memristor associative memory neural network circuit with delay learning functionality |
| CN109147855A (en) * | 2017-06-27 | 2019-01-04 | 英特尔公司 | Design relevant voltage control and clock in region |
-
2019
- 2019-12-11 CN CN201911277841.6A patent/CN110993005B/en active Active
Patent Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5774403A (en) * | 1997-06-12 | 1998-06-30 | Hewlett-Packard | PVT self aligning internal delay line and method of operation |
| CN1227932A (en) * | 1997-12-19 | 1999-09-08 | 日本电气株式会社 | Cache memory system which assures normal operation in synchronous cache access and access method to cache memory |
| CN1381849A (en) * | 2001-04-03 | 2002-11-27 | 睦塞德技术公司 | Content-addressed memory unit |
| CN1757202A (en) * | 2002-08-13 | 2006-04-05 | 英特尔公司 | Free list and ring data structure management |
| US6944039B1 (en) * | 2003-12-12 | 2005-09-13 | Netlogic Microsystems, Inc. | Content addressable memory with mode-selectable match detect timing |
| CN103730156A (en) * | 2009-08-03 | 2014-04-16 | 瑞萨电子株式会社 | Content addressable memory |
| CN101840374A (en) * | 2010-04-28 | 2010-09-22 | 福建星网锐捷网络有限公司 | Processing device, information searching system and information searching method |
| CN103502964A (en) * | 2011-05-06 | 2014-01-08 | 超威半导体公司 | Control circuit and method for testing a memory element |
| CN103366808A (en) * | 2012-03-27 | 2013-10-23 | 瑞萨电子株式会社 | Content addressable memory chip |
| CN103839573A (en) * | 2012-11-27 | 2014-06-04 | 阿尔特拉公司 | Memory interface circuitry with improved timing margins |
| CN104021246A (en) * | 2014-05-28 | 2014-09-03 | 复旦大学 | Self-adaptive length predictor applied to low power consumption fault-tolerant circuit |
| CN106486159A (en) * | 2015-08-28 | 2017-03-08 | 瑞萨电子株式会社 | Semiconductor device |
| CN108091357A (en) * | 2016-11-21 | 2018-05-29 | 爱思开海力士有限公司 | Semiconductor memory system and its operating method |
| CN106656817A (en) * | 2016-12-29 | 2017-05-10 | 盛科网络（苏州）有限公司 | Method for reducing lookup conflicts caused by read-write of TCAM |
| US9941008B1 (en) * | 2017-03-23 | 2018-04-10 | National Taiwan University | Ternary content addressable memory device for software defined networking and method thereof |
| CN108986868A (en) * | 2017-05-30 | 2018-12-11 | 瑞萨电子株式会社 | Content addressable memory and semiconductor device |
| CN109147855A (en) * | 2017-06-27 | 2019-01-04 | 英特尔公司 | Design relevant voltage control and clock in region |
| CN107967925A (en) * | 2017-12-13 | 2018-04-27 | 大连理工大学 | A kind of adaptive low-power consumption CAM matched line sensors of technique change |
| CN109002647A (en) * | 2018-08-17 | 2018-12-14 | 郑州轻工业学院 | A kind of memristor associative memory neural network circuit with delay learning functionality |
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