WO2023116366A1

WO2023116366A1 - Flash memory controller, delay adjustment method and storage device

Info

Publication number: WO2023116366A1
Application number: PCT/CN2022/135130
Authority: WO
Inventors: 陆震熙; 黄运新
Original assignee: 深圳大普微电子科技有限公司
Priority date: 2021-12-24
Filing date: 2022-11-29
Publication date: 2023-06-29
Also published as: CN114327267A; CN114327267B

Abstract

A flash memory controller, a delay adjustment method and a storage device. The flash memory controller comprises a data driving module, a particle switching detection module, a signal delay module and a delay parameter setting module. The data driving module selects a target flash memory particle from a plurality of flash memory particles according to the current particle operation requirement, so as to perform a read-write operation on the target flash memory particle; when it is detected that the data driving module is switched to the target flash memory particle for operation, the particle switching detection module generates a detection signal which represents that the currently operated flash memory particle is switched to the target flash memory particle; the signal delay module performs delay transmission on a read-write operation signal between the data driving module and the target flash memory particle according to the currently set delay parameter; and after receiving the detection signal, the delay parameter setting module determines, according to a correspondence between flash memory particles and delay parameters, a target delay parameter corresponding to the target flash memory particle, and adjusts a delay parameter of the signal delay module according to the target delay parameter, thereby ensuring the read-write accuracy.

Description

A flash memory controller, delay adjustment method and storage device

This application claims the priority of the Chinese patent application with the application number 202111604831.6 and the title of the invention "A Flash Memory Controller, Delay Adjustment Method, and Storage Device" filed with the China Patent Office on December 24, 2021, the entire contents of which are incorporated by reference incorporated in this application.

technical field

The invention relates to the storage field, in particular to a flash memory controller, a delay adjustment method and a storage device.

Background technique

NAND Flash (non-volatile flash memory) storage devices include NAND Flash particles for storing data and flash memory controllers for managing data stored in NAND Flash particles. As shown in Figure 1, the flash memory controller is connected to the NAND Flash particles through PCB (Printed Circuit Board, printed circuit board) traces, so as to realize the management of the data stored in the NAND Flash particles. It can be seen that the delay (delay) value on the read-write link between the flash memory controller and the NAND Flash particle is controlled by the delay value inside the NAND Flash particle, the delay value of the PCB trace between the NAND Flash particle and the flash memory controller, and the flash memory. The delay value of the internal link of the controller; among them, the delay value inside the NAND Flash particle is determined by the internal particle; the delay value of the PCB trace is determined by the length of the trace; the delay value of the internal link of the flash memory controller is determined by the internal circuit.

At present, the specific connection relationship between the flash memory controller and NAND Flash particles is shown in Figure 2. The connection links between the two include: DQS (Bi-directional Data Strobe, bidirectional data control pin) link, DQ ( Data input/output channel) link and DBI (Data Bus Inversion, data bus inversion) link; among them, DQ link is used to read and write NAND Flash particles, and the data signal transmitted on it is called DQ signal; DBI link The DBI signal transmitted above is used to indicate whether the current DQ signal needs to be reversed; the DQS signal transmitted on the DQS link is used as a reference signal for collecting DQ signals and DBI signals to determine when to collect DQ signals and DBI signals.

In order to ensure the correctness of data transmission between the flash memory controller and NAND Flash particles, it is necessary to ensure that the phase relationship between the DQS signal, DQ signal and DBI signal is within a correct range. Since the delay value inside the NAND Flash particle and the delay value of the planned PCB trace cannot be set, the phase relationship between the DQS signal, DQ signal and DBI signal can only be realized by setting the delay value of the internal link of the flash memory controller. , the accuracy of reading and writing data between the flash memory controller and NAND Flash particles can be guaranteed after setting the appropriate delay value of the internal link of the flash memory controller.

At present, after setting the delay value of the internal link of the flash memory controller, the delay value of the internal link of the flash memory controller is determined, and the flash memory controller uses this delay value to transmit data between NAND Flash particles. However, this method is only applicable to the case where the flash controller is connected to one NAND Flash particle. If the flash controller is connected to multiple NAND Flash particles (as shown in Figure 3), due to the link between the flash controller and different NAND Flash particles There are differences in the actual delay value, so the delay value originally set in the internal link of the flash memory controller may not be applicable to all connected NAND Flash particles, resulting in reduced read and write accuracy.

Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present.

Contents of the invention

The object of the present invention is to provide a flash memory controller, delay adjustment method and storage device, which can detect whether the flash memory particles operated by the flash memory controller are switched, and when detecting the switching of the flash memory particles operated by the flash memory controller, switch the flash memory controller to The delay parameters on the internal link are adjusted to the delay parameters applicable to the flash memory particles currently operated by the flash memory controller, so as to ensure the accuracy of reading and writing.

In order to solve the above technical problems, the present invention provides a flash memory controller, comprising:

A data drive module respectively connected to a plurality of flash memory particles, used to select a target flash memory particle from a plurality of said flash memory particles according to the current particle operation requirements, so as to perform read and write operations on said target flash memory particle;

A particle switching detection module connected to the data drive module, used to generate a detection that the flash memory particle representing the current operation is switched to the target flash memory particle when it detects that the data drive module is switched to the target flash memory particle for operation Signal;

The signal delay module arranged on the read-write link between the data drive module and the plurality of flash memory particles is used to transmit the data between the data drive module and the target flash memory particle according to the delay parameter currently set. Read and write operation signals for delayed transmission;

A delay parameter setting module respectively connected to the particle switching detection module and the signal delay module, used to determine the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter after receiving the detection signal corresponding target delay parameters, and adjust the delay parameters of the signal delay module according to the target delay parameters.

Optionally, the data drive module is respectively connected to the CE terminals of a plurality of the flash memory particles;

The data drive module is specifically configured to determine a target flash memory particle for pre-reading and writing operations from a plurality of flash memory particles according to the current particle operation requirements, and send a CE valid signal to the CE end of the target flash memory particle, so that the The target flash memory particle enters the working state.

Optionally, the particle switching detection module is respectively connected to multiple enabling links between the data driving module and the CE terminals of multiple flash memory particles;

The particle switching detection module is specifically configured to determine that the data drive module switches to the target flash memory particle for operation when detecting that the CE valid signal is started to be transmitted on the enabling link connected to the target flash memory particle.

Optionally, the particle switching detection module is internally provided with a CE register for recording the CE value corresponding to the flash memory particle last operated by the data drive module;

The granular switching detection module is specifically configured to determine the target enabled link that currently transmits the CE valid signal from among the plurality of enabled links, and determine according to the preset corresponding relationship between the enabled link and the CE value. The target CE value corresponding to the target enabling link, if the target CE value is inconsistent with the CE value currently stored in the CE register, it is determined that the data driver module is switched to connect to the target enabling link The flash memory particles are operated, and the CE register is updated based on the target CE value.

Optionally, the detection signal is a signal carrying the target CE value;

Then the delay parameter setting module is specifically used to determine the target delay parameter corresponding to the target CE value according to the preset corresponding relationship between the CE value and the delay parameter after receiving the detection signal, and according to the target delay parameter Adjust the delay parameters of the signal delay module.

Optionally, the particle switching detection module is further configured to generate a trigger signal before generating the detection signal after detecting that the data drive module switches to the target flash memory particle for operation;

Then the delay parameter setting module is also used to detect whether the trigger signal is received; if so, enter the step of parameter adjustment after receiving the detection signal; if not, do not enter after receiving the detection signal Steps for parameter tuning.

Optionally, the data drive module is further configured to generate a switching signal representing that the currently operating flash memory particle is switched to the target flash memory particle when selecting a target flash memory particle from a plurality of the flash memory particles to the particle switching detection module;

The particle switching detection module is specifically configured to determine that the data drive module switches to the target flash memory particle based on the switching signal to operate.

Optionally, the delay parameter setting module is internally provided with parameter registers for storing multiple delay parameter tables; wherein, the multiple delay parameter tables are used to record delay parameters applicable to multiple flash memory particles one by one;

The delay parameter setting module is specifically configured to, after receiving the detection signal, determine a target delay parameter table corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter table, and The delay parameters recorded in the parameter table adjust the delay parameters of the signal delay module.

Optionally, the read-write link includes a DQS input/output link, a DQ input/output link, and a DBI input/output link; each delay parameter recorded in the delay parameter table includes an input/output link of a DQS signal. Output delay parameters, input/output delay parameters of DQ signals and input/output delay parameters of DBI signals;

The signal delay module includes:

- a plurality of signal delay elements arranged on a plurality of said read-write links;

The delay parameter setting module is specifically configured to adjust the delay parameters of the plurality of signal delay elements in a one-to-one correspondence according to the plurality of delay parameters recorded in the target delay parameter table.

In order to solve the above technical problems, the present invention also provides a delay adjustment method, which is applied to a flash memory controller connected to multiple flash memory particles, including:

Selecting a target flash memory particle from a plurality of the flash memory particles according to the current particle operation requirements, so as to perform read and write operations on the target flash memory particle;

When it is detected that switching to the target flash memory particle is operated, the target delay parameter corresponding to the target flash memory particle is determined according to the preset corresponding relationship between the flash memory particle and the delay parameter;

Adjusting the delay parameter on the target read-write link corresponding to the target flash memory particle according to the target delay parameter, so as to delay transmission of the read-write operation signal on the target read-write link.

Optionally, the flash memory controller is respectively connected to the CE terminals of a plurality of the flash memory particles; the flash memory controller is internally provided with a CE register for recording the CE value corresponding to the flash memory particle last operated;

Then switch to the detection process of the target flash memory particles for operation, including:

Determining a target enabling link that currently transmits a CE valid signal from a plurality of enabling links connected one by one to the CE ends of a plurality of said flash memory particles;

determining a target CE value corresponding to the target enabled link according to a preset corresponding relationship between enabled links and CE values;

If the target CE value is inconsistent with the CE value currently stored in the CE register, determine to switch to the flash memory particle connected to the target enabling link for operation, and update the CE register based on the target CE value;

And determine the target delay parameter corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter, including:

The target delay parameter corresponding to the target CE value is determined according to the preset corresponding relationship between the CE value and the delay parameter.

In order to solve the above technical problem, the present invention also provides a storage device, which includes a plurality of flash memory particles and any one of the above flash memory controllers.

The invention provides a flash memory controller, which includes a data driving module, a particle switching detection module, a signal delay module and a delay parameter setting module. The data driving module is used to select the target flash memory particle from multiple flash memory particles according to the current particle operation requirements, so as to perform read and write operations on the target flash memory particle; the particle switching detection module is used to switch to the target flash memory particle for operation after the data driving module is detected , generate a detection signal that indicates that the currently operating flash memory particle switches to the target flash memory particle; the signal delay module is used to delay the transmission of the read and write operation signals between the data drive module and the target flash memory particle according to the currently set delay parameters; delay The parameter setting module is used to determine the target delay parameter corresponding to the target flash memory particle according to the preset correspondence between the flash memory particle and the delay parameter after receiving the detection signal, and adjust the delay parameter of the signal delay module according to the target delay parameter. It can be seen that the present application can detect whether the flash memory particles operated by the flash controller are switched, and when detecting the switching of the flash memory particles operated by the flash controller, adjust the delay parameter on the internal link of the flash controller to the current operation of the flash controller. The delay parameters applicable to flash memory particles ensure the accuracy of reading and writing.

The present invention also provides a delay adjustment method and a storage device, which have the same beneficial effect as the above-mentioned flash memory controller.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the prior art and the accompanying drawings that need to be used in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is the structural representation of a kind of NAND Flash storage device in the prior art;

Fig. 2 is a schematic diagram of the specific connection relationship between a flash memory controller and NAND Flash particles in the prior art;

Fig. 3 is the structural representation of a kind of flash memory controller connecting a plurality of NAND Flash particles in the prior art;

FIG. 4 is a schematic structural diagram of a flash memory controller provided by an embodiment of the present invention;

5 is a schematic structural diagram of a data drive module connected to CE terminals of multiple flash memory particles provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a flash memory controller provided by an embodiment of the present invention;

FIG. 7 is a delay parameter recording diagram of a delay parameter table corresponding to a plurality of flash memory particles provided by an embodiment of the present invention;

FIG. 8 is a flowchart of a delay adjustment method provided by an embodiment of the present invention;

FIG. 9 is a flow chart of detecting whether switching of flash memory particles in operation is provided by an embodiment of the present invention.

Detailed ways

The core of the present invention is to provide a flash memory controller, a delay adjustment method, and a storage device, which can detect whether the flash memory particles operated by the flash memory controller are switched, and when detecting that the flash memory particles operated by the flash memory controller are switched, switch the flash memory controller to The delay parameters on the internal link are adjusted to the delay parameters applicable to the flash memory particles currently operated by the flash memory controller, so as to ensure the accuracy of reading and writing.

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to FIG. 4 , which is a schematic structural diagram of a flash memory controller provided by an embodiment of the present invention.

The flash controller includes:

A data drive module 1 respectively connected to multiple flash memory particles is used to select a target flash memory particle from multiple flash memory particles according to the current particle operation requirements, so as to perform read and write operations on the target flash memory particle;

The particle switching detection module 2 connected with the data drive module 1 is used to generate a detection signal that the flash memory particle representing the current operation is switched to the target flash memory particle when it is detected that the data drive module 1 is switched to the target flash memory particle for operation;

The signal delay module 3 arranged on the read-write link between the data drive module 1 and a plurality of flash memory particles is used to transmit the read and write operation signals between the data drive module 1 and the target flash memory particles according to the delay parameter currently set. carry out delayed transmission;

The delay parameter setting module 4 connected with the particle switching detection module 2 and the signal delay module 3 respectively is used to determine the target delay parameter corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter after receiving the detection signal , and adjust the delay parameter of the signal delay module 3 according to the target delay parameter.

Specifically, the storage device of the present application includes a plurality of flash memory particles and a flash memory controller, and the flash memory controller includes a data drive module 1, a particle switching detection module 2, a signal delay module 3 and a delay parameter setting module 4, and its working principle is as follows:

The data driving module 1 is respectively connected to multiple flash memory particles, and the data driving module 1 can select a target flash memory particle from the multiple flash memory particles according to the current particle operation requirements, so as to perform read and write operations on the target flash memory particle. It should be noted that the data drive module 1 can only select one flash memory particle for read and write operations at a time, that is, the data drive module 1 cannot operate multiple flash memory particles at the same time. Specifically, it can be considered that the data drive module 1 operates each flash memory particle in a time-sharing manner.

Particle switching detection module 2 is connected with data driving module 1 and delay parameter setting module 4 respectively, and particle switching detection module 2 can generate the flash memory particle representing the current operation when switching to the target flash memory particle for operation when detecting that data driving module 1 is switched to The detection signal of the target flash memory particle, and the generated detection signal is sent to the delay parameter setting module 4.

The signal delay module 3 is arranged on the read-write link between the data drive module 1 and multiple flash memory particles. When the flash memory particle currently operated by the data drive module 1 is switched to the target flash memory particle, the signal delay module 3 can delay the transmission of the read and write operation signals between the data drive module 1 and the target flash memory particle according to the delay parameter currently set by itself . It can be understood that the signal delay module 3 is located in the flash memory controller, and the delay parameter of the signal delay module 3 determines the delay value of the internal link of the flash memory controller, so adjusting the delay parameter of the signal delay module 3 is equivalent to adjusting the internal link of the flash memory controller The delay value of the link, so that by adjusting the delay parameter of the signal delay module 3, the delay value of the internal link of the flash memory controller is suitable for the target flash memory particle of the current operation, which can well solve the problem of connecting multiple flash memory particles to the flash memory controller. The problem of inconsistent delay parameters.

The adjustment of the delay parameter of the signal delay module 3 is realized by the delay parameter setting module 4. After receiving the detection signal, the delay parameter setting module 4 can determine that the flash memory particle currently operated by the data drive module 1 is switched to the target flash memory particle based on the detection signal, and According to the preset corresponding relationship between flash memory particles and delay parameters (characterize the delay parameters of signal delay modules 3 applicable to different flash memory particles), determine the target delay parameters corresponding to the target flash memory particles, and then adjust the signal delay module 3 according to the target delay parameters. Delay parameters, so that the delay value of the internal link of the flash memory controller is suitable for the target flash memory particle currently operating, so as to ensure the accuracy of reading and writing.

It should be noted that, in general, multiple flash memory particles in the same storage device are the same type of flash memory particles. Of course, different types of flash memory particles (such as SLC (Single Level Cell, single-level cell), MLC (Multi-Level Cell, double-layer unit), TLC (Triple Level Cell, three-layer unit), QLC (Quad-Level Cell, four-layer unit) and other types), which belong to the mixed use of particles. The characteristics of each flash memory particle are different, so the working conditions are also different. In the case of low frequency and different working conditions, the same set of delay parameters can also work. In the case of high frequency, different delay parameters need to be set for each working condition. Guaranteed high precision and better matching.

It can be seen that the present application can detect whether the flash memory particles operated by the flash controller are switched, and when detecting the switching of the flash memory particles operated by the flash controller, adjust the delay parameter on the internal link of the flash controller to the current operation of the flash controller. The delay parameters applicable to flash memory particles ensure the accuracy of reading and writing. Moreover, the data drive module, particle switching detection module, signal delay module and delay parameter setting module of the present application are all pure hardware modules, which can effectively improve read and write performance without software intervention and adjustment.

On the basis of above-mentioned embodiment:

As an optional embodiment, the data drive module 1 is respectively connected to the CE terminals of a plurality of flash memory particles;

The data drive module 1 is specifically used to determine the target flash memory particle for pre-reading and writing operations from multiple flash memory particles according to the current particle operation requirements, and send a CE valid signal to the CE terminal of the target flash memory particle, so that the target flash memory particle enters the working state.

Specifically, as shown in Figure 5, the data driver module 1 of the present application is respectively connected to the CE (chip enable, chip enable) end of a plurality of flash memory particles, for the data driver module 1 to select the target flash memory particle from a plurality of flash memory particles use.

Based on this, the principle of data drive module 1 selecting a target flash memory particle from multiple flash memory particles is as follows: determine the target flash memory particle for pre-reading and writing operations from multiple flash memory particles according to the current particle operation requirements, and then report to the CE of the target flash memory particle The terminal sends a CE valid signal to make the target flash memory particles enter the working state, so as to realize the read and write operations on the target flash memory particles. It should be noted that the data drive module 1 only sends a CE valid signal to the CE terminal of one flash memory particle each time, that is, only one flash memory particle is selected for read and write operations each time.

More specifically, the CE effective signal is a low-level signal, and among multiple enable links between the data drive module 1 and the CE terminals of multiple flash memory particles, only one enable link transmits a low-level signal at a time , and the other enabling links transmit high-level signals, so that only one flash memory particle is selected for read and write operations at a time.

As an optional embodiment, the particle switching detection module 2 is respectively connected to multiple enabling links between the data drive module 1 and the CE ends of multiple flash memory particles;

The particle switching detection module 2 is specifically used to determine that the data drive module 1 is switched to the target flash memory particle for operation when it detects that the enabling link connected to the target flash memory particle starts to transmit the CE valid signal.

Specifically, the data drive module 1 is respectively connected to the CE terminals of a plurality of flash memory particles, and an enabling link is connected between the data drive module 1 and the CE terminals of each flash memory particle, and the particle switching detection module 2 is respectively connected to the data The driving module 1 is connected to multiple enabling links between the CE terminals of multiple flash memory particles, and then the particle switching detection module 2 determines that the data driving module 1 switches to the target flash memory particle for operation. When the enable link connected to the flash memory particle starts to transmit the CE valid signal, it is determined that the data driving module 1 is switched to the target flash memory particle for operation.

As an optional embodiment, the particle switching detection module 2 is internally provided with a CE register for recording the CE value corresponding to the flash memory particle last operated by the data drive module 1;

The granular switching detection module 2 is specifically used to determine the target enabled link that currently transmits a CE effective signal from multiple enabled links, and determine the corresponding relationship between the enabled link and the CE value according to the preset enabled link. If the target CE value is inconsistent with the CE value currently stored in the CE register, it is determined that the data driver module 1 switches to the flash memory particle connected to the target enabling link for operation, and updates the CE register based on the target CE value .

Specifically, an enabling link is connected between the data driving module 1 and the CE end of each flash memory particle, in order to distinguish multiple enabling links connected between the data driving module 1 and the CE ends of multiple flash memory particles , respectively define a CE value for each enabled link, and the CE values defined by different enabled links are different, such as the Nth enabled link connected between the data driver module 1 and the CE terminal of the Nth flash memory particle The corresponding CE value can be defined as N.

Based on this, the particle switching detection module 2 of the present application has a CE register inside, and the CE register records the CE value corresponding to the flash memory particle that the data drive module 1 operated last time. Then the particle switching detection module 2 determines that the data drive module 1 switches the flash memory particles to operate, specifically as follows:

The granular switching detection module 2 determines the target enabled link that currently transmits a valid CE signal from multiple enabled links, and determines the corresponding link to the target enabled link according to the preset corresponding relationship between the enabled link and the CE value. The target CE value, and then judge whether the target CE value is consistent with the CE value currently stored in the CE register. If the target CE value is consistent with the CE value currently stored in the CE register, it is determined that the data driver module 1 is not currently switching the flash memory particles; if the target If the CE value is inconsistent with the CE value currently stored in the CE register, it is determined that the data driver module 1 switches to the flash memory particle connected to the target enabling link for operation, and updates the CE register based on the target CE value for subsequent judgment of whether the data driver module 1 Toggle operation of flash particles used.

As an optional embodiment, the detection signal is a signal carrying a target CE value;

Then the delay parameter setting module 4 is specifically used to determine the target delay parameter corresponding to the target CE value according to the preset CE value and the delay parameter correspondence after receiving the detection signal, and adjust the delay of the signal delay module 3 according to the target delay parameter parameter.

Specifically, when the particle switching detection module 2 determines that the data drive module 1 is switched to the flash particle connected to the target enabling link for operation, it will generate a flash particle that represents the current operation to be switched to a flash particle connected to the target enabling link. and send the generated detection signal to the delay parameter setting module 4. Since the target CE value can indicate that the currently operating flash memory particle is switched to the flash memory particle connected to the target enabling link, the particle switching detection module 2 is determined to switch to the flash memory particle connected to the target enabling link for operation. When , the detection signal carrying the target CE value can be specifically generated, and the detection signal carrying the target CE value can be sent to the delay parameter setting module 4 .

Based on this, the delay parameter setting module 4 adjusts the delay parameter principle of the signal delay module 3 specifically as follows: after receiving the detection signal carrying the target CE value, according to the preset CE value and the delay parameter correspondence (representing that different CE values correspond to The delay parameters of the respective applicable signal delay modules 3 of the flash memory particles), determine the target delay parameters corresponding to the target CE value carried in the detection signal, and then adjust the delay parameters of the signal delay module 3 according to the target delay parameters, so that the flash memory controller The delay value of the internal link is applicable to the currently operating flash memory particles to ensure read and write accuracy.

As an optional embodiment, the particle switching detection module 2 is also used to generate a trigger signal after detecting that the data drive module 1 switches to the target flash memory particle for operation and before generating the detection signal;

Then the delay parameter setting module 4 is also used to detect whether a trigger signal is received; if so, enter the step of adjusting parameters after receiving the detection signal; if not, then do not enter the step of adjusting parameters after receiving the detection signal.

Further, after the particle switching detection module 2 of the present application detects that the data drive module 1 switches to the target flash memory particle for operation, it first sends a trigger signal to the delay parameter setting module 4, and then sends a detection signal to the delay parameter setting module 4. It is to first notify the delay parameter setting module 4 that it is about to enter the parameter adjustment process, and then send the detection signal that the flash memory particle representing the current operation is switched to the target flash memory particle to the delay parameter setting module 4, so that the detection signal received by the delay parameter setting module 4 The signal enters the parameter adjustment process to ensure the accuracy of parameter adjustment.

As an optional embodiment, the data drive module 1 is also used to generate a switching signal representing that the currently operating flash memory particle is switched to the target flash memory particle to the particle switching detection module 2 when selecting a target flash memory particle from a plurality of flash memory particles ;

The particle switching detection module 2 is specifically configured to determine based on the switching signal that the data driving module 1 switches to the target flash memory particle for operation.

Specifically, the particle switching detection module 2, in addition to the above-mentioned connection with multiple enabling links between the data drive module 1 and the CE terminals of multiple flash memory particles, starts to transmit CE by detecting the enabling link connected to the target flash memory particle. In addition to determining that the data driver module 1 is switched to the target flash memory particle for operation by a valid signal, there is another way to determine that the data driver module 1 is switched to the target flash memory particle for operation:

When the data driving module 1 selects a target flash memory particle from multiple flash memory particles, it also generates a switching signal indicating that the currently operating flash memory particle is switched to the target flash memory particle to the particle switching detection module 2 . After the particle switching detection module 2 receives the switching signal, it can directly determine based on the switching signal that the data driving module 1 switches to the target flash memory particle for operation.

As an optional embodiment, the delay parameter setting module 4 is internally provided with a parameter register for storing a plurality of delay parameter tables; wherein, a plurality of delay parameter tables are used to record the applicable delay parameters of a plurality of flash memory particles one by one;

The delay parameter setting module 4 is specifically used to determine the target delay parameter table corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter table after receiving the detection signal, and according to the delay parameter recorded in the target delay parameter table Adjust the delay parameters of the signal delay module 3.

Specifically, the delay parameter setting module 4 of the present application is provided with a parameter register inside, and a plurality of delay parameter tables are stored in the parameter register, and each delay parameter table is used to record a delay parameter applicable to a flash memory particle.

Based on this, the delay parameter setting module 4 adjusts the delay parameter principle of the signal delay module 3 specifically as follows: after receiving the detection signal, it is determined based on the detection signal that the flash memory particle currently operated by the data drive module 1 is switched to the target flash memory particle, and according to the predetermined The corresponding relationship between the flash memory particles and the delay parameter table (characterize the delay parameters of the signal delay module 3 applicable to different flash memory particles), determine the target delay parameter table corresponding to the target flash memory particle, and then follow the delay parameters recorded in the target delay parameter table Adjust the delay parameters of the signal delay module 3, so that the delay value of the internal link of the flash memory controller is suitable for the target flash memory particles currently operating, so as to ensure the accuracy of reading and writing.

Please refer to FIG. 6 , which is a schematic structural diagram of a flash memory controller provided by an embodiment of the present invention.

As an optional embodiment, the read-write link includes a DQS input/output link, a DQ input/output link, and a DBI input/output link; the delay parameters recorded in each delay parameter table include the input of the DQS signal /Output delay parameter, input/output delay parameter of DQ signal and input/output delay parameter of DBI signal;

Signal delay module 3 includes:

- a plurality of signal delay elements arranged on a plurality of read-write links;

The delay parameter setting module 4 is specifically configured to adjust the delay parameters of multiple signal delay elements according to the multiple delay parameters recorded in the target delay parameter table.

Specifically, the read-write link between the data drive module 1 of the present application and a plurality of flash memory particles includes a DQS input link, a DQS output link, a DQ input link, and a DQ output link (the DQ signal is an 8-bit signal, Expressed as DQ0-7, the DQ input link has a total of 8 input links, and each input link inputs one bit of data; the DQ output link has a total of 8 output links, and each output link outputs one bit of data ), DBI input link and DBI output link. As shown in Figure 7, the delay parameters recorded in each delay parameter table include the input delay parameter (input delay parameter) of the DQS signal, the output delay parameter (output delay parameter) of the DQS signal, and the input delay parameter of the DQ0-7 signal , DQ0-7 signal output delay parameters, DBI signal input delay parameters DBI signal output delay parameters. That is to say, in each delay parameter table, each read-write link corresponds to a delay parameter.

Based on this, the signal delay module 3 includes a plurality of signal delay elements (delay lines) that are arranged on multiple read-write links one by one, then the delay parameter setting module 4 adjusts the principle of the delay parameter of the signal delay module 3 specifically as follows: After receiving the detection signal, it is determined based on the detection signal that the flash memory particle currently operated by the data drive module 1 is switched to the target flash memory particle, and the target delay parameter table corresponding to the target flash memory particle is determined according to the preset corresponding relationship between the flash memory particle and the delay parameter table, Then adjust the delay parameters of multiple signal delay elements one by one according to the multiple delay parameters recorded in the target delay parameter table (specifically, write the delay parameter value to the signal delay element delay line to realize delay adjustment), so that the flash memory control The delay value of the internal link of the device is applicable to the target flash memory particles currently operating to ensure the accuracy of reading and writing.

Please refer to FIG. 8 , which is a flowchart of a delay adjustment method provided by an embodiment of the present invention.

This delay adjustment method is applied to a flash controller connected to multiple flash particles, including:

Step S1: Select a target flash memory particle from multiple flash memory particles according to the current particle operation requirements, so as to perform read and write operations on the target flash memory particle.

Step S2: When switching to the target flash memory particle for operation is detected, determine the target delay parameter corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter.

Step S3: Adjust the delay parameter on the target read-write link corresponding to the target flash memory particle according to the target delay parameter, so as to delay the transmission of the read-write operation signal on the target read-write link.

For the principle introduction of this embodiment, please refer to the above embodiment of the flash memory controller, and the present application will not repeat it here.

As an optional embodiment, the flash memory controller is respectively connected to the CE terminals of a plurality of flash memory particles; the flash memory controller is internally provided with a CE register for recording the CE value corresponding to the flash memory particle of the last operation;

Then switch to the detection process of the target flash memory particle for operation, including:

Determining a target enabling link that currently transmits a CE valid signal from a plurality of enabling links connected one by one to the CE ends of a plurality of flash memory particles;

Determine the target CE value corresponding to the target enabled link according to the preset corresponding relationship between the enabled link and the CE value;

If the target CE value is inconsistent with the CE value currently stored in the CE register, it is determined to switch to the flash memory particle connected to the target enabling link for operation, and update the CE register based on the target CE value;

As shown in FIG. 9 , how to detect whether the operating flash memory particles are switched is summarized. The specific detection principle can refer to the above-mentioned embodiment of the flash memory controller, and the present application will not repeat them here.

The present application also provides a storage device, including a plurality of flash memory particles and any one of the above flash memory controllers.

For the introduction of the storage device provided in this application, please refer to the above-mentioned embodiment of the flash memory controller, and this application will not repeat it here.

It should also be noted that in this specification, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is no such actual relationship or order between the operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

A kind of flash controller, is characterized in that, comprises:

A data drive module respectively connected to a plurality of flash memory particles, used to select a target flash memory particle from a plurality of said flash memory particles according to the current particle operation requirements, so as to perform read and write operations on said target flash memory particle;

A particle switching detection module connected to the data drive module, used to generate a detection that the flash memory particle representing the current operation is switched to the target flash memory particle when it detects that the data drive module is switched to the target flash memory particle for operation Signal;

The signal delay module arranged on the read-write link between the data drive module and the plurality of flash memory particles is used to transmit the data between the data drive module and the target flash memory particle according to the delay parameter currently set. Read and write operation signals for delayed transmission;

A delay parameter setting module respectively connected to the particle switching detection module and the signal delay module, used to determine the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter after receiving the detection signal corresponding target delay parameters, and adjust the delay parameters of the signal delay module according to the target delay parameters.
The flash memory controller according to claim 1, wherein the data driver module is respectively connected to CE terminals of a plurality of the flash memory particles;

The data drive module is specifically configured to determine a target flash memory particle for pre-reading and writing operations from a plurality of flash memory particles according to the current particle operation requirements, and send a CE valid signal to the CE end of the target flash memory particle, so that the The target flash memory particle enters the working state.
The flash memory controller according to claim 2, wherein the particle switching detection module is respectively connected to multiple enabling links between the data drive module and the CE ends of a plurality of the flash memory particles;

The particle switching detection module is specifically configured to determine that the data drive module switches to the target flash memory particle for operation when detecting that the CE valid signal is started to be transmitted on the enabling link connected to the target flash memory particle.
The flash memory controller according to claim 3, wherein the particle switching detection module is internally provided with a CE register for recording the corresponding CE value of the flash memory particle last operated by the data drive module;

The granular switching detection module is specifically configured to determine the target enabled link that currently transmits the CE valid signal from among the plurality of enabled links, and determine according to the preset corresponding relationship between the enabled link and the CE value. The target CE value corresponding to the target enabling link, if the target CE value is inconsistent with the CE value currently stored in the CE register, it is determined that the data driver module is switched to connect to the target enabling link The flash memory particles are operated, and the CE register is updated based on the target CE value.
The flash memory controller according to claim 4, wherein the detection signal is a signal carrying the target CE value;

Then the delay parameter setting module is specifically used to determine the target delay parameter corresponding to the target CE value according to the preset corresponding relationship between the CE value and the delay parameter after receiving the detection signal, and according to the target delay parameter Adjust the delay parameters of the signal delay module.
The flash memory controller according to claim 1, wherein the particle switching detection module is further configured to detect that the data drive module switches to the target flash memory particle for operation and before generating the detection signal , to generate a trigger signal;

Then the delay parameter setting module is also used to detect whether the trigger signal is received; if so, enter the step of parameter adjustment after receiving the detection signal; if not, do not enter after receiving the detection signal Steps for parameter tuning.
The flash memory controller according to claim 1, wherein the data drive module is further configured to generate a flash memory particle representing the current operation and switch to the target flash memory particle when selecting a target flash memory particle from a plurality of the flash memory particles The switching signal of the flash memory particles is sent to the particle switching detection module;

The particle switching detection module is specifically configured to determine that the data drive module switches to the target flash memory particle based on the switching signal to operate.
The flash memory controller according to any one of claims 1-7, wherein the delay parameter setting module is internally provided with parameter registers for storing a plurality of delay parameter tables; wherein, a plurality of delay parameter tables are used for Record the delay parameters applicable to a plurality of flash memory particles one by one;

The delay parameter setting module is specifically configured to, after receiving the detection signal, determine a target delay parameter table corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter table, and The delay parameters recorded in the parameter table adjust the delay parameters of the signal delay module.
The flash memory controller according to claim 8, wherein said read-write link comprises a DQS input/output link, a DQ input/output link and a DBI input/output link; each said delay parameter table The recorded delay parameters include the input/output delay parameters of the DQS signal, the input/output delay parameters of the DQ signal and the input/output delay parameters of the DBI signal;

The signal delay module includes:

- a plurality of signal delay elements arranged on a plurality of said read-write links;

The delay parameter setting module is specifically configured to adjust the delay parameters of the plurality of signal delay elements in a one-to-one correspondence according to the plurality of delay parameters recorded in the target delay parameter table.
A delay adjustment method, characterized in that it is applied to a flash memory controller connected to a plurality of flash memory particles, including:

Selecting a target flash memory particle from a plurality of the flash memory particles according to the current particle operation requirements, so as to perform read and write operations on the target flash memory particle;

When switching to the target flash memory particle for operation is detected, the target delay parameter corresponding to the target flash memory particle is determined according to the preset corresponding relationship between the flash memory particle and the delay parameter;

Adjusting the delay parameter on the target read-write link corresponding to the target flash memory particle according to the target delay parameter, so as to delay transmission of the read-write operation signal on the target read-write link.
The delay adjustment method according to claim 10, wherein the flash memory controller is respectively connected to the CE terminals of a plurality of the flash memory particles; the flash memory controller is internally provided with a corresponding flash memory particle for recording the last operation. The CE register of the CE value;

Then switch to the detection process of the target flash memory particles for operation, including:

Determining a target enabling link that currently transmits a CE valid signal from a plurality of enabling links connected one by one to the CE ends of a plurality of said flash memory particles;

determining a target CE value corresponding to the target enabled link according to a preset corresponding relationship between enabled links and CE values;

If the target CE value is inconsistent with the CE value currently stored in the CE register, determine to switch to the flash memory particle connected to the target enabling link for operation, and update the CE register based on the target CE value;

And determine the target delay parameter corresponding to the target flash memory particle according to the preset corresponding relationship between the flash memory particle and the delay parameter, including:

The target delay parameter corresponding to the target CE value is determined according to the preset corresponding relationship between the CE value and the delay parameter.
A storage device, characterized by comprising a plurality of flash memory particles and the flash memory controller according to any one of claims 1-9.