CN110991062B

CN110991062B - Method for realizing Verilog-A simulation model of OLED

Info

Publication number: CN110991062B
Application number: CN201911263604.4A
Authority: CN
Inventors: 宫雷雨; 张万鑫; 李翡; 刘伟平
Original assignee: Nanjing Huada Jiutian Technology Co ltd
Current assignee: Nanjing Huada Jiutian Technology Co ltd
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2022-07-15
Anticipated expiration: 2039-12-11
Also published as: CN110991062A

Abstract

A method for realizing a Verilog-A simulation model of an OLED comprises the following steps: 1) acquiring current-voltage and capacitance-voltage data of the device; 2) establishing a curve fitting polynomial according to the data; 3) establishing a Verilog-A expression to obtain a simulated OLED model; 4) respectively carrying out current-voltage and capacitance-voltage curve fitting; 5) and carrying out model verification. The method for realizing the Verilog-A simulation model of the OLED can effectively improve the simulation precision and the simulation efficiency of the OLED.

Description

Method for realizing Verilog-A simulation model of OLED

Technical Field

The invention relates to the technical field of device model development, in particular to a method for realizing a Verilog-A simulation model of an OLED.

Background

In the prior art, an OLED model is built by building a sub-circuit by using the existing combination of diode, resistor and capacitor models. However, the existing diode, resistor and capacitor models are not specially designed for the new device OLED, so that the accuracy of the simulation result of the OLED is limited, and the simulation time is long due to the combination of several devices. In addition, in the research of the literature, the current-voltage (I-V) characteristics of the OLED are of great interest, the capacitance-voltage (C-V) characteristics of the OLED are of less interest, and the C-V characteristics of the OLED are of great interest in practical requirements.

In the current industrial application, there is no compact model (compact model) integrated in the simulator, and the simulation of the sub-circuit model (subbckt model) of the existing OLED does not perform well in terms of accuracy and efficiency.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention aims to provide an implementation method of a Verilog-A simulation model of an OLED, which can effectively improve the simulation precision and the simulation efficiency of the OLED.

In order to achieve the above object, the method for implementing the Verilog-a simulation model of the OLED provided by the present invention includes the following steps:

1) acquiring current-voltage and capacitance-voltage data of the device;

2) establishing a curve fitting polynomial according to the data;

3) establishing a Verilog-A expression to obtain a simulated OLED model;

4) respectively carrying out current-voltage and capacitance-voltage curve fitting;

5) and carrying out model verification.

Further, the step 2) further includes removing bad points and noise points of the data.

Further, the step 2) further comprises,

dividing a current-voltage characteristic curve into a reverse region, a start region and a saturation region, and respectively establishing a fitting polynomial;

dividing the capacitance-voltage characteristic curve into a flat area, a rising area and a falling area, and respectively establishing a fitting polynomial.

Further, in the current-voltage characteristic curve,

taking the point of which the voltage is 0 as a starting boundary point of the reverse region and the starting region;

taking a point of second derivative of the current to the voltage as 0 as a saturation boundary point of the opening region and the saturation region;

the region with the voltage smaller than 0 is the reverse region, the region with the voltage larger than 0 and smaller than the saturation demarcation point is the starting region, and the region with the voltage larger than the saturation demarcation point is the saturation region.

Further, in the capacitance-voltage characteristic curve,

taking the point at which the voltage is 0 as a rising boundary point of the falling region and the rising region;

taking the point of the second derivative of the voltage obtained by the capacitor to be 0 as a flat dividing point of the ascending area and the flat area;

the area with the voltage smaller than 0 is the descending area, the area with the voltage larger than 0 and smaller than the flat boundary point is the ascending area, and the area with the voltage larger than the flat boundary point is the flat area.

Further, establishing the voltage-current characteristic curve fitting polynomial comprises the following steps:

setting the voltage as x and the current as y;

performing voltage-current polynomial fitting by using a least square method;

the coefficient of the voltage-current fitting polynomial is less than or equal to 3;

the voltage-current fitting polynomial is: y = k3x + k2x + k1x configured to + k0;

wherein the k0, k1, k2 and k3 are constants.

Further, before establishing the fitting polynomial, the current and voltage of the open region and the saturation region are logarithmized.

Further, a transition equation is established between each region, including:

P1*s1+P0=0 ①

P1*s2+P0=（f1（s2）+f2（s2））/2 - f1(s1) ②

calculating the P1 and the P0;

Q1*s3+Q0=0 ③

Q1*s2+Q0=（f1（s2）+f2（s2））/2 - f2(s3) ④

calculating the Q1 and the Q0 by using a simultaneous algorithm;

this gave f1(s2) + P1 × s2+ P0= f2(s2) + Q1 × s2+ Q0, ensuring continuity at point s 2.

Wherein f1 is a polynomial of a region preceding the breakpoint, f2 is a polynomial of a region succeeding the breakpoint, s1 is a minimum point of the voltage or the capacitance, s2 is the turn-on breakpoint or the rise breakpoint, and s3 is the saturation breakpoint or the flat breakpoint; p0, P1, Q0, Q1 are the coefficients of the transition equation independent variables, respectively.

Further, the polynomial of the region before the dividing point is F1(s) = F1(s) + P1 s + P0, and the polynomial of the region after the dividing point is F2(s) = F2(s) + Q1 s + Q0, where s is a voltage or a capacitance value.

Further, the step 4) further comprises representing the curve-fitting polynomial and the transition equation by the Verilog-a language.

Further, the step 4) further comprises respectively fitting each region according to the Verilog-a expression.

Further, the step 5) further includes simulating the model and outputting a verification result.

To achieve the above object, the present invention further provides a computer readable storage medium, on which computer instructions are stored, which when executed perform the steps of the method for implementing the Verilog-a simulation model of an OLED as described above.

In order to achieve the above object, the present invention further provides an apparatus for implementing a Verilog-a simulation model of an OLED, including a memory and a processor, where the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the above method steps for implementing the Verilog-a simulation model of an OLED.

The method for realizing the Verilog-A simulation model of the OLED has the following beneficial effects:

1) the method is more flexible, and the statements such as if-else and while in Verilog-A can be used for constructing a model to meet the requirements of new devices.

2) And the Verilog-A simulation model files are all visible, so that secondary modification is facilitated.

3) The simulation efficiency is higher, and the characteristic curve of the capacitance-voltage can be better fitted.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of a method for implementing Verilog-A simulation model of OLED according to the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Fig. 1 is a flowchart illustrating a method for implementing a Verilog-a simulation model of an OLED according to the present invention, and a method for implementing a Verilog-a simulation model of an OLED according to the present invention will be described in detail with reference to fig. 1.

First, in step 101, the current-voltage and capacitance-voltage data of the OLED device are measured. In the step, according to the physical characteristics of the OLED, the phenomenon that electrons and holes respectively start from a positive electrode and a negative electrode by using current and are injected into an organic film area between the two electrodes to generate light because of meeting is adopted, an actual OLED device is tested, and the data of current-voltage and capacitance-voltage are recorded through the measurement of electrical equipment.

At step 102, the test data is processed.

Preferably, the measured OLED device data is subjected to dead pixel removal and noise point removal.

At step 103, the test data is analyzed. In this step, the actual test data is observed and analyzed.

Preferably, for the I-V portion, the I-V characteristic is divided into three regions, reverse, open, and saturation.

Preferably, the region distinguishing method of I-V comprises: in the I-V characteristic curve, V =0 is used as a boundary point between the inversion region and the opening region, a point V1 where the second derivative of I with respect to V is 0 is used as a boundary point between the opening region and the saturation region, the region of V <0 is the inversion region, 0< V1 is the opening region, and the portion of V > V1 is the saturation region.

Preferably, the inversion region is fitted linearly, i.e. polynomial operations are performed.

Preferably, the method for establishing the polynomial in the reverse region comprises: 1) v is taken as x, I is taken as y; 2) performing polynomial fitting by using a least square method; 3) the coefficients of the polynomial < = 3. The polynomial expression is as follows: y = k3x + k2x + k1x configured to + k0; k0, k1, k2, k3 were calculated from the actually measured current-voltage data.

Preferably, the open region and the saturation region are subjected to first logarithmic operation and then linear fitting. In this step, the values of I, V are logarithmically fitted, and linear fitting is performed by polynomial fitting in the same manner as reverse region fitting.

Preferably, an overage equation is established between each region, ensuring continuity of the curve. In the step, the function of the transition equation is to ensure the continuity of the curves of two adjacent intervals, and the transition equation is established by taking the reverse region and the opening region as examples.

Preferably, let the polynomial of the inversion region be f1(x), the polynomial of the turn-on region be f2(x), and take three points x1 (the minimum point of x), x2 (the boundary point of the inversion region and the turn-on region), and x3 (the boundary point of the turn-on region and the saturation region), where x represents the voltage. The transition equation is established as follows:

a reverse region: p1 x1+ P0=0 (r)

P1*x2+P0=（f1（x2）+f2（x2））/2 - f1(x1) ②

Working out P1P 0.

An opening area: q1 x1+ Q0=0

Q1*x2+Q0=（f1（x2）+f2（x2））/2 -f2(x3) ④

And calculating Q1Q 0.

Wherein, P1, P0, Q1 and Q0 are coefficients of transition equation.

From the above calculations, the equation f1(x2) + P1 x2+ P0= f2(x2) + Q1 x2+ Q0 is obtained, thus ensuring continuity at point x 2. The final polynomials in the two regions of the reverse region and the open region are respectively: f1(x) = F1(x) + P1 x + P0, F2(x) = F2(x) + Q1 x + Q0.

Preferably, for the C-V part, C-V is converted into PF, and then the curve is divided into three areas, namely a flat area, an ascending area and a descending area.

Preferably, the region distinguishing method of the C-V part includes: in the C-V characteristic curve, V =0 is set as a boundary point between a falling region and a rising region, a point V1 at which the second derivative of C with respect to V is 0 is set as a boundary point between a rising region and a flat region, a region of V <0 is a falling region, 0< V1 is a rising region, and a portion of V > V1 is a flat region.

Preferably, each region in the C-V is subjected to linear fitting in the same way as the I-V, and then a transition equation is established between each region in the same way as the I-V, so that the continuity of the curve is ensured.

In step 104, a Verilog-A expression is established to obtain a simulated OLED model. In the step, establishing the Verilog-A expression comprises expressing an equation and a transition equation of polynomial operation by using a Verilog-A language, and obtaining a Verilog-A model of the OLED according to the Verilog-A expression. Verilog-A itself can use if-else, while, etc. statements, so it is more convenient to build the model. For example, if v <0, I (a, k) = k3v + k2v + k1v + k0 else … ….

At step 105, an I-V curve fit is performed.

Preferably, the reverse, turn-on and saturation regions of the current-voltage are fitted separately.

At step 106, a C-V curve fit is performed.

Preferably, the flat, rising and falling regions of the capacitance-voltage are fitted separately.

In step 107, model verification is performed. In this step, the model is used in a large-scale circuit to see whether the output result of this circuit simulation is consistent with the normal output result of the circuit.

The invention provides a method for realizing a Verilog-A simulation model of an OLED, which is characterized in that I-V and C-V characteristic curves are respectively fitted by two branches, so that the C-V does not influence the I-V when the I-V characteristic curve is adjusted, and the C-V characteristic curve is adjusted only after the I-V is determined, thereby reducing the fitting difficulty.

In order to achieve the above object, the present invention further provides an apparatus for implementing a Verilog-a simulation model of an OLED, including a memory and a processor, where the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the above steps of the method for implementing the Verilog-a simulation model of an OLED.

Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for realizing a Verilog-A simulation model of an OLED is characterized by comprising the following steps:

1) acquiring current-voltage and capacitance-voltage data of the device;

2) establishing a curve fitting polynomial according to the data;

said step 2) further comprises the step of,

dividing a current-voltage characteristic curve into a reverse region, a starting region and a saturation region, and respectively establishing a fitting polynomial;

dividing a capacitance-voltage characteristic curve into a flat area, a rising area and a falling area, and respectively establishing a fitting polynomial;

in the current-voltage characteristic curve,

taking a point of the second derivative of the current to the voltage as 0 as a saturation boundary point of the starting region and the saturation region;

the region with the voltage less than 0 is the reverse region, the region with the voltage greater than 0 and less than the saturation demarcation point is the starting region, and the region with the voltage greater than the saturation demarcation point is the saturation region;

in the capacitance-voltage characteristic curve in question,

taking the point of the second derivative of the voltage obtained by the capacitor to be 0 as a flat boundary point of the ascending area and the flat area;

the area with the voltage smaller than 0 is the descending area, the area with the voltage larger than 0 and smaller than the flat dividing point is the ascending area, and the area with the voltage larger than the flat dividing point is the flat area;

establishing a transition equation between each region, comprising:

P1*s1+P0=0 ①

P1*s2+P0=（f1（s2）+f2（s2））/2 - f1(s1) ②

working out the P1 and the P0;

Q1*s3+Q0=0 ③

Q1*s2+Q0=（f1（s2）+f2（s2））/2 - f2(s3) ④

calculating the Q1 and the Q0 by using a simultaneous algorithm;

f1(s2) + P1 × s2+ P0= f2(s2) + Q1 × s2+ Q0, ensuring continuity at point s 2;

wherein f1 is a polynomial corresponding to a region preceding a breakpoint, f2 is a polynomial corresponding to a region succeeding the breakpoint, s1 is a minimum point of the voltage or the capacitance, s2 is the start breakpoint or the rise breakpoint, and s3 is the saturation breakpoint or the flat breakpoint; p0, P1, Q0 and Q1 are coefficients of an independent variable of the transition equation respectively;

3) establishing a Verilog-A expression to obtain a simulated OLED model;

5) and carrying out model verification.

2. The method for implementing the Verilog-a simulation model of OLED according to claim 1, further comprising, before the step 2), removing bad points and noise points of the data.

3. The method of claim 1, wherein establishing the voltage-current characteristic curve fitting polynomial comprises:

setting the voltage as x and the current as y;

performing voltage-current polynomial fitting by using a least square method;

the voltage-current fitting polynomial is: y = k3x method of harvesting + k2x + k1 x-transforming + k0;

wherein the k0, k1, k2 and k3 are constants.

4. The method of claim 3, wherein before the establishing the fitting polynomial, the method further comprises logarithm of the current and the voltage of the turn-on region and the saturation region.

5. The method for implementing the Verilog-a simulation model of OLED according to claim 1, wherein the step 4) further comprises representing the curve-fitting polynomial and the transition equation in the Verilog-a language.

6. The method for implementing the Verilog-A simulation model of an OLED according to claim 1, wherein the step 4) further comprises respectively fitting an inversion region, a turn-on region, a saturation region, a flat region, a rise region and a fall region according to the Verilog-A expression.

7. The method for implementing the Verilog-a simulation model of OLED according to claim 1, wherein the step 5) is specifically to simulate the model and output a verification result.

8. A computer readable storage medium, on which computer instructions are stored, characterized in that said computer instructions when executed perform the method steps of implementing the Verilog-a simulation model of an OLED according to any one of claims 1 to 7.

9. An apparatus for implementing Verilog-a simulation model of OLED, comprising a memory and a processor, wherein the memory stores computer instructions running on the processor, and the processor executes the computer instructions to execute the method steps of implementing Verilog-a simulation model of OLED according to any one of claims 1 to 7.