CN110990318A - PCIe bus address expansion method, device, equipment and medium - Google Patents

PCIe bus address expansion method, device, equipment and medium Download PDF

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Publication number
CN110990318A
CN110990318A CN201911093364.8A CN201911093364A CN110990318A CN 110990318 A CN110990318 A CN 110990318A CN 201911093364 A CN201911093364 A CN 201911093364A CN 110990318 A CN110990318 A CN 110990318A
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bar
access
bus address
space
bus
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CN110990318B (en
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林涛
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Fuzhou Rockchip Electronics Co Ltd
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Fuzhou Rockchip Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The invention provides a PCIe bus address expansion method, a device, equipment and a medium, wherein the method comprises the following steps: when detecting that two BAR spaces or capacity spaces of two devices generate overlapping conflict of bus address ranges due to insufficient allocated bus addresses, recording the two BAR spaces or the capacity spaces of the two devices which generate the overlapping conflict through a table, allocating the bus address range which generates the overlapping conflict to one space, and forbidding the access of the other space. The invention can solve the problem of overlapping conflict distribution of the bus address range by dynamically expanding the PCIe bus address, and can not cause address waste of MMIO space.

Description

PCIe bus address expansion method, device, equipment and medium
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a PCIe bus address expansion method, apparatus, device, and medium.
Background
When a chip is designed, a bus mapping address needs to be reserved for PCIe (PCI express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard), a BAR (abbreviation of base address register) space of a downstream device is scanned, and a base address of a memory allocated to an EP end by an RC end is stored, and the bus mapping address is allocated from the reserved bus mapping address according to the size of the bus address in the BAR space. If the reservation of the bus mapping address during the chip design is insufficient, the BAR space address of the downstream equipment can not be allocated. If the reservation is too large, it will result in wasted addresses for MMIO space. In order to solve the problem, the scheme designs a mechanism capable of dynamically expanding PCIe bus addresses.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a PCIe bus address expansion method, apparatus, device, and medium, which can solve the problem of overlapping and conflicting allocation of bus address ranges by dynamically expanding PCIe bus addresses, and also will not cause address waste in MMIO (memory map input output, which is used for mapping each controller and memory of a system) space.
In a first aspect, the present invention provides a PCIe bus address expansion method, including at least one of an intra-device bus address expansion and an inter-device bus address expansion:
the bus address expansion in the device is as follows: when the device is detected to have bus address range overlapping conflict distributed by two BAR spaces, recording the two BAR spaces with overlapping conflict, distributing the bus address range with overlapping conflict to one of the two BAR spaces, and forbidding the access of the other BAR space, when one BAR space needs to be accessed, firstly, inquiring the record to know the other BAR space with overlapping conflict with the BAR space to be accessed, judging whether the access of the other BAR space is forbidden, if so, directly accessing, if not, forbidding the access of the other BAR space, distributing the bus address range with overlapping conflict to the BAR space needing to be accessed, and then accessing;
the inter-device bus address extension is: when detecting that the bus address range overlapping conflict occurs in the capacity space of the two devices, recording the two devices which have the overlapping conflict, allocating the bus address range overlapping conflict to one of the devices, and forbidding the access of the other device, when needing to access one of the devices, firstly, inquiring the record to know that the device which has the overlapping conflict with the device to be accessed is the other device, judging whether the access of the other device is forbidden, if so, directly accessing, if not, firstly, forbidding the access of the other device, allocating the bus address range overlapping conflict to the second device, and then, accessing.
In a second aspect, the present invention provides a PCIe bus address expansion apparatus, including at least one of an intra-device bus address expansion module and an inter-device bus address expansion module:
the device internal bus address expansion module is used for expanding the internal bus address of the BAR space of the device, and the specific expansion process is as follows: when the device is detected to have bus address range overlapping conflict distributed by two BAR spaces, recording the two BAR spaces with overlapping conflict, distributing the bus address range with overlapping conflict to one of the two BAR spaces, and forbidding the access of the other BAR space, when one BAR space needs to be accessed, firstly, inquiring the record to know the other BAR space with overlapping conflict with the BAR space to be accessed, judging whether the access of the other BAR space is forbidden, if so, directly accessing, if not, forbidding the access of the other BAR space, distributing the bus address range with overlapping conflict to the BAR space needing to be accessed, and then accessing;
the inter-device bus address expansion module is used for expanding the internal bus address of the inter-device total capacity space, and the specific expansion process is as follows: when detecting that the bus address range overlapping conflict occurs in the capacity space of the two devices, recording the two devices which have the overlapping conflict, allocating the bus address range overlapping conflict to one of the devices, and forbidding the access of the other device, when needing to access one of the devices, firstly, inquiring the record to know that the device which has the overlapping conflict with the device to be accessed is the other device, judging whether the access of the other device is forbidden, if so, directly accessing, if not, firstly, forbidding the access of the other device, allocating the bus address range overlapping conflict to the second device, and then, accessing.
In a third aspect, the present invention provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of the first aspect when executing the program.
In a fourth aspect, the invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method of the first aspect.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages: when the overlapping conflict of bus address ranges caused by insufficient allocated bus addresses in two BAR spaces or two equipment capacity spaces is detected, the table records the two BAR spaces or the two equipment capacity spaces with the overlapping conflict, the bus address range with the overlapping conflict is allocated to one space, the access of the other space is forbidden, when one space needs to be accessed, the table is inquired to know which two spaces the overlapping conflict occurs, and the bus address range with the overlapping conflict is allocated to the space needing to be accessed by forbidding the access of the other space which is not accessed currently, so that the dynamic expansion is realized, the problem of overlapping conflict allocation of the bus address ranges can be solved, and the address waste of an MMIO space can not be caused.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a bus address expansion state structure in the device according to the present invention;
FIG. 2 is a schematic diagram of an inter-device bus address expansion state structure according to the present invention;
FIG. 3 is a flow chart illustrating bus address expansion in a device according to a method of an embodiment of the present invention;
FIG. 4 is a flowchart illustrating inter-device bus address expansion according to a method of one embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an apparatus according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to a third embodiment of the invention;
fig. 7 is a schematic structural diagram of a medium according to a fourth embodiment of the present invention.
Detailed Description
The embodiments of the present application provide a PCIe bus address expansion method, apparatus, device, and medium, which can dynamically expand a PCIe bus address, and not only can solve the problem of overlapping and conflicting allocation of bus address ranges, but also can not cause address waste of an MMIO space.
The technical scheme in the embodiment of the application has the following general idea: when detecting that two BAR spaces or capacity spaces of two devices generate overlapping conflict of bus address ranges due to insufficient allocated bus addresses, recording the two BAR spaces or the capacity spaces of the two devices which generate the overlapping conflict through a table, allocating the bus address range which generates the overlapping conflict to one space, and forbidding the access of the other space.
Before describing the specific embodiments, the specific situations of the system framework corresponding to the method of the embodiment of the present application are described:
as shown in fig. 1, the system for bus address expansion in a device includes a chip and a device: when the chip reserves a bus address range, the address is from 0 to D; and a single device downstream includes multiple BAR spaces, each BAR space requiring a total amount exceeding the total capacity of the reserved bus addresses 0-D of the chip.
As shown in fig. 2, a system for inter-device bus address expansion includes a chip, a PCIe controller, and a plurality of devices: when the chip reserves a bus address range, the address is from 0 to B; the total space requirement of the device 1 is from address 0 to address a, the total space requirement of the device 2 is from address 0 to address C, and the total space requirement of the device 3 is from address C to address B. The total amount of space required by the individual devices exceeds the total capacity of the reserved bus addresses 0-B of the chip.
Example one
The embodiment provides a PCIe bus address expansion method, which comprises at least one of intra-device bus address expansion or inter-device bus address expansion:
as shown in fig. 3, the intra-device bus address extension is: when a chip bus address is insufficient to reserve, when the chip bus address is allocated to a BAR space of a downstream device, bus address ranges allocated by two BAR spaces overlap conflict, the two BAR spaces with the overlap conflict are recorded by a table, the bus address range with the overlap conflict is allocated to one of the two BAR spaces, access of the other BAR space is forbidden, when one BAR space needs to be accessed, the other BAR space with the overlap conflict with the BAR space to be accessed is known by inquiring the table, whether access of the other BAR space is forbidden or not is judged, if the access is forbidden, direct access is carried out, if the access is not forbidden, access of the other BAR space is forbidden, the bus address range with the overlap conflict is allocated to the BAR space needing to be accessed, and then access is carried out;
in the bus address extension in the device, when the bus address ranges allocated by the two BAR spaces have overlapping conflict, the EP end detects the illegal address allocation with the overlapping conflict according to the protocol, thereby forbidding the access of the other BAR space. The forbidding is realized by a PCIe BAR address enabling unit of the EP terminal, a base address enabling (BAR enable) bit is added in an address unit of each BAR space of a PCIe controller of the EP terminal, and the BAR space to be accessed and the BAR space to be forbidden are switched by setting the value of the base address enabling bit. Such as: when a PCIe BAR address enables a certain BAR space, the PCIe controller sets the enabling bit of the base address corresponding to the BAR space to be 1, otherwise, the enabling bit is set to be 0; once the accessed BAR space needs to be switched, the base address enable bit of a different BAR space is operated, which is 1 to access the BAR space and 0 to another conflicting BAR.
As shown in connection with FIG. 1, for a device, BAR1 assigns addresses of 0-A, BAR2 assigns addresses of A-B, BAR3 assigns addresses of C-D because of insufficient space left; at this time, the addresses of BAR2 and BAR3 are substantially overlapped, i.e., the address space between C-B, and such illegal address allocation is detected according to the protocol EP. At this time, the access of BAR3 can be prohibited to table-record the addresses allocated by the software, but the addresses of BAR1 and BAR2 are actually allocated to the BAR1 and BAR2 of the device in the hardware. When the RC end needs to access the BAR3, the lookup table can know that illegal address allocation exists in the BAR2 and the BAR3, so that in order to realize the access of the BAR3, the access of the BAR2 needs to be prohibited firstly, the C-D is enabled and allocated to the BAR3, and the RC end software is enabled to finish the access of the BAR 3. And the like for all kinds of conditions.
In addition, the table for recording two BAR spaces with overlapping conflicts is stored in the memory, and the memory for storing the table needs to be uncached and aligned in a dword mode.
As shown in fig. 4, the inter-device bus address extension is: when the chip bus address is insufficient to reserve, the bus address range overlapping conflict occurs when the capacity space is allocated to two downstream devices, the two devices with the overlapping conflict are recorded by a table, the bus address range overlapping the conflict is allocated to one device, the access of the other device is forbidden, when one device needs to be accessed, the other device which has the overlapping conflict with the device to be accessed is known by inquiring the table, whether the access of the other device is forbidden is judged, if the access of the other device is forbidden, the access of the other device is directly forbidden, if the access of the other device is not forbidden, the bus address range overlapping the conflict is allocated to the second device, and then the access is carried out.
In the inter-device bus address extension, the prohibition of access of one of the devices is realized by a PCIe controller, a bus prohibition (BD) attribute is added to each outbend configuration in an address translation layer (ALT) of the PCIe controller, when accessing the first device, the PCIe controller identifies that the bus is prohibited from the first device, and automatically closes all BAR spaces of the second device, and when the access is completed and the second device needs to be accessed, the PCIe controller identifies that the bus prohibition attribute is the second device, and automatically closes all BAR spaces of the first device;
after the BAR space of a device is disabled, access to the device is stored in a reserved error packet (i.e., replay buffer) of the PCIe controller, and once access to another device is completed, the PCIe controller detects that there is a stored access to the BAR of the back-disabled device in the reserved error packet, automatically enables the BAR of the device, allocates the conflicting address space to it, and disables access to the BAR of the device whose address conflicts with it.
In the inter-device bus address expansion, the table is stored in a memory and arranged according to a certain data format, the memory physical address of the table is configured to the PCIe controller, and the PCIe controller executes an expansion process fully automatically.
Referring to fig. 2, since the chip bus address is not reserved enough, once the address conflict spans different devices, for example, the total capacity of device 1 overlaps the total capacity of device 2 by a-C part, we need to add a bus disable attribute to each outbend configuration by the Address Translation Layer (ATL) of the PCIe controller. When the RC end accesses the device 1, the PCIe controller recognizes the bus disable attribute as the device 1, and automatically closes all BAR spaces of the device 2. Once access is complete and device 2 needs to be accessed, the PCIe controller recognizes the bus disable attribute as device 2 and automatically closes all BAR space of device 1. It should be noted that after the BAR space of a certain device is disabled, the access issued by the RC terminal for the device is not issued, but is stored in the storage error packet of the controller. Once another device access is complete, the controller detects a stored BAR access to the disabled device in the save error packet, automatically enables this BAR, assigns the conflicting address space to it, and disables the device with which the address conflicts. The division and sliding of overlapping windows can be controlled by software.
Based on the same inventive concept, the application also provides a device corresponding to the method in the first embodiment, which is detailed in the second embodiment.
Example two
In this embodiment, an CIe bus address expansion apparatus is provided, as shown in fig. 5, including at least one of an intra-device bus address expansion module and an inter-device bus address expansion module:
the device internal bus address expansion module is used for expanding the internal bus address of the BAR space of the device, and the specific expansion process is as follows: when a chip bus address is insufficient to reserve, when the chip bus address is allocated to a BAR space of a downstream device, bus address ranges allocated by two BAR spaces overlap conflict, the two BAR spaces with the overlap conflict are recorded by a table, the bus address range with the overlap conflict is allocated to one of the two BAR spaces, access of the other BAR space is forbidden, when one BAR space needs to be accessed, the other BAR space with the overlap conflict with the BAR space to be accessed is known by inquiring the table, whether access of the other BAR space is forbidden or not is judged, if the access is forbidden, direct access is carried out, if the access is not forbidden, access of the other BAR space is forbidden, the bus address range with the overlap conflict is allocated to the BAR space needing to be accessed, and then access is carried out;
in the bus address extension in the device, when there is an overlapping conflict of the bus address ranges allocated by the two BAR spaces, the EP detects an illegal address allocation with the overlapping conflict according to the protocol, thereby prohibiting an access of another BAR space.
The inter-device bus address expansion module is used for expanding the internal bus address of the inter-device total capacity space, and the specific expansion process is as follows: when the chip bus address is insufficient to reserve, the bus address range overlapping conflict occurs when the capacity space is allocated to two downstream devices, the two devices with the overlapping conflict are recorded by a table, the bus address range overlapping the conflict is allocated to one device, the access of the other device is forbidden, when one device needs to be accessed, the other device which has the overlapping conflict with the device to be accessed is known by inquiring the table, whether the access of the other device is forbidden is judged, if the access of the other device is forbidden, the access of the other device is directly forbidden, if the access of the other device is not forbidden, the bus address range overlapping the conflict is allocated to the second device, and then the access is carried out.
In the inter-device bus address extension, forbidding access of one device is realized through a PCIe controller, a bus forbidding attribute is added to each outbound configuration in an address translation layer of the PCIe controller, when the first device is accessed, the PCIe controller identifies the bus forbidding attribute as the first device and automatically closes all BAR spaces of the second device, and once the access is completed and the second device needs to be accessed, the PCIe controller identifies the bus forbidding attribute as the second device and automatically closes all BAR spaces of the first device;
after the BAR space of a device is disabled, access to the device is stored in a save error packet of the PCIe controller, and upon completion of access to another device, the PCIe controller detects that there is a stored access to the BAR of the back-disabled device in the save error packet, automatically enables the BAR of the device, assigns the conflicting address space to it, and disables access to the BAR of the device whose address conflicts with it.
In the inter-device bus address expansion, the table is stored in a memory and arranged according to a certain data format, the memory physical address of the table is configured to the PCIe controller, and the PCIe controller executes an expansion process fully automatically.
Since the apparatus described in the second embodiment of the present invention is an apparatus used for implementing the method of the first embodiment of the present invention, based on the method described in the first embodiment of the present invention, a person skilled in the art can understand the specific structure and the deformation of the apparatus, and thus the details are not described herein. All the devices adopted in the method of the first embodiment of the present invention belong to the protection scope of the present invention.
Based on the same inventive concept, the application provides an electronic device embodiment corresponding to the first embodiment, which is detailed in the third embodiment.
EXAMPLE III
The present embodiment provides an electronic device, as shown in fig. 6, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, any implementation manner of the first embodiment may be implemented.
Since the electronic device described in this embodiment is a device used for implementing the method in the first embodiment of the present application, based on the method described in the first embodiment of the present application, a specific implementation of the electronic device in this embodiment and various variations thereof can be understood by those skilled in the art, and therefore, how to implement the method in the first embodiment of the present application by the electronic device is not described in detail herein. The equipment used by those skilled in the art to implement the methods in the embodiments of the present application is within the scope of the present application.
Based on the same inventive concept, the application provides a storage medium corresponding to the fourth embodiment, which is described in detail in the fourth embodiment.
Example four
The present embodiment provides a computer-readable storage medium, as shown in fig. 7, on which a computer program is stored, and when the computer program is executed by a processor, any one of the embodiments can be implemented.
The technical scheme provided in the embodiment of the application at least has the following technical effects or advantages: the method, the device, the equipment and the medium provided by the embodiment of the application realize the dynamic expansion of the bus address of the chip, can solve the problem of overlapping and conflicting distribution of the bus address range, and can not cause the address waste of an MMIO space.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims (10)

1. A PCIe bus address expansion method, characterized in that: including at least one of an intra-device bus address extension or an inter-device bus address extension:
the bus address expansion in the device is as follows: when the device is detected to have bus address range overlapping conflict distributed by two BAR spaces, recording the two BAR spaces with overlapping conflict, distributing the bus address range with overlapping conflict to one of the two BAR spaces, and forbidding the access of the other BAR space, when one BAR space needs to be accessed, firstly, inquiring the record to know the other BAR space with overlapping conflict with the BAR space to be accessed, judging whether the access of the other BAR space is forbidden, if so, directly accessing, if not, forbidding the access of the other BAR space, distributing the bus address range with overlapping conflict to the BAR space needing to be accessed, and then accessing;
the inter-device bus address extension is: when detecting that the bus address range overlapping conflict occurs in the capacity space of the two devices, recording the two devices which have the overlapping conflict, allocating the bus address range overlapping conflict to one of the devices, and forbidding the access of the other device, when needing to access one of the devices, firstly, inquiring the record to know that the device which has the overlapping conflict with the device to be accessed is the other device, judging whether the access of the other device is forbidden, if so, directly accessing, if not, firstly, forbidding the access of the other device, allocating the bus address range overlapping conflict to the second device, and then, accessing.
2. The PCIe bus address expansion method of claim 1, wherein:
in the bus address expansion in the equipment, when the bus address ranges allocated by two BAR spaces have overlapping conflict, the EP end detects the illegal address allocation with the overlapping conflict according to a protocol, thereby forbidding the access of the other BAR space;
the forbidding is realized by a PCIe BAR address enabling unit of an EP terminal, a base address enabling bit is added in an address unit of each BAR space of a PCIe controller of the EP terminal, and the BAR space to be accessed and the BAR space to be forbidden are switched by setting the value of the base address enabling bit.
3. The PCIe bus address expansion method of claim 1, wherein:
in the inter-device bus address extension, forbidding access of one device is realized through a PCIe controller, a bus forbidding attribute is added to each outbound configuration in an address translation layer of the PCIe controller, when the first device is accessed, the PCIe controller identifies the bus forbidding attribute as the first device and automatically closes all BAR spaces of the second device, and once the access is completed and the second device needs to be accessed, the PCIe controller identifies the bus forbidding attribute as the second device and automatically closes all BAR spaces of the first device;
after the BAR space of a device is disabled, access to the device is stored in a save error packet of the PCIe controller, and upon completion of access to another device, the PCIe controller detects that there is a stored access to the BAR of the back-disabled device in the save error packet, automatically enables the BAR of the device, assigns the conflicting address space to it, and disables access to the BAR of the device whose address conflicts with it.
4. The PCIe bus address expansion method of claim 3, wherein:
the recording is performed in a form of a table, in the inter-device bus address expansion, the table is stored in a memory and arranged according to a certain data format, the memory physical address of the table is configured to the PCIe controller, and the PCIe controller fully automatically executes the expansion process.
5. A PCIe bus address expansion apparatus, characterized in that: the device comprises at least one of an intra-device bus address expansion module and an inter-device bus address expansion module:
the device internal bus address expansion module is used for expanding the internal bus address of the BAR space of the device, and the specific expansion process is as follows: when the device is detected to have bus address range overlapping conflict distributed by two BAR spaces, recording the two BAR spaces with overlapping conflict, distributing the bus address range with overlapping conflict to one of the two BAR spaces, and forbidding the access of the other BAR space, when one BAR space needs to be accessed, firstly, inquiring the record to know the other BAR space with overlapping conflict with the BAR space to be accessed, judging whether the access of the other BAR space is forbidden, if so, directly accessing, if not, forbidding the access of the other BAR space, distributing the bus address range with overlapping conflict to the BAR space needing to be accessed, and then accessing;
the inter-device bus address expansion module is used for expanding the internal bus address of the inter-device total capacity space, and the specific expansion process is as follows: when detecting that the bus address range overlapping conflict occurs in the capacity space of the two devices, recording the two devices which have the overlapping conflict, allocating the bus address range overlapping conflict to one of the devices, and forbidding the access of the other device, when needing to access one of the devices, firstly, inquiring the record to know that the device which has the overlapping conflict with the device to be accessed is the other device, judging whether the access of the other device is forbidden, if so, directly accessing, if not, firstly, forbidding the access of the other device, allocating the bus address range overlapping conflict to the second device, and then, accessing.
6. The PCIe bus address expansion apparatus of claim 5, wherein: in the bus address extension in the equipment, when the bus address ranges allocated by two BAR spaces have overlapping conflict, the EP end detects the illegal address allocation with the overlapping conflict according to the protocol, thereby forbidding the access of the other BAR space.
7. The PCIe bus address expansion apparatus of claim 5, wherein: in the inter-device bus address extension, forbidding access of one device is realized through a PCIe controller, a bus forbidding attribute is added to each outbound configuration in an address translation layer of the PCIe controller, when the first device is accessed, the PCIe controller identifies the bus forbidding attribute as the first device and automatically closes all BAR spaces of the second device, and once the access is completed and the second device needs to be accessed, the PCIe controller identifies the bus forbidding attribute as the second device and automatically closes all BAR spaces of the first device;
after the BAR space of a device is disabled, access to the device is stored in a save error packet of the PCIe controller, and upon completion of access to another device, the PCIe controller detects that there is a stored access to the BAR of the back-disabled device in the save error packet, automatically enables the BAR of the device, assigns the conflicting address space to it, and disables access to the BAR of the device whose address conflicts with it.
8. The PCIe bus address expansion apparatus of claim 5, wherein: the recording is carried out through a table, in the inter-device bus address expansion, the table is stored in a memory and is arranged according to a certain data format, the memory physical address of the table is configured to the PCIe controller, and the PCIe controller fully automatically executes the expansion process.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 4 when executing the program.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 4.
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Cited By (2)

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