CN111581139A

CN111581139A - Compatible processing method, device and equipment of PCIe equipment and storage medium

Info

Publication number: CN111581139A
Application number: CN202010372409.1A
Authority: CN
Inventors: 孙旭; 莫德欠; 霍文龙
Original assignee: Zhejiang Uniview Technologies Co Ltd
Current assignee: Zhejiang Uniview Technologies Co Ltd
Priority date: 2020-05-06
Filing date: 2020-05-06
Publication date: 2020-08-25
Anticipated expiration: 2040-05-06
Also published as: CN111581139B

Abstract

The embodiment of the invention discloses a compatible processing method, a device, equipment and a storage medium of PCIe equipment. The method comprises the following steps: determining a target address bit width and a target Bar space distributed to target PCIe end equipment according to an address bit width supported by PCIe root equipment and an address bit width supported by the target PCIe end equipment; performing PCIe compatible configuration according to the allocated target address bit width and the target Bar space to construct a target PCIe link between the PCIe root device and the target PCIe end device; and sending a data packet to the target PCIe terminal equipment by adopting a target PCIe link. By adopting the scheme, when the PCIe equipment is initialized, the PCIe root equipment and the target PCIe end equipment in the PCIe bus can be subjected to compatible processing so as to construct a compatible PCIe link, and normal communication between RC root equipment with different address bit widths and EP end equipment is ensured, so that functions of upgrading the EP end equipment, reading an equipment register and the like can be realized in the subsequent process.

Description

Compatible processing method, device and equipment of PCIe equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of computers, in particular to a compatible processing method, a compatible processing device and a compatible processing storage medium for PCIe equipment.

Background

PCIe is a high-speed serial computer expansion bus standard, and belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. In practical application, PCIe devices are connected through a PCIe link, but RC devices with different address bit widths are incompatible with EP devices, which may cause the RC devices and the EP devices to be unable to normally communicate and complete corresponding service functions. However, if the PCIe link is not used for transmission but other general interfaces are used, not only the hardware cost is high, but also the transmission speed of the other general interfaces is relatively slow, which affects the data transmission speed. Therefore, there is a need to solve the above-mentioned incompatibility problem urgently.

Disclosure of Invention

In view of the foregoing problems, embodiments of the present invention provide a method, an apparatus, a device, and a storage medium for compatible processing of PCIe devices, so as to implement communication compatibility between an RC device and an EP device.

In a first aspect, an embodiment of the present invention provides a compatible processing method for a PCIe device, where the compatible processing method is executed by a PCIe root device, and the PCIe root device is associated with at least one target PCIe end device, including:

determining a target address bit width and a target Bar space distributed to target PCIe end equipment according to an address bit width supported by PCIe root equipment and an address bit width supported by the target PCIe end equipment;

performing PCIe compatible configuration according to the allocated target address bit width and the target Bar space to construct a target PCIe link between the PCIe root device and the target PCIe end device;

and sending a data packet to the target PCIe terminal equipment by adopting a target PCIe link.

In a second aspect, an embodiment of the present invention further provides a compatible processing apparatus for a PCIe device, configured in a PCIe root device, where the PCIe root device is associated with at least one target PCIe end device, and the apparatus includes:

the target allocation module is used for determining a target address bit width and a target Bar space allocated to the target PCIe end equipment according to the address bit width supported by the PCIe root equipment and the address bit width supported by the target PCIe end equipment;

the compatible configuration module is used for carrying out PCIe compatible configuration according to the allocated target address bit width and the target Bar space so as to construct a target PCIe link between the PCIe root equipment and the target PCIe end equipment;

and the data packet sending module is used for sending the data packet to the target PCIe terminal equipment by adopting the target PCIe link.

In a third aspect, an embodiment of the present invention further provides an electronic device, including:

one or more processors;

storage means for storing one or more programs;

the one or more programs are executed by the one or more processors so that the one or more processors implement a compatible processing method for a PCIe device as any of the embodiments of the present invention.

In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the compatible processing method for the PCIe device as described in any of the embodiments of the present invention.

The embodiment of the invention provides a compatible processing method of PCIe equipment, which can allocate proper target address bit width and target Bar space to target PCIe end equipment according to address bit width supported by PCIe root equipment and address bit width supported by the target PCIe end equipment, and then carry out PCIe compatible configuration according to the target address bit width and the target Bar space so as to construct a target PCIe link. By adopting the scheme, when the PCIe equipment is initialized, the PCIe root equipment and the target PCIe end equipment in the PCIe bus can be subjected to compatible processing so as to construct a compatible PCIe link, and normal communication between RC root equipment with different address bit widths and EP end equipment is ensured, so that functions of upgrading the EP end equipment, reading an equipment register and the like can be realized in the subsequent process.

The above summary of the present invention is merely an overview of the technical solutions of the present invention, and the present invention can be implemented in accordance with the content of the description in order to make the technical means of the present invention more clearly understood, and the above and other objects, features, and advantages of the present invention will be more clearly understood.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a PCIe protocol provided in an embodiment of the present invention;

fig. 2 is a flowchart of a method for processing compatibility of a PCIe device provided in the embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a format of a TLP packet with a 32-bit address bit width provided in the embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a format of a TLP packet with 64-bit address bit width provided in the embodiment of the present invention;

FIG. 5 is a flow chart of another PCIe device compatibility processing method provided in the embodiments of the present invention;

FIG. 6 is a flow chart of a method for processing compatibility of a PCIe device provided in the embodiment of the present invention;

fig. 7 is a block diagram of a compatible processing apparatus of a PCIe device provided in the embodiment of the present invention;

fig. 8 is a schematic structural diagram of an electronic device provided in an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations (or steps) can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

Fig. 1 is a schematic diagram of a PCIe protocol provided in an embodiment of the present invention. For better understanding of the scheme of the present application and the technical effects achieved, the following is a brief explanation of the PCIe protocol: the PCIe protocol defines a variety of devices, as shown in fig. 1, including: root complex RC, Switch, endpoint EP, and PCIe device to PCI/PCI-X Bridge (Bridge), etc. Wherein the root complex RC is a PCIe root device connecting the CPU and the main memory to a PCIe fabric; the Switch can route tasks from one port to another port, and is used for interconnection of multiple devices in the system; EP refers to a device (requester or completer) that specifically performs tasks for different business functions; and Bridge is used for realizing the connection between PCIe equipment and PCI/PCI-X equipment and realizing the interconversion between two different protocols.

Fig. 2 is a flowchart of a compatible processing method for PCIe devices provided in the embodiment of the present invention. The embodiment of the invention can be suitable for the condition of carrying out compatible processing on PCIe equipment with different address bit widths. The method can be executed by a compatible processing device of the PCIe equipment, and the device can be realized by adopting a software and/or hardware mode and can be integrated on any equipment with a network communication function. As shown in fig. 2, the compatible processing method for PCIe devices provided in this embodiment may include the following steps S210 to S230:

s210, determining a target address bit width and a target Bar space allocated to target PCIe end equipment according to the address bit width supported by the PCIe root equipment and the address bit width supported by the target PCIe end equipment; and at least one target PCIe end device is associated under the PCIe root device.

In this embodiment, referring to fig. 1, the PCIe root device may be associated with one or at least two target PCIe end devices such that the PCIe root device may communicate data with the target PCIe end devices. However, in practical applications, because the Bar space cannot be normally allocated, the PCIe root device RC with different address bit widths and the target PCIe end device EP cannot normally communicate and complete corresponding service functions. For example, in an RC device with a 64-bit address, the Bar space that can be allocated is much larger than that of an RC device with a 32-bit address, so the Bar space allocated to each EP device is generally large; in 32-bit address RC devices, Bar which can be allocated is smaller, so Bar space allocated to each EP device is generally smaller. Thus, when the address bit width supported by the PCIe root device is inconsistent with the address bit width supported by the target PCIe end device, the PCIe root device may not normally allocate the Bar space to the target PCIe end device. Therefore, the address bit width supported by the PCIe root device and the address bit width supported by the target PCIe end device need to be determined, and then a target Bar space meeting the compatibility requirement is allocated to the target PCIe end device according to the address bit width supported by the PCIe root device and the address bit width supported by the target PCIe end device. Meanwhile, a target address bit width meeting the compatibility requirement is also required to be allocated to the target PCIe terminal equipment.

In an alternative example, when the address bit width supported by the PCIe root device is 32 bits, the address bit width supported by the target PCIe end device associated under the PCIe root device may be 32 bits or 64 bits. For example, in the case that the address bit width supported by the PCIe root device is 32 bits, among the target PCIe end devices associated under the PCIe root device with the address bit width of 32 bits, the address bit width supported by one part of the target PCIe end devices may be 32 bits, and the address bit width supported by another part of the target PCIe end devices may be 64 bits.

In yet another alternative example, when the address bit width supported by the PCIe root device is 64 bits, the address bit width supported by the target PCIe end device associated under the PCIe root device may be 32 bits or 64 bits. For example, in a case where the address bit width supported by the PCIe root device is 64 bits, among the target PCIe end devices associated under the PCIe root device with the address bit width of 64 bits, the address bit width supported by one part of the target PCIe end devices may be 32 bits, and the address bit width supported by another part of the target PCIe end devices may be 64 bits.

In an optional manner of this embodiment, before determining the target address bit width and the target Bar space allocated to the target PCIe end device according to the address bit width supported by the PCIe root device and the address bit width supported by the target PCIe end device, the method further includes the following steps:

through PCIe scanning of the target PCIe end equipment, equipment indication information of the target PCIe end equipment is determined; wherein the device indication information includes: device identification, address bit width supported by the device, and Bar space applied by the device.

In this embodiment, when the PCIe root device is initialized during power-on, the PCIe root device may perform initialization PCIe scanning on the target PCIe end device associated therewith, and identify the device identifier of the target PCIe end device, the address bit width supported by the device, and the Bar space applied by the device. The device identifier may be a sequence composed of letters, numbers, underlines, and/or special symbols and used for identifying the identity of the PCIE device; the address bit width supported by the device can be 32-bit address bit width or 64-bit address bit width; and the Bar space applied for by the device may be a Bar space with a function of completing at least one business function task applied to the PCIe root device for completing the at least one business function task.

In an optional manner of this embodiment, the compatible processing method for PCIe devices provided in this embodiment of the present invention may further include: and determining a pre-deployment Bar space associated with the target PCIe end equipment according to the equipment identifier of the target PCIe end equipment.

In this embodiment, the PCIe root device has a pre-deployment Bar space for each target PCIe end device deployed therein. The PCIe root device is associated with at least one target PCIe end device, and the PCIe root device can pre-deploy corresponding Bar spaces for the associated target PCIe end devices according to requirements, and generate and store pre-deployment configuration information of the Bar spaces. Each target PCIe end device has a unique device identifier, and one target PCIe end device in the pre-deployment configuration information of the Bar space is associated with a unique pre-deployment Bar space. The advantage of this arrangement is that it is avoided that incompatible target PCIe end devices forcibly occupy too much Bar space, resulting in insufficient Bar space being used by other target PCIe end devices.

In this embodiment, after determining the pre-deployment Bar space associated with the target PCIe end device, a target address bit width and a target Bar space that satisfy the compatibility requirement may be allocated to the target PCIe end device from the pre-deployment Bar space associated with the target PCIe end device according to the address bit width supported by the PCIe root device and the address bit width supported by the target PCIe end device.

In this embodiment, optionally, the PCIe root device may perform normalization setting on the offset address of each target PCIe end device according to the service function. Through normalization setting, in the pre-disposition Bar space associated with each target PCIe end device, the pre-disposition Bar space is spatially divided according to different service functions, that is, PCIe offset addresses of the service functions in the pre-disposition Bar space are pre-defined, for example, register addresses of a system and positions of upgrade file addresses in the pre-disposition Bar space.

S220, PCIe compatible configuration is carried out according to the distributed target address bit width and the target Bar space, so that a target PCIe link between the PCIe root device and the target PCIe end device is constructed.

In this embodiment, after the target address bit width and the target Bar space allocated to the target PCIe end device are determined, since the target address bit width and the target Bar space both satisfy the compatibility requirement between the PCIe root device and the target PCIe end device, the PCIe compatibility configuration may be performed on the PCIe link between the PCIe root device and the target PCIe end device according to the target address bit width and the target Bar space, and a target PCIe link compatible with at least part of the service functions is constructed.

And S230, sending the data packet to the target PCIe terminal equipment by adopting the target PCIe link.

In this embodiment, on the basis of the target PCIe link constructed as described above, the PCIe root device may send a data packet capable of implementing a part of the service function to the target PCIe end device through the target PCIe link, so that the target PCIe end device implements the part of the service function accordingly.

In this embodiment, since the TLPs with different address bit widths have different structures, except that Bar space allocation is not reasonable, the PCIe root device RC and the target PCIe end device EP with different address bit widths cannot complete corresponding service functions due to different data packet formats. Therefore, when a data packet is sent to the target PCIe end equipment through the target PCIe link, the format of the data packet to be sent can be determined according to the address bit width supported by the PCIe root equipment and the address bit width supported by the target PCIe end equipment, and then the data packet with the proper format is sent to the target PCIe end equipment so as to adapt to the target PCIe end equipment with different address bit widths.

Exemplarily, fig. 3 is a schematic format diagram of a TLP packet with a 32-bit address bit width provided in the embodiment of the present invention, and fig. 4 is a schematic format diagram of a TLP packet with a 64-bit address bit width provided in the embodiment of the present invention. Referring to fig. 3 and fig. 4, it is easy to see that the TLP packet header information with 32 bit address bit width is 3 dws (double words), and the TLP packet header information with 64 bit address bit width is 4 dws (double words), and the parsing methods of the packets are also different, which brings great limitations to the use of the target PCIe end device EP. If the format of the data packet received by the target PCIe end device EP does not meet the requirement, the data packet may not be analyzed normally, and thus the corresponding service function cannot be completed.

The embodiment of the invention provides a compatible processing method of PCIe equipment, and by adopting the scheme, when the PCIe equipment is initialized, the PCIe equipment and the target PCIe end equipment in a PCIe bus can be subjected to compatible processing according to the address bit width supported by the PCIe root equipment and the address bit width supported by the target PCIe end equipment so as to construct a compatible PCIe link and ensure that the RC root equipment with different address bit widths and the EP end equipment can carry out normal communication, so that the functions of upgrading the EP end equipment, reading an equipment register and the like can be realized in the subsequent process.

On the basis of the foregoing embodiment, optionally, sending the data packet to the target PCIe end device by using the target PCIe link, may include the following steps:

and if the address bit width supported by the PCIe root equipment is less than the address bit width supported by the target PCIe end equipment, sending a data packet to the target PCIe end equipment through the target PCIe link according to the address bit width supported by the PCIe root equipment.

In this embodiment, when the address bit width supported by the PCIe root device is smaller than the address bit width supported by the target PCIe end device, the target PCIe end device may support both the PCIe configuration with the address bit width supported by the PCIe root device and the PCIe configuration with the address bit width supported by the target PCIe end device. At this time, the target PCIe end device may be compatible with the TLP packet analysis of the address bit width supported by the PCIe root device, and may also be compatible with the TLP packet analysis of the address bit width supported by the target PCIe end device. Therefore, a data packet with address bit width supported by the PCIe root device can be generated according to the address bit width supported by the PCIe root device, and the generated data packet is sent to the target PCIe end device through the target PCIe link. For example, the address bit width supported by the PCIe root device is 32 bits, and if it is identified that the address bit width supported by the target PCIe end device is 64 bits, the target PCIe end device supports both PCIe configuration with a 64-bit address bit width and PCIe configuration with a 32-bit address bit width, and at this time, as long as a TLP packet with an address bit width supported by the PCIe root device is a TLP packet with an address bit width supported by the PCIe root device, the PCIe root device and the target PCIe end device may normally receive and send the packet and analyze the packet, so that a part of service functions may be normally implemented.

In this embodiment, referring to fig. 3 and fig. 4, since the target PCIe end device is capable of analyzing a TLP packet with 32-bit and 64-bit addresses, after the target PCIe end device receives a TLP packet sent by the PCIe root device, the type of the TLP packet is determined according to the FMT field in the TLP packet, and different analysis methods are used according to the type of the packet, so as to extract valid data included in the TLP packet. And then, the target PCIe terminal equipment can perform corresponding business function tasks according to the extracted effective data.

On the basis of the foregoing embodiment, optionally, sending the data packet to the target PCIe end device by using the target PCIe link, the method may further include the following steps:

and if the address bit width supported by the PCIe root equipment is greater than or equal to the address bit width supported by the target PCIe end equipment, sending a data packet to the target PCIe end equipment through the target PCIe link according to the address bit width supported by the target PCIe end equipment.

In this embodiment, when the address bit width supported by the PCIe root device is greater than or equal to the address bit width supported by the target PCIe end device, the target PCIe end device can certainly support PCIe configuration with the address bit width supported by the target PCIe end device. At this time, the target PCIe end device is sure to be compatible with self-supported TLP packet resolution with address bit width. Therefore, a data packet with the address bit width supported by the target PCIe end device can be generated according to the address bit width supported by the target PCIe end device, and the generated data packet is sent to the target PCIe end device through the target PCIe link. For example, the address bit width supported by the PCIe root device is 64 bits, and if it is identified that the address bit width supported by the target PCIe end device is 64 or 32 bits, the target PCIe end device definitely supports PCIe configuration with an address bit width supported by itself, at this time, as long as a TLP packet with an address bit width supported by itself is received and sent normally between the PCIe root device and the target PCIe end device, and the packet can be analyzed, so that a partial service function can be realized normally.

In this embodiment, referring to fig. 3 and fig. 4, since the target PCIe end device can be compatible with self-supported TLP packet analysis of address bit widths, after the target PCIe end device receives a TLP packet sent by the PCIe root device, the type of the TLP packet is determined according to the FMT field, and different analysis methods are used according to the type of the packet, so as to extract valid data included in the TLP packet. And then, the target PCIe terminal equipment can perform corresponding business function tasks according to the extracted effective data.

By adopting the two alternatives, the TLP data packets of the address bit widths supported by the PCIe root device and the target PCIe end device can be sent to the target PCIe end device according to the address bit width supported by the PCIe root device and the address bit width supported by the target PCIe end device, and it is ensured that the data packet generated by the PCIe root device can be compatible with the data packet of the address bit width supported by the target PCIe end device, so that the target PCIe end device can compatibly analyze the received data packet, and the problem of analyzing the data packet is avoided.

Fig. 5 is a flowchart of another PCIe device compatibility processing method provided in the embodiment of the present invention. The embodiments of the present invention are optimized based on the embodiments described above, and the embodiments of the present invention may be combined with various alternatives in one or more of the embodiments described above. As shown in fig. 5, the compatible processing method for PCIe devices provided in this embodiment may include the following steps S510 to S540:

s510, if the detected address bit width supported by the PCIe root device is smaller than the address bit width supported by the target PCIe end device, the address bit width supported by the PCIe root device is distributed to the target PCIe end device to be used as the target address bit width.

In this embodiment, when the address bit width supported by the PCIe root device is smaller than the address bit width supported by the target PCIe end device, the target PCIe end device may support PCIe configuration of the address bit width supported by the PCIe root device, but the PCIe root device may not necessarily support the address bit width supported by the target PCIe end device, for example, the address bit width supported by the PCIe root device is 32 bits, the address bit width supported by the target PCIe end device is 64 bits, and at this time, the PCIe root device may not support the address bit width of 64 bits. For this reason, when address bit widths are allocated to the target PCIe end device, only address bit widths supported by the PCIe root device can be allocated to the target PCIe end device. Therefore, the PCIe root device and the target PCIe end device can be normally used compatibly only in the address bit width that can be supported, for example, the PCIe root device and the target PCIe end device can be used compatibly only in the 32-bit address space that can be supported.

S520, according to the pre-deployed Bar space service function associated with the target PCIe end device and the Bar space service function applied by the target PCIe end device, determining a Bar space with overlapped service functions as a target Bar space.

In this embodiment, at least one target PCIe end device is associated under the PCIe root device, and a pre-deployment Bar space of each target PCIe end device is deployed in the PCIe root device. Each pre-deployed Bar space can be pre-configured with at least one business function, so that the pre-deployed Bar space can be set as a Bar space capable of realizing at least one pre-configured business function.

In this embodiment, the Bar space applied for by the device may be a Bar space with at least one business function task for completing the at least one business function task and applied to the PCIe root device. After determining the business function of the pre-deployed Bar space associated with the target PCIe end device and the business function of the Bar space applied by the PCIe end device, it is determined that the two generate an overlapping business function, and at this time, no matter whether the pre-deployed Bar space associated with the target PCIe end device or the Bar space applied by the PCIe end device is compatible with the overlapping business function, the overlapping business function can be normally used, for example, the business functions of the target PCIe end device, such as FPGA upgrade, reading and writing registers of the EP device, and the like. On the basis, the pre-deployed Bar space with overlapped service functions generated in the pre-deployed Bar space associated with the target PCIe end device can be forced to be used as the target Bar space and distributed to the target PCIe end device.

S530, PCIe compatible configuration is carried out according to the distributed target address bit width and the target Bar space, so that a target PCIe link between the PCIe root device and the target PCIe end device is constructed.

And S540, sending the data packet to the target PCIe terminal equipment by adopting the target PCIe link.

The embodiment of the invention provides a compatible processing method of PCIe equipment, and by adopting the scheme, when the PCIe equipment is initialized, when the incompatibility is caused by the fact that the address bit width supported by the PCIe root equipment is smaller than the address bit width supported by the target PCIe end equipment according to the address bit width supported by the PCIe root equipment and the address bit width supported by the target PCIe end equipment, the PCIe root equipment and the target PCIe end equipment in a PCIe bus are subjected to compatible processing to construct a compatible PCIe link and ensure that normal communication is carried out between RC root equipment with different address bit widths and EP end equipment, so that functions of upgrading the EP end equipment, reading an equipment register and the like can be realized in the subsequent process.

Fig. 6 is a flowchart of a compatible processing method for PCIe devices provided in the embodiment of the present invention. The embodiments of the present invention are optimized based on the embodiments described above, and the embodiments of the present invention may be combined with various alternatives in one or more of the embodiments described above. As shown in fig. 6, the compatible processing method for PCIe devices provided in this embodiment may include the following steps S610 to S640:

s610, if the detected address bit width supported by the PCIe root device is larger than or equal to the address bit width supported by the target PCIe end device, determining the address bit width supported by the target PCIe end device as the target address bit width.

In this embodiment, when the address bit width supported by the PCIe root device is greater than or equal to the address bit width supported by the target PCIe end device, the target PCIe end device can only support PCIe configuration with its address bit width, and the PCIe root device can support the address bit width supported by the target PCIe end device, for example, the address bit width supported by the PCIe root device is 64 bits, and the PCIe root device can support the address bit width at this time no matter whether the address bit width supported by the target PCIe end device is 64 bits or 32 bits. Therefore, when the address bit width is allocated to the target PCIe end equipment, the address bit width supported by the target PCIe end equipment is determined as the target address bit width and is allocated to the target PCIe end equipment. Therefore, the PCIe root device and the target PCIe end device can be ensured to be compatible with the address bit width which can be supported at the same time.

S620, distributing all Bar spaces applied by the target PCIe end equipment to the target PCIe end equipment from the pre-deployed Bar space associated with the target PCIe end equipment to serve as the target Bar space.

In this embodiment, the Bar space applied for by the device may be a Bar space with at least one business function task for completing the at least one business function task and applied to the PCIe root device. The Bar space applied for by the PCIe peer device can be found in the pre-deployed Bar space associated with the target PCIe peer device. On the basis, the Bar space applied by the target PCIe end device can be found from the pre-deployed Bar space associated with the target PCIe end device and is distributed to the target PCIe end device.

And S630, performing PCIe compatible configuration according to the allocated target address bit width and the target Bar space to construct a target PCIe link between the PCIe root device and the target PCIe end device.

And S640, sending the data packet to the target PCIe terminal equipment by adopting the target PCIe link.

The embodiment of the invention provides a compatible processing method of PCIe equipment, and by adopting the scheme, when the PCIe equipment is initialized, when the address bit width supported by the PCIe root equipment and the address bit width supported by target PCIe end equipment are determined, the PCIe root equipment and the target PCIe end equipment in a PCIe bus are subjected to compatible processing according to the fact that the address bit width supported by the PCIe root equipment is larger than or equal to the address bit width supported by the target PCIe end equipment, so that a compatible PCIe link is constructed, normal communication between RC root equipment with different address bit widths and EP end equipment is ensured, and functions of upgrading the EP end equipment, reading an equipment register and the like can be realized in the subsequent process.

Fig. 7 is a block diagram of a compatible processing apparatus of a PCIe device provided in the embodiment of the present invention. The embodiment of the invention can be suitable for the condition of carrying out compatible processing on PCIe equipment with different address bit widths. The device can be implemented in software and/or hardware, and can be integrated on any equipment with network communication function. As shown in fig. 7, the compatible processing apparatus for PCIe devices provided in the embodiment of the present invention may include: a destination assignment module 710, a compatible configuration module 720, and a packet transmission module 730. Wherein:

a target allocating module 710, configured to determine a target address bit width and a target Bar space allocated to a target PCIe end device according to an address bit width supported by a PCIe root device and an address bit width supported by the target PCIe end device; at least one target PCIe end device is associated under the PCIe root device;

a compatible configuration module 720, configured to perform PCIe compatible configuration according to the allocated target address bit width and the target Bar space, so as to construct a target PCIe link between the PCIe root device and the target PCIe end device;

and the data packet sending module 730 is configured to send a data packet to the target PCIe end device by using the target PCIe link.

On the basis of the foregoing embodiment, optionally, the apparatus further includes:

a PCIe scanning module 740, configured to perform PCIe scanning on the target PCIe end device, and determine device indication information of the target PCIe end device; wherein the device indication information includes: device identification, address bit width supported by the device, and Bar space applied by the device.

On the basis of the foregoing embodiment, optionally, the target allocating module 710 includes:

if the address bit width supported by the PCIe root equipment is detected to be smaller than the address bit width supported by the target PCIe end equipment, distributing the address bit width supported by the PCIe root equipment to the target PCIe end equipment to be used as the target address bit width;

and determining a Bar space with overlapped service functions as the target Bar space according to the pre-deployed Bar space service function associated with the target PCIe end equipment and the Bar space service function applied by the target PCIe end equipment.

On the basis of the foregoing embodiment, optionally, the target allocating module 720 includes:

if the address bit width supported by the PCIe root equipment is detected to be larger than or equal to the address bit width supported by target PCIe end equipment, determining the address bit width supported by the target PCIe end equipment as the target address bit width;

and distributing all Bar spaces applied by the target PCIe end equipment to the target PCIe end equipment from the pre-deployed Bar space associated with the target PCIe end equipment to serve as the target Bar space.

On the basis of the foregoing embodiment, optionally, a pre-deployment Bar space of each target PCIe end device is deployed in the PCIe root device; the device further comprises:

a Bar space identification module 750, configured to determine a pre-deployment Bar space associated with the target PCIe end device according to the device identifier of the target PCIe end device.

On the basis of the foregoing embodiment, optionally, the data packet sending module 730 includes:

if the address bit width supported by the PCIe root equipment is less than the address bit width supported by the target PCIe end equipment, sending a data packet to the target PCIe end equipment through a target PCIe link according to the address bit width supported by the PCIe root equipment;

and if the address bit width supported by the PCIe root equipment is greater than or equal to the address bit width supported by the target PCIe end equipment, sending a data packet to the target PCIe end equipment through a target PCIe link according to the address bit width supported by the target PCIe end equipment.

On the basis of the above embodiment, optionally, the address bit width supported by the PCIe root device is 32 bits or 64 bits, and the address bit width supported by the target PCIe end device is 32 bits or 64 bits.

The PCIe device compatible processing apparatus provided in the embodiment of the present invention may execute the PCIe device compatible processing method provided in any embodiment of the present invention, and have a function and an advantageous effect corresponding to the execution of the PCIe device compatible processing method.

Fig. 8 is a schematic structural diagram of an electronic device provided in an embodiment of the present invention. As shown in fig. 8, the electronic device provided in the embodiment of the present invention includes: one or more processors 810 and storage 820; the processor 810 in the electronic device may be one or more, and fig. 8 illustrates one processor 810 as an example; storage 820 is used to store one or more programs; the one or more programs are executed by the one or more processors 810, such that the one or more processors 810 implement a method for compatible processing for PCIe devices as described in any of the embodiments of the present invention.

The electronic device may further include: an input device 830 and an output device 840.

The processor 810, the storage device 820, the input device 830 and the output device 840 in the electronic apparatus may be connected by a bus or other means, and fig. 8 illustrates an example of connection by a bus.

The storage 820 in the electronic device is used as a computer readable storage medium for storing one or more programs, which may be software programs, computer executable programs, and modules, such as program instructions/modules corresponding to the compatible processing method for PCIe devices provided in the embodiments of the present invention. The processor 910 executes various functional applications and data processing of the electronic device by executing software programs, instructions and modules stored in the storage 820, that is, implements the compatible processing method of the PCIe device in the above method embodiment.

The storage device 820 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the electronic device, and the like. Further, storage 820 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, storage 820 may further include memory located remotely from processor 810, which may be connected to devices over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input device 830 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic apparatus. The output device 840 may include a display device such as a display screen.

And, when the one or more programs included in the electronic device are executed by the one or more processors 810, the programs perform the following operations:

determining a target address bit width and a target Bar space distributed to target PCIe end equipment according to an address bit width supported by PCIe root equipment and an address bit width supported by the target PCIe end equipment; at least one target PCIe end device is associated under the PCIe root device;

Of course, it will be understood by those skilled in the art that when one or more programs included in the electronic device are executed by the one or more processors 810, the programs may also perform operations related to the PCIe device compatible processing method provided in any embodiment of the present invention.

An embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program for executing a compatible processing method for a PCIe device when the program is executed by a processor, the method including:

Optionally, the program may be further configured to perform a compatible processing method for a PCIe device provided in any embodiment of the present invention when executed by the processor.

The computer-readable storage media of embodiments of the invention may take any combination of one or more computer-readable media. The computer readable storage medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a flash Memory, an optical fiber, a portable CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. A computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take a variety of forms, including, but not limited to: an electromagnetic signal, an optical signal, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable storage medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, Radio Frequency (RF), etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A compatible processing method for a PCIe device, performed by a PCIe root device, to which at least one target PCIe end device is associated, the method comprising:

2. The method of claim 1, further comprising:

through PCIe scanning the target PCIe end equipment, determining equipment indication information of the target PCIe end equipment; wherein the device indication information includes: device identification, address bit width supported by the device, and Bar space applied by the device.

3. The method of claim 1, wherein determining a target address bit width and a target Bar space allocated to the target PCIe end device according to address bit widths supported by a PCIe root device and address bit widths supported by the target PCIe end device comprises:

4. The method of claim 1, wherein determining a target address bit width and a target Bar space allocated to the target PCIe end device according to address bit widths supported by a PCIe root device and address bit widths supported by the target PCIe end device comprises:

5. The method of claim 1, wherein a pre-deployed Bar space is deployed in the PCIe root device for each target PCIe end device; the method further comprises the following steps:

and determining a pre-deployment Bar space associated with the target PCIe end equipment according to the equipment identifier of the target PCIe end equipment.

6. The method of claim 1, wherein sending the data packet to the target PCIe peer device using the target PCIe link comprises:

7. The method of claim 1, wherein the address bit width supported by the PCIe root device is 32 bits or 64 bits, and the address bit width supported by the target PCIe end device is 32 bits or 64 bits.

8. A compatible processing apparatus of a PCIe device, configured in a PCIe root device, the PCIe root device having at least one target PCIe end device associated therewith, the apparatus comprising:

9. An electronic device, comprising:

one or more processors;

storage means for storing one or more programs;

when executed by the one or more processors, cause the one or more processors to implement the PCIe device compatible processing method of any of claims 1 to 7.

10. A computer-readable storage medium on which a computer program is stored, the program, when executed by a processor, implementing a compatible processing method for a PCIe device as defined in any one of claims 1 to 7.