CN110980633A - Silicon chip of micro electro mechanical system and preparation method thereof - Google Patents

Silicon chip of micro electro mechanical system and preparation method thereof Download PDF

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Publication number
CN110980633A
CN110980633A CN201911330767.XA CN201911330767A CN110980633A CN 110980633 A CN110980633 A CN 110980633A CN 201911330767 A CN201911330767 A CN 201911330767A CN 110980633 A CN110980633 A CN 110980633A
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silicon wafer
bumps
contact surface
ion
mechanical system
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戴维·兰姆·马克斯
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Qst Corp [cn/cn]
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B1/00—Devices without movable or flexible elements, e.g. microcapillary devices
    • B81B1/006—Microdevices formed as a single homogeneous piece, i.e. wherein the mechanical function is obtained by the use of the device, e.g. cutters
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/04—Networks or arrays of similar microstructural devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005—Bulk micromachining
    • B81C1/00507—Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00531—Dry etching

Abstract

The invention relates to the technical field of silicon wafer manufacturing, in particular to a silicon wafer of a micro electro mechanical system and a preparation method thereof, wherein the preparation method comprises the following steps: in step S1, a plurality of bumps are formed on the contact surface of the silicon wafer to reduce the contact area of the contact surface of the silicon wafer. The technical scheme of the invention has the beneficial effects that: the silicon chip of the micro electro mechanical system and the preparation method thereof are provided, the contact area of the silicon chip is reduced by implanting the convex block on the contact surface of the silicon chip, and thus the static resistance of the silicon chip is effectively reduced.

Description

Silicon chip of micro electro mechanical system and preparation method thereof
Technical Field
The invention relates to the technical field of silicon wafer manufacturing, in particular to a silicon wafer of a micro electro mechanical system and a preparation method thereof.
Background
Stiction is a common problem in MEMS (Micro-Electro-Mechanical systems). When the surfaces of two silicon wafers are contacted, static resistance is generated, and if the adhesive force is larger than the restoring force of the silicon wafer material, the silicon wafers cannot be restored or even damaged. Therefore, there is a need for a novel silicon wafer for a micro electro mechanical system and a method for preparing the same, which can reduce the adhesion on the surface of the silicon wafer, thereby improving the static resistance performance of the silicon wafer.
Disclosure of Invention
Aiming at the problems in the prior art, a silicon wafer of a micro electro mechanical system and a preparation method thereof are provided.
The specific technical scheme is as follows:
the invention discloses a preparation method of a silicon chip of a micro electro mechanical system, which comprises the following steps:
step S1, forming a plurality of bumps on the contact surface of the silicon wafer to reduce the contact area of the contact surface of the silicon wafer.
Preferably, the step S1 includes:
step S11, covering a patterned mask on the contact surface to open a process window;
step S12, performing an ion implantation process through the process window to form a plurality of ion-doped regions;
step S13, removing the mask;
step S14, an etching process is performed on the contact surface to form a plurality of bumps on the contact surface.
Preferably, the method further comprises the following steps:
step S2, covering a layer of anti-adhesion protective film on the surfaces of the bumps.
Preferably, the anti-bonding protective film is hexamethyldisilazane.
Preferably, in step S12, the ions implanted by the ion implantation process are arsenic ions.
Preferably, in the step S12, each of the ion doped regions has a doping concentration of 1 × 1016/cm3。
Preferably, the bump height is 172 angstroms.
The present invention also includes a silicon wafer for a microelectromechanical system, comprising:
and the plurality of bumps are arranged on the contact surface of the silicon wafer.
Preferably, the surface of a plurality of the bumps is covered with an anti-adhesion protective film.
Preferably, the heights of the bumps are the same and/or the bumps are spaced from each other at the same interval.
The technical scheme of the invention has the beneficial effects that: the silicon chip of the micro electro mechanical system and the preparation method thereof are provided, the contact area of the silicon chip is reduced by implanting the convex block on the contact surface of the silicon chip, and thus the static resistance of the silicon chip is effectively reduced.
Drawings
Embodiments of the present invention will be described more fully with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a process diagram of a MEMS silicon wafer fabrication process in accordance with an embodiment of the present invention;
FIGS. 2-5 are schematic views illustrating a process for manufacturing a MEMS silicon wafer according to an embodiment of the present invention;
FIGS. 6-7 are experimental analysis diagrams of a silicon wafer of a MEMS in an embodiment of the invention;
FIGS. 8-9 are graphs illustrating experimental analysis of the effect of inter-bump width on the performance of a silicon wafer of a MEMS in accordance with embodiments of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
Example one
The first embodiment of the invention provides a preparation method of a silicon wafer of a micro-electro-mechanical system, which comprises the following steps:
in step S1, a plurality of bumps are formed on the contact surface of the silicon wafer to reduce the contact area of the contact surface of the silicon wafer.
Specifically, there are three methods for improving the stiction performance of silicon wafers, the first is to enhance the self-healing force of the silicon wafer, the second is to change the energy of the surface of the silicon wafer, and the third is to reduce the contact area between two silicon wafers. In this embodiment, a third method is adopted to reduce the contact area between the silicon chips by implanting a plurality of bumps on the contact surface of each silicon chip.
As a preferred embodiment, as shown in fig. 1, step S1 specifically includes:
step S11, as shown in fig. 2, a patterned mask 2 is covered on the contact surface of the silicon wafer to open a process window 1;
step S12, as shown in fig. 3, an ion implantation process is performed through the process window 1 to form a plurality of ion-doped regions 3;
step S13, as shown in fig. 4, removing the mask 2;
in step S14, as shown in fig. 5, an etching process is performed on the contact surface to form a plurality of bumps 4 on the contact surface.
Specifically, the mask 2 in this embodiment is a photoresist, a patterned photoresist is first covered on the contact surface to open the process window 1, and then an ion implantation process is performed through the process window 1 to form a plurality of ion-doped regions 3 on the contact surface of the silicon wafer, and the widths of the plurality of ion-doped regions 3 are the same. In the present embodiment, arsenic ions (As) are implanted by an ion implantation process to form a plurality of ion-doped regions 3, wherein the implantation amount of the arsenic ions is 1 × 1016/cm3Phosphine (Ph) may also be implanted, but at the same implant dose, the height of the ion doped region implanted with arsenic ions is significantly higher than the ion doped region implanted with phosphine ions. As shown in Table 1, the implantation doses were all 5.00E +15/cm3Meanwhile, the height of an ion doping area formed by injecting phosphine ions is 115 angstroms, and the height of an ion doping area formed by injecting arsenic ions is 117 angstroms, so that the difference between the two is small; the implantation dosage is 1.00E +16/cm3In this case, the height of the ion-doped region formed by implanting phosphine ions was 157 angstroms, while the height of the ion-doped region formed by implanting arsenic ions was 172 angstroms, which was significantly higher than the former. Therefore, the most preferable embodiment in this example is to implant the concentration of 1.00E +16/cm into the contact surface3Arsenic ion (b).
Wafer numbering Implanted ion species Implant dose (/ cm)3) Height of ion-doped region
1 Ph 1.00E+16 157A
2 Ph 5.00E+15 115A
3 As 1.00E+16 172A
4 As 5.00E+15 117A
5 Ion implantation free N/A 20A
TABLE 1
Further, after the plurality of ion doping regions 3 are formed in the above step, the mask 2 on the contact surface is removed, the plurality of ion doping regions 3 are subjected to patterning processing, and finally, a dry etching process is performed on the contact surface of the silicon wafer until the plurality of ion doping regions 3 are completely etched away, and the etching rate of the plurality of ion doping regions 3 is higher due to the doping of ions, so that the etching depth of the regions corresponding to the plurality of ion doping regions 3 is higher than that of other regions, and a height difference is generated, thereby forming the plurality of bumps 4. It should be noted that the height of the bump 4 is related to the height of the ion-doped region 3, and therefore, in step S12, the height of the ion-doped region 3 needs to be controlled, and generally speaking, the higher the height of the bump 4 is within a certain range, the more beneficial the static resistance of the contact surface of the silicon wafer is to be reduced.
Specifically, in this embodiment, an electrostatic discharge test (Snapdown test) is performed on a silicon wafer of a different type of mems, and the electrostatic discharge test refers to a test in which a voltage is used to pull and deform the internal structure of the silicon wafer by generating an electrostatic force to observe the recovery of the internal structure of the silicon wafer, and is more rigorous than a drop test (Dropping test). As shown in fig. 6, the reference sample (control) is a normal silicon wafer without any static resistance protection and having only self-restoring force, and the test sample (Implant) is a silicon wafer implanted with bumps, and the proportion of good chips in the silicon wafer after the two are subjected to the electrostatic discharge test is analyzed. The experimental results show that the proportion of Good cores (called Good Die in silicon wafer boundary, each silicon wafer is composed of a plurality of cores, and the Good cores with qualified performance after testing) of the silicon wafer implanted with the bumps is far higher than that of the silicon wafer without the bumps. Fig. 7 shows a CDF (cumulative sensitivity function) of the experiment.
Specifically, the width of the bump 4 also has a certain influence on the static resistance performance of the silicon chip of the mems, and in this embodiment, a six-degree-of-freedom sensor unit (6DOF inertial sensor unit FIS2108) is used as an experimental sample, and bumps with different widths are arranged on the six-degree-of-freedom inertial sensor unit, and the widths are 0.4 μm, 0.6 μm and 1 μm respectively. As shown in fig. 8, the six-degree-of-freedom inertial sensor unit having a bump width of 1 μm has the highest good core rate compared to the other two. FIG. 9 is a CDF map of this experiment. In short, the larger the width of the bump 4, the better the stiction performance of the silicon wafer of the mems.
Example two
A second embodiment of the present invention provides a method for preparing a silicon wafer of a micro electro mechanical system, comprising the steps of:
step S1, step S1, forming a plurality of bumps on the contact surface of the silicon wafer to reduce the contact area of the contact surface of the silicon wafer;
step S2, a layer of anti-adhesive protective film is covered on the surfaces of the bumps.
Specifically, the difference between the second embodiment and the first embodiment is that, in the second embodiment, besides implanting the bump on the surface of the silicon wafer substrate, an anti-adhesion protective film is further covered on the surface of the bump for reducing the adhesion on the surface of the bump. In this embodiment, Hexamethyldisilazane (HMDS) is used as the material of the anti-adhesive protective film.
Further, in this embodiment, an experimental analysis of the static resistance performance is performed on the above several different types of Inertial Measurement Units (IMUs), and the inertial measurement unit is a six-degree-of-freedom inertial sensor unit. The experiment totally comprises four types of micro-electro-mechanical system silicon wafers: the first type is an IMU without any stiction protection (neither bump nor HMDS implanted), the second type is an IMU with HMDS only on the contact side of the silicon wafer, the third type is an IMU with bumps only implanted (silicon wafer in example one), the fourth type is an IMU with bumps implanted and HMDS on the bump surface (silicon wafer in example two).
Specifically, in this experiment, the first type of IMU included 33 chips, the second type of IMU included 103 chips, the third type of IMU included 20 chips, and the fourth type of IMU included 60 chips. When testing each IMU, put a plurality of chips on the circuit board (DB for short), then place the circuit board on a U template, drop the experiment to every IMU, drop the U template to the metal sheet from the height of difference on, every IMU carries out 60 at least and drops the experiment to guarantee that the surface of metal sheet bears 40 ~ 2000 g's impact force.
Further, table 2 shows the stiction performance data after the four types of IMUs in this experiment had completed the drop test, with 85% of the 33 chips of the first type of IMU showing stiction, 22% of the 103 chips of the second type of IMU showing stiction, 5% of the 20 chips of the third type of IMU showing stiction, and none of the 60 chips of the fourth type of IMU showing stiction, without recovery via Firmware (FW). With FW recovery, the first class of IMUs still exhibited 39% stiction, while the other three classes did not. The experimental data show that the effect of implanting the bump on the contact surface of the silicon wafer is the best, and meanwhile, the effect of reducing the static resistance to a certain extent is achieved by covering the HMDS, so that the fourth type of IMU is obtained by combining the two methods in the second embodiment.
Figure BDA0002329494280000081
TABLE 2
An embodiment of the present invention provides a silicon wafer of a micro electro mechanical system, as shown in fig. 5, including:
and a plurality of bumps 4 arranged on the contact surface of the silicon wafer.
Specifically, in the present embodiment, the plurality of bumps 4 are disposed on the contact surface of each silicon wafer, so as to reduce the contact area between the silicon wafers of the mems, and effectively reduce the static resistance, i.e., the adhesion, of the silicon wafers.
In a preferred embodiment, the surfaces of the bumps are covered with an anti-adhesion protective film, and the anti-adhesion protective film is made of hexamethyldisilazane for reducing the adhesion on the surfaces of the bumps.
The technical scheme of the invention has the beneficial effects that: the silicon chip of the micro electro mechanical system and the preparation method thereof are provided, the contact area between the silicon chips is reduced by implanting the convex blocks on the contact surface of the silicon chip, and thus the static resistance of the silicon chip is effectively reduced.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims (10)

1. A preparation method of a silicon wafer of a micro-electro-mechanical system is characterized by comprising the following steps:
step S1, forming a plurality of bumps on the contact surface of the silicon wafer to reduce the contact area of the contact surface of the silicon wafer.
2. The method for preparing a composite material according to claim 1, wherein the step S1 includes:
step S11, covering a patterned mask on the contact surface to open a process window;
step S12, performing an ion implantation process through the process window to form a plurality of ion-doped regions;
step S13, removing the mask;
step S14, an etching process is performed on the contact surface to form a plurality of bumps on the contact surface.
3. The method of claim 1, further comprising:
step S2, covering a layer of anti-adhesion protective film on the surfaces of the bumps.
4. The production method according to claim 3, wherein the anti-adhesion protective film is hexamethyldisilazane.
5. The method of claim 2, wherein in the step S12, the ions implanted by the ion implantation process are arsenic ions.
6. The method according to claim 2, wherein in the step S12, each ion doped region has a doping concentration of 1 x 1016/cm3。
7. The method of claim 1, wherein the bump height is 172 angstroms.
8. A mems silicon wafer, comprising:
and the plurality of bumps are arranged on the contact surface of the silicon wafer.
9. The silicon wafer of claim 8, wherein the surface of the plurality of bumps is covered with an anti-stiction protective film.
10. The semiconductor structure of claim 8, wherein heights of the plurality of bumps are the same and/or spacings between the plurality of bumps are the same.
CN201911330767.XA 2019-12-20 2019-12-20 Silicon chip of micro electro mechanical system and preparation method thereof Pending CN110980633A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060024880A1 (en) * 2004-07-29 2006-02-02 Clarence Chui System and method for micro-electromechanical operation of an interferometric modulator
US20060278942A1 (en) * 2005-06-14 2006-12-14 Innovative Micro Technology Antistiction MEMS substrate and method of manufacture
CN101641219A (en) * 2007-04-05 2010-02-03 E.I.内穆尔杜邦公司 Method to form a pattern of functional material on a substrate using a mask material
CN102543665A (en) * 2010-12-07 2012-07-04 中国科学院微电子研究所 Improved rapid thinning method of gallium arsenide substrate
CN103178014A (en) * 2013-03-14 2013-06-26 上海华力微电子有限公司 Manufacturing method of U-shaped trenches

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060024880A1 (en) * 2004-07-29 2006-02-02 Clarence Chui System and method for micro-electromechanical operation of an interferometric modulator
US20060278942A1 (en) * 2005-06-14 2006-12-14 Innovative Micro Technology Antistiction MEMS substrate and method of manufacture
CN101641219A (en) * 2007-04-05 2010-02-03 E.I.内穆尔杜邦公司 Method to form a pattern of functional material on a substrate using a mask material
CN102543665A (en) * 2010-12-07 2012-07-04 中国科学院微电子研究所 Improved rapid thinning method of gallium arsenide substrate
CN103178014A (en) * 2013-03-14 2013-06-26 上海华力微电子有限公司 Manufacturing method of U-shaped trenches

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
赵坚勇, 国防工业出版社 *

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