CN110968270B - Efficient storage method and device for Flash space - Google Patents
Efficient storage method and device for Flash space Download PDFInfo
- Publication number
- CN110968270B CN110968270B CN201911157718.0A CN201911157718A CN110968270B CN 110968270 B CN110968270 B CN 110968270B CN 201911157718 A CN201911157718 A CN 201911157718A CN 110968270 B CN110968270 B CN 110968270B
- Authority
- CN
- China
- Prior art keywords
- storage
- space
- data
- address
- flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004891 communication Methods 0.000 claims description 12
- 239000002699 waste material Substances 0.000 abstract description 3
- 238000013500 data storage Methods 0.000 description 9
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
- Stored Programmes (AREA)
Abstract
The invention discloses a high-efficiency storage method and device of a Flash space, wherein the high-efficiency storage method of the Flash space comprises the following steps: receiving a storage instruction sent by external terminal equipment; after resolving and confirming that the storage instruction is effective, storing the storage instruction into a head address space of Flash; addressing from the first storage space behind the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched; setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range. The invention can solve the problem of waste of the existing Flash storage space.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a high-efficiency storage method and device for a Flash space.
Background
Along with the popularization of electronic products, the requirement for the storage function of the products is diversified and intelligent. At present, common storage devices comprise an SD card, a FLASH and the like, in programming, the SD card reads and writes in a block unit, NAND FLASH reads and writes in a page unit, and address data of a single byte cannot be read, so that less flexibility in programming is caused, and one block or one page of space is not fully applied easily, so that the waste of storage space is caused.
Disclosure of Invention
The invention provides a high-efficiency storage method and device for a Flash space, which solve the problem of waste of the existing Flash storage space.
According to a first aspect of the present invention, an embodiment of the present invention provides a method for efficient storage of Flash space, including the following steps: receiving a storage instruction sent by external terminal equipment; after resolving and confirming that the storage instruction is effective, storing the storage instruction into a head address space of Flash; addressing from the first storage space behind the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched; setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range.
Preferably, the method further comprises the following steps: receiving a reading instruction sent by external terminal equipment; after the reading instruction is analyzed and confirmed to be effective, a reading interval range of the data to be read is set, and the data in the reading interval range is sent to the terminal equipment.
Preferably, the method further comprises the following steps: receiving a clearing instruction sent by external terminal equipment; after the clearing instruction is analyzed and confirmed to be effective, all data in the Flash space are cleared.
Preferably, the method further comprises the following steps: when new data to be stored is received, judging whether a first address space stores the storage instruction, if so, addressing from a first storage space behind the first address space, and when a storage space for non-stored data is found, determining the address of the storage space for the non-stored data; setting the determined address to the maximum address as a storage interval range, and storing new data to be stored in the storage interval range byte by byte according to the address space sequence.
Preferably, the method further comprises the following steps: when the data in the head address space is empty, the control system enters a waiting mode.
According to a second aspect of the present invention, an embodiment of the present invention provides a Flash space efficient storage device, including a communication module, a Flash, and a processing module connected to the communication module and the Flash, where the processing module is configured to execute the following method: receiving a storage instruction sent by external terminal equipment; after resolving and confirming that the storage instruction is effective, storing the storage instruction into a head address space of Flash; addressing from the first storage space behind the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched; setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range.
Preferably, the processing module is further configured to: receiving a reading instruction sent by external terminal equipment; after the reading instruction is analyzed and confirmed to be effective, a reading interval range of the data to be read is set, and the data in the reading interval range is sent to the terminal equipment.
Preferably, the processing module is further configured to: receiving a clearing instruction sent by external terminal equipment; after the clearing instruction is analyzed and confirmed to be effective, all data in the Flash space are cleared.
Preferably, the processing module is further configured to: when new data to be stored is received, judging whether a first address space stores the storage instruction, if so, addressing from a first storage space behind the first address space, and when a storage space for non-stored data is found, determining the address of the storage space for the non-stored data; setting the determined address to the maximum address as a storage interval range, and storing new data to be stored in the storage interval range byte by byte according to the address space sequence.
Preferably, the processing module is further configured to: when the data in the head address space is empty, the control system enters a waiting mode.
The invention has the technical effects that: when data storage is carried out, the processing module carries out addressing, searches an address space of non-stored data, stores the data byte by byte according to the sequence of the address space from the address space of the first non-stored data, realizes data storage by byte, and greatly improves the utilization rate of the Flash storage space.
Drawings
FIG. 1 is a schematic diagram of a Flash space efficient memory device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for efficient storage of Flash space according to one embodiment of the invention;
fig. 3 is a schematic structural diagram of Flash according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The embodiment of the invention provides a high-efficiency storage method of a Flash space, wherein a hardware environment applied by the method is shown in figure 1, and the method comprises a processing module 1, a Flash2 and a communication module 3, wherein the communication module 3 and the Flash2 are connected with the processing module 1. The processing module 1 can be a single chip microcomputer chip, and the Flash2 can be connected with the processing module 1 through an SPI bus. The efficient storage method of the Flash space will be described from the point of view of the processing module 1, as shown in fig. 2, which specifically includes the following steps:
S100: and receiving a storage instruction sent by the external terminal equipment.
After the system is powered on, the processing module, the Flash and the SPI buses all perform initialization operation, and after the initialization is completed, external instructions can be waited. The external terminal equipment can send a storage instruction, and the communication module transmits the storage instruction to the processing module after receiving the storage instruction.
S200: after the storage instruction is analyzed and confirmed to be effective, the storage instruction is stored in a head address space of Flash.
The wireless communication data are often encrypted, so after receiving the storage instruction, the processing module performs analysis operations such as decryption verification and the like on the storage instruction, and if the storage instruction is confirmed to be invalid, the processing module does not respond to the storage instruction. If the storage instruction is confirmed to be effective, data storage can be performed, and the processing module stores the received storage instruction into a head address space of Flash. This has the advantage that if the system is powered down, the store instructions remain stored in Flash. When the system is powered up again, the data can be automatically addressed and stored continuously, and the data can be automatically stored only by sending the instruction once.
S300: and starting addressing from the first storage space after the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched.
The head address space is dedicated to storing external instructions and is not directly used to store data to be stored. Therefore, the processing module starts addressing from the first storage space behind the first address space, specifically starts addressing from the first byte space behind the first address space, sequentially judges whether each byte space has data stored, continues to judge the next byte space until the storage space without data is searched, and then determines the address of the storage space, so that the first byte space without data is searched according to the ordering of the storage spaces.
S400: setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range.
Setting the determined address as a starting address, setting the maximum address of Flash as an ending address, setting a storage space between the starting address and the ending address as a storage interval range, storing data in the storage interval range, and storing the data byte by byte according to the sequence of the address space. The data volume stored each time should be smaller than the residual capacity of Flash, before data storage, it can be judged whether the stored data volume is smaller than or equal to the residual capacity, if so, the data can be stored, otherwise, the data will overflow, and the information which can not be stored can be fed back to the terminal equipment.
In one embodiment, before step S100, the method further includes the following steps: the processing module reads the first address space data (usually the storage space with the address of 0x 00) of the Flash, judges whether the data meets the self-defined data format, if so, the system enters an automatic storage mode, the processing module starts addressing from the first address of the Flash until no data is found in a certain address space, sets the address and the maximum address as a storage interval range, and stores the data in the system byte by byte according to the sequence of the address space; if not, entering a waiting mode to wait for the instruction of the external terminal equipment. If an instruction of an external terminal device is received, steps S100 to S400 are performed.
The embodiment realizes the switching of the working modes of the system by judging the data in the head address space. In the automatic storage mode, flash will store the internal data of the system, which is not under the control of external instructions. The external instruction is received only in the waiting mode, thereby storing external data.
After the data storage transmitted by the external terminal device is completed, a waiting mode may be continued to be entered to wait for the generation of external events, specifically, two events as will be mentioned below.
In one embodiment, the external terminal device may issue a read instruction to desire to read the data stored in Flash. The processing module analyzes the read instruction sent by the external terminal equipment, verifies the validity and the validity of the read instruction, and after confirming that the read instruction is valid and valid, sets a read interval range of data to be read, further reads out the data in the read interval range, and finally sends the data to the terminal equipment through the communication module to complete data reading.
In one embodiment, the external terminal device may issue a purge instruction in hopes of purging the data stored in Flash. The processing module analyzes the clearing instruction received from the external terminal equipment, verifies the validity and the effectiveness of the reading instruction, and clears the data in the Flash space after confirming that the reading instruction is valid and effective.
On the basis of the embodiment, when the processing module receives new data to be stored, the processing module will determine whether the first address space of the Flash stores a storage instruction, and if the storage instruction still exists, the Flash will continue to store the newly received data to be stored. Specifically, according to steps S300 and S400, addressing is started from the first storage space after the first address space, and when the storage space of the non-stored data is found, the address of the storage space of the non-stored data is determined; setting the determined address to the maximum address as a storage interval range, and storing new data to be stored in the storage interval range byte by byte according to the address space sequence. Therefore, new data to be stored is stored in the address space behind the address space of the data stored in the Flash, and the new data can be continuously received until the address space stores the data.
The preset address space of Flash may be set as a recording address space, and after the data storage is completed, the last bit address of the stored data is determined, and the determined last bit address is written into the recording address space of Flash. When new data to be stored is received, setting addresses recorded in the recording address space to the maximum addresses as a storage interval range, and further storing the new data to be stored byte by byte in the storage interval range according to the address space sequence. Compared with the embodiment, the implementation omits the process of data addressing, and when new data needs to be stored, the recorded last bit address can be directly read from the recording address space, so that the data storage is quickly started from the last bit address, and the data storage speed is increased.
In one embodiment, when the data in the first address space is empty, the control system enters a waiting mode, in which the Flash does not perform any operation, but waits for an instruction of the external terminal device, and after receiving the corresponding instruction, the processing module controls the Flash to perform a corresponding action. Upon receipt of a clear instruction, the data in the head address space is also cleared, thereby entering a wait mode.
The embodiment of the invention provides a high-efficiency storage device for a Flash space, which is shown in fig. 1 and comprises a processing module 1, a Flash2 and a communication module 3, wherein the communication module 3 and the Flash2 are connected with the processing module 1. The processing module 1 may be a single chip microcomputer chip, for example, an STM32 single chip microcomputer, as shown in fig. 3, flash2 may be a chip W25Q128, W25Q128 has a capacity space of 16M, standard SPI is supported, and pins 2, 5 and 6 of the chip W25Q128 may be connected to the processing module 1 through an SPI bus. The communication module 3 may be a bluetooth module, and the terminal device may be a mobile device such as a mobile phone, a tablet computer, etc., where the mobile device is pre-equipped with an app client, and a user issues an instruction through the app client to store data into Flash2, read data in Flash2, or clear data in Flash 2.
The processing module is configured to perform the following method: receiving a storage instruction sent by external terminal equipment; after resolving and confirming that the storage instruction is effective, storing the storage instruction into a head address space of Flash; addressing from the first storage space behind the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched; setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range.
In one embodiment, the processing module is further configured to: receiving a reading instruction sent by external terminal equipment; after the reading instruction is analyzed and confirmed to be effective, a reading interval range of the data to be read is set, and the data in the reading interval range is sent to the terminal equipment.
In one embodiment, the processing module is further configured to: receiving a clearing instruction sent by external terminal equipment; after the clearing instruction is analyzed and confirmed to be effective, all data in the Flash space are cleared.
In one embodiment, the processing module is further configured to: when new data to be stored is received, judging whether a first address space stores the storage instruction, if so, addressing from a first storage space behind the first address space, and when a storage space for non-stored data is found, determining the address of the storage space for the non-stored data; setting the determined address to the maximum address as a storage interval range, and storing new data to be stored in the storage interval range byte by byte according to the address space sequence.
In one embodiment, the processing module is further configured to: when the data in the head address space is empty, the control system enters a waiting mode.
The above description of the method performed by the processing module refers to the embodiments of the method section described above.
The foregoing is a further detailed description of the invention in connection with specific embodiments, and it is not intended that the invention be limited to such description. It will be apparent to those skilled in the art that several simple deductions or substitutions can be made without departing from the spirit of the invention.
Claims (2)
1. The efficient storage method of the Flash space is characterized by comprising the following steps of:
receiving a storage instruction sent by external terminal equipment;
after resolving and confirming that the storage instruction is effective, storing the storage instruction into a head address space of Flash;
addressing from the first storage space behind the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched;
setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range;
The method also comprises the following steps: receiving a reading instruction sent by external terminal equipment; after the reading instruction is analyzed and confirmed to be effective, setting a reading interval range of data to be read, and sending the data in the reading interval range to terminal equipment;
the method also comprises the following steps: receiving a clearing instruction sent by external terminal equipment; after the clearing instruction is analyzed and confirmed to be effective, all data in the Flash space are cleared;
The method also comprises the following steps: when new data to be stored is received, judging whether a first address space stores the storage instruction, if so, addressing from a first storage space behind the first address space, and when a storage space for non-stored data is found, determining the address of the storage space for the non-stored data; setting the determined address to the maximum address as a storage interval range, and storing new data to be stored in the storage interval range byte by byte according to the address space sequence;
The method also comprises the following steps: when the data in the head address space is empty, the control system enters a waiting mode.
2. The utility model provides a high-efficient storage device in Flash space which characterized in that: the Flash memory comprises a communication module, a Flash and a processing module which is respectively connected with the communication module and the Flash, wherein the processing module is configured to execute the following method: receiving a storage instruction sent by external terminal equipment; after resolving and confirming that the storage instruction is effective, storing the storage instruction into a head address space of Flash; addressing from the first storage space behind the head address space, and determining the address of the storage space of the non-stored data when the storage space of the non-stored data is searched; setting the determined address to the maximum address as a storage interval range, and storing data byte by byte according to the address space sequence in the storage interval range;
The processing module is further configured to: receiving a reading instruction sent by external terminal equipment; after the reading instruction is analyzed and confirmed to be effective, setting a reading interval range of data to be read, and sending the data in the reading interval range to terminal equipment;
The processing module is further configured to: receiving a clearing instruction sent by external terminal equipment; after the clearing instruction is analyzed and confirmed to be effective, all data in the Flash space are cleared;
The processing module is further configured to: when new data to be stored is received, judging whether a first address space stores the storage instruction, if so, addressing from a first storage space behind the first address space, and when a storage space for non-stored data is found, determining the address of the storage space for the non-stored data; setting the determined address to the maximum address as a storage interval range, and storing new data to be stored in the storage interval range byte by byte according to the address space sequence;
The processing module is further configured to: when the data in the head address space is empty, the control system enters a waiting mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911157718.0A CN110968270B (en) | 2019-11-22 | 2019-11-22 | Efficient storage method and device for Flash space |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911157718.0A CN110968270B (en) | 2019-11-22 | 2019-11-22 | Efficient storage method and device for Flash space |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110968270A CN110968270A (en) | 2020-04-07 |
| CN110968270B true CN110968270B (en) | 2024-06-07 |
Family
ID=70031292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911157718.0A Active CN110968270B (en) | 2019-11-22 | 2019-11-22 | Efficient storage method and device for Flash space |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110968270B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114340097A (en) * | 2021-12-30 | 2022-04-12 | 合肥市芯海电子科技有限公司 | Method and device for controlling lamp strip, chip and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855881A (en) * | 2005-04-28 | 2006-11-01 | 华为技术有限公司 | Method for dynamically sharing space of memory |
| CN106569748A (en) * | 2016-10-27 | 2017-04-19 | 南方电网科学研究院有限责任公司 | Data processing method and device for Flash file system |
| CN109101436A (en) * | 2018-06-28 | 2018-12-28 | 广州视源电子科技股份有限公司 | Data dynamic addressing storage method, device and storage medium, terminal device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0978786A1 (en) * | 1998-08-05 | 2000-02-09 | Siemens Aktiengesellschaft | Interface scheme et method for transferring data between a serial interface and a processor |
| US10277677B2 (en) * | 2016-09-12 | 2019-04-30 | Intel Corporation | Mechanism for disaggregated storage class memory over fabric |
-
2019
- 2019-11-22 CN CN201911157718.0A patent/CN110968270B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855881A (en) * | 2005-04-28 | 2006-11-01 | 华为技术有限公司 | Method for dynamically sharing space of memory |
| CN106569748A (en) * | 2016-10-27 | 2017-04-19 | 南方电网科学研究院有限责任公司 | Data processing method and device for Flash file system |
| CN109101436A (en) * | 2018-06-28 | 2018-12-28 | 广州视源电子科技股份有限公司 | Data dynamic addressing storage method, device and storage medium, terminal device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110968270A (en) | 2020-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7921244B2 (en) | Data sharing and transfer systems and methods | |
| US7007127B2 (en) | Method and related apparatus for controlling transmission interface between an external device and a computer system | |
| CN115858431B (en) | Data transmission control method, controller and electronic equipment | |
| US11016917B2 (en) | Data storage system and method for multiple communication protocols and direct memory access | |
| JPWO2004077306A1 (en) | SDIO controller | |
| CN108628543B (en) | Garbage collection method and device using same | |
| CN103631534B (en) | Data storage system and managing method thereof | |
| CN112947857B (en) | Data moving method, device, equipment and computer readable storage medium | |
| CN110968270B (en) | Efficient storage method and device for Flash space | |
| CN112445766A (en) | Terminal fragment sorting method and device and terminal | |
| CN101031898B (en) | Implementing bufferless dma controllers using split transactions | |
| US6954815B2 (en) | Microcomputer with universal serial bus interface circuit and method of controlling the same | |
| CN112631969A (en) | Virtual multichannel data transmission method and system based on PCIE interface | |
| JP2003140980A (en) | Recording apparatus | |
| US20030172203A1 (en) | Automated transfer of a data unit comprising a plurality of fundamental data units between a host device and a storage medium | |
| US20060184708A1 (en) | Host controller device and method | |
| WO2023240941A1 (en) | Method and apparatus for downloading data, and secure element | |
| CN111208757A (en) | eMMC main controller based on FPGA | |
| CN110795373A (en) | Method for converting I2C bus into parallel bus, terminal and storage medium | |
| CN100517377C (en) | Multifunctional IC card and control method thereof | |
| US20030056037A1 (en) | Hardware chain pull | |
| JP4793798B2 (en) | Microcomputer | |
| JP2002149623A (en) | Microcomputer | |
| JP4988982B2 (en) | Microcomputer control method | |
| CN104636081B (en) | Data-storage system and its management method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |