CN110958177B - Network-on-chip route optimization method, device, equipment and readable storage medium - Google Patents
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- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
- H04L45/08—Learning-based routing, e.g. using neural networks or artificial intelligence
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/302—Route determination based on requested QoS
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Abstract
The invention discloses a method, a device, equipment and a readable storage medium for optimizing network-on-chip routing, wherein the method comprises the following steps: testing the network on chip by using a network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies; creating a deep neural network matched with the on-chip network; training the deep neural network by using a test data set to obtain an optimized routing strategy; and setting routing parameters of each node of the network on chip according to the optimized routing strategy. Compared with the manual setting of the routing strategy, the method can reduce manual intervention, simplify the routing control process and improve the route strategy with better quality.
Description
Technical Field
The present invention relates to the field of computer application technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for optimizing a network-on-chip route.
Background
A network-on-chip (NoC) is a new communication method for a system-on-chip (SoC). It is a major component of multi-core technology. Nocs bring a new on-chip communication method that is significantly superior to the performance of traditional bus-based systems (buses).
In nocs, the most commonly used network architecture, which is also best suited, is the packet-switched direct network. Each node is connected to adjacent nodes by bidirectional lanes. The network connections of nocs are heterogeneous, requiring different processing elements and storage elements to be connected, and traffic distribution is also non-uniform. In the design of the NOC architecture facing the FPGA platform, limited by the internal resources of the chip, the number of channels is limited, and a policy for routing the data packets on each node is important, the policy specifies the priority of the data packets in each direction and to which port the data packets are sent out preferentially, including how to balance the load in each direction, reduce the waiting time of the data packets, improve the passing efficiency as much as possible under the condition of limited channels, and reduce the occurrence of deadlock (dead-lock) and livelock (live-lock) phenomena in the network.
Currently, the commonly adopted routing strategies include fixed priority order of each direction, Round-Robin time slice rotation, longest waiting time priority and the like. Setting the routing strategy is often manually tested in a large amount, which is time-consuming, and manually setting the routing strategy is often related to personal experience, and the set routing strategy is often difficult to meet the actual transmission requirement of the network on chip.
In summary, how to effectively solve the problem of optimizing the routing policy of the network on chip is a technical problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method, a device and equipment for optimizing network-on-chip routing and a readable storage medium, so as to optimize the routing strategy of the network-on-chip.
In order to solve the technical problems, the invention provides the following technical scheme:
a method for optimizing network-on-chip routing, comprising:
testing the network on chip by using a network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies;
creating a deep neural network matched with the on-chip network;
training a deep neural network by using the test data set to obtain an optimized routing strategy;
and setting routing parameters of each node of the network on chip according to the optimized routing strategy.
Preferably, the testing the network on chip by using the network test model to obtain the test data set includes:
when the network test model is used for deploying the routing test strategy on the network on chip in sequence, the nodes respectively correspond to the network performance; the network performance includes: and simultaneously inputting the number of data packets, the injection rate, the number of channels, the single-channel cache capacity, the deadlock occurrence rate, the livelock occurrence rate, the waiting time of the data packets in the nodes and the node positions.
Preferably, the creating a deep neural network matched with the network on chip includes:
creating a deep neural network having a size that matches the number of nodes of the network-on-chip.
Preferably, the creating a deep neural network whose size matches the number of nodes of the network on chip includes:
creating a deep neural network comprising an input layer, a hidden layer and an output layer; wherein the routing parameters in the routing strategy of the network on chip are distributed in the deep neural network.
Preferably, training a deep neural network using the test data set includes:
inputting the test data set into the deep neural network for training;
calculating a loss value by using a network loss function matched with the network requirement;
and when the loss value is smaller than a preset threshold value, determining the current routing strategy as the optimized routing strategy.
Preferably, training a deep neural network using the test data set includes:
dividing the test data set into a training set and a test set;
training the deep neural network by using the training set;
testing the deep neural network by using the test set, and fixing the current parameters as final routing strategy parameters if the test performance reaches the standard; otherwise, adding the training set and the test set to continue training and testing until the test performance reaches the standard.
Preferably, setting routing parameters of each node of the network on chip according to the optimized routing policy includes:
and setting the priority of the data packet in each direction of each node and the priority of each sending port according to the optimized routing strategy.
An on-chip network route optimization device, comprising:
the test data set acquisition module is used for testing the network on chip by using the network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies;
the deep neural network creating module is used for creating a deep neural network matched with the on-chip network;
the routing strategy optimization module is used for training the deep neural network by utilizing the test data set so as to obtain an optimized routing strategy;
and the routing configuration module is used for setting routing parameters of each node of the network on chip according to the optimized routing strategy.
An on-chip network route optimization device, comprising:
a memory for storing a computer program;
and the processor is used for realizing the steps of the network-on-chip route optimization method when executing the computer program.
A readable storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the above-mentioned network-on-chip route optimization method.
By applying the method provided by the embodiment of the invention, the network-on-chip is tested by utilizing the network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies; creating a deep neural network matched with the on-chip network; training the deep neural network by using a test data set to obtain an optimized routing strategy; and setting routing parameters of each node of the network on chip according to the optimized routing strategy.
In the method, the network on chip is tested by utilizing a network test model under different routing strategies to obtain the network performance of the network on chip. And establishing a deep neural network matched with the on-chip network, and training the deep neural network based on the test data set, namely learning the deep neural network to obtain the incidence relation among all nodes of the on-chip network and the incidence relation of various routing configurations among the nodes, so that the deep neural network can finally simulate the processing mode of all nodes of the on-chip network under different routing strategies. And carrying out routing strategy optimization training based on the deep neural network to obtain an optimized routing strategy. And finally, setting routing parameters of each node of the network-on-chip according to the optimized routing strategy. Thus, the routing strategy of the network on chip can be optimized. Compared with the manual setting of the routing strategy, the method can reduce manual intervention, simplify the routing control process and improve the route strategy with better quality.
Accordingly, embodiments of the present invention further provide a device, an apparatus, and a readable storage medium for optimizing a network-on-chip route, which correspond to the above method for optimizing a network-on-chip route, and have the above technical effects, which are not described herein again.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart illustrating an implementation of a method for optimizing a network-on-chip route according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a single node according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an on-chip network route optimization apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an on-chip network route optimization device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an on-chip network route optimization device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, fig. 1 is a flowchart of a method for optimizing a network-on-chip route according to an embodiment of the present invention, where the method includes the following steps:
s101, testing the network on chip by using a network test model to obtain a test data set.
The test data set comprises different routing test strategies and network performances corresponding to various routing test strategies.
Wherein, the acquisition of the test data set comprises: when a network test model is utilized to sequentially deploy a routing test strategy on a network-on-chip, each node respectively corresponds to network performance; the network performance includes: and simultaneously inputting the number of data packets, the injection rate, the number of channels, the single-channel cache capacity, the deadlock occurrence rate, the livelock occurrence rate, the waiting time of the data packets in the nodes and the node positions. The network test model may be embodied as a common traffic model. That is, various test types can be generated by using a traffic model commonly used for testing the NOC network, and in a large number of tests under different conditions (i.e., under different routing test configurations), the elements such as the number of packets, the injection rate (i.e., the number of packets injected per unit time), the number of channels, the single-channel cache capacity, the deadlock occurrence rate, the livelock occurrence rate, the waiting time of the packets in the nodes, and the positions of the nodes in the network, which are input by the single nodes in the network at the same time, are statistically sorted to obtain a test data set. That is, the test data set includes different routing test policies and network performance of each node in the network on chip under various routing test policies.
And S102, creating a deep neural network matched with the on-chip network.
In this embodiment, in order to obtain an optimal routing strategy, a network on chip is simulated through a Deep Neural Network (DNN), and then the Deep neural network is used to optimize the routing strategy, so as to obtain an optimized routing strategy. Therefore, when creating a deep neural network, a deep neural network matching the on-chip network needs to be created.
The small scale of the network on chip may have 3 x 3, 4 x 4, 5 x 5, etc., and the large scale of the network may have 10 x 10, 20 x 20, etc. For a network on chip, each node and its neighboring nodes perform packet transmission mutually through channels, so that routing parameters need to be set for each node.
The deep neural network simulates the network on chip, and thus can be specifically created with a size matching the number of nodes of the network on chip. For a deep neural network, at least an input layer, a hidden layer and an output layer are required, so that the deep neural network comprising the input layer, the hidden layer and the output layer can be specifically created; wherein, the routing parameters in the routing strategy of the network on chip are distributed in the deep neural network. Specifically, parameters in the routing strategy can be uniformly distributed on each layer of nodes in the deep neural network, the input of the deep neural network is a data packet, the output of the deep neural network is a score of the network performance, and the score is calculated by a network loss function, namely the performance is tested.
It should be noted that, in the specific execution process of the above steps S101 and S102, there may be no order, for example, step S101 may be executed first and then step S102 may be executed, step S102 may be executed first and then step S101 may be executed, and step S101 and step S102 may also be executed in parallel. That is, before step S103 is executed, the creation of the deep neural network and the acquisition of the test data set may be completed.
S103, training the deep neural network by using the test data set to obtain an optimized routing strategy.
Training a deep neural network to train routing parameters, wherein the parameters embody routing strategies; the training process of the neural network is a process of repeated iterative computation, the parameters on each node in the neural network are just started to be some initial values, a group of data packets are input to pass through the neural network, a loss value is computed by using a network loss function, then each parameter is computed by reverse derivation according to the principle that the loss value approaches to 0, and the parameters are updated to each node. By repeating the above steps, after training of a large number of data packets, parameters with small loss values can be obtained, and the parameters represent routing strategies and are further applied to the final network on chip.
Specifically, the process of obtaining the optimized routing policy may include the following steps:
inputting a test data set into a deep neural network for training;
calculating a loss value by using a network loss function matched with the network requirement;
and step three, when the loss value is smaller than a preset threshold value, determining the current routing strategy as an optimized routing strategy.
For convenience of description, the above three steps will be described in combination.
In practical applications, the loss value is specifically determined according to the test performance, i.e., whether the training is up to standard can be determined according to the test performance. The determination process of optimizing the routing policy may specifically be:
step 1, dividing a test data set into a training set and a test set;
step 2, training the deep neural network by using a training set;
step 3, testing the deep neural network by using the test set, and fixing the current parameters as final routing strategy parameters if the test performance reaches the standard; otherwise, adding the training set and the test set to continue training and testing until the test performance reaches the standard.
In particular, most of the test data set can be used as a training set of the neural network (usually, the ratio is greater than 80%), and a small part can be used as a test set (usually, the ratio is less than 20%).
The deep neural network may then be trained offline using a training set with the goal of constantly reducing the incidence of deadlock, livelock, latency of packets in nodes, etc. in NOC networks with a defined number of channels and single channel buffer capacity. Training can be performed by setting a network loss function to calculate a loss value, and finally, an optimal solution of routing strategy parameters, namely, an optimized routing strategy, is obtained. Parameters in the optimized routing strategy define information such as which direction a packet entering the node is allowed to preferentially pass through and which direction the packet is preferentially transferred to. The network loss function may perform weighted statistics on output parameters of each node (specifically, performance to be reduced is positive, such as deadlock occurrence rate, and performance to be improved is negative, such as injection rate), so that a final loss value reaches a preset threshold or does not decrease any more (that is, test performance reaches a standard). Of course, the determination conditions of the optimal solution may also be set separately, for example, the determination conditions corresponding to other performances such as the upper threshold of the deadlock occurrence rate and the lower threshold of the injection rate are set separately, and when the routing policy that satisfies all the determination conditions is used as the optimized routing policy. Specifically, a test set can be used for testing the neural network on line, and whether repeated iterative training is performed or not is determined according to a test result; and if the test performance is not ideal, repeatedly executing the training test on the deep neural network until an optimal utilization strategy is obtained.
S104, setting routing parameters of each node of the network on chip according to the optimized routing strategy.
Specifically, the priority of the data packet in each direction and the priority of each sending port of each node may be set according to an optimized routing policy.
Specifically, please refer to fig. 2, wherein the TX FIFO and the RO FIFO are a sending buffer and a receiving buffer, respectively, for establishing a channel/port together. The single node route, the priority of the packets from each direction, and to which port the packets are preferentially sent out are determined. For example, when the priority order of the packets in each direction is set as: EAST, NORTH, WESH, SOUTH, and the EAST packet is preferentially sent to the west port, the NORTH packet is preferentially sent to the SOUTH port, the west packet is preferentially sent to the EAST port, and the SOUTH packet is preferentially sent to the NORTH port. When the data packets are simultaneously transmitted in four directions, the data packets can be received and transmitted according to the directions of the data packets and the sequence of the northeast, the southwest and the northwest and based on the priority transmitting ports respectively corresponding to the data packets.
And after the routing parameters of each node of the network on chip are set, the routing strategy setting of the network on chip is completed. Therefore, the optimized routing strategy generated by the deep neural network can be used for guiding the circulation of data packets in the actual NOC network, and the communication performance of the network on chip can be improved.
By applying the method provided by the embodiment of the invention, the network-on-chip is tested by utilizing the network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies; creating a deep neural network matched with the on-chip network; training the deep neural network by using a test data set to obtain an optimized routing strategy; and setting routing parameters of each node of the network on chip according to the optimized routing strategy.
In the method, the network on chip is tested by utilizing a network test model under different routing strategies to obtain the network performance of the network on chip. And establishing a deep neural network matched with the on-chip network, and training the deep neural network based on the test data set, namely learning the deep neural network to obtain the incidence relation among all nodes of the on-chip network and the incidence relation of various routing configurations among the nodes, so that the deep neural network can finally simulate the processing mode of all nodes of the on-chip network under different routing strategies. And carrying out routing strategy optimization training based on the deep neural network to obtain an optimized routing strategy. And finally, setting routing parameters of each node of the network-on-chip according to the optimized routing strategy. Thus, the routing strategy of the network on chip can be optimized. Compared with the manual setting of the routing strategy, the method can reduce manual intervention, simplify the routing control process and improve the route strategy with better quality.
Example two:
corresponding to the above method embodiments, the embodiments of the present invention further provide an on-chip network route optimization device, and the on-chip network route optimization device described below and the on-chip network route optimization method described above may be referred to in a corresponding manner.
Referring to fig. 3, the apparatus includes the following modules:
a test data set obtaining module 101, configured to test a network on chip by using a network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies;
a deep neural network creating module 102, configured to create a deep neural network matching the on-chip network;
the routing strategy optimization module 103 is configured to train the deep neural network by using the test data set to obtain an optimized routing strategy;
and the routing configuration module 104 is configured to set routing parameters of each node of the network on chip according to the optimized routing policy.
By applying the device provided by the embodiment of the invention, the network-on-chip is tested by utilizing the network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies; creating a deep neural network matched with the on-chip network; training the deep neural network by using a test data set to obtain an optimized routing strategy; and setting routing parameters of each node of the network on chip according to the optimized routing strategy.
In the device, the network on chip is tested by utilizing a network test model under different routing strategies to obtain the network performance of the network on chip. And establishing a deep neural network matched with the on-chip network, and training the deep neural network based on the test data set, namely learning the deep neural network to obtain the incidence relation among all nodes of the on-chip network and the incidence relation of various routing configurations among the nodes, so that the deep neural network can finally simulate the processing mode of all nodes of the on-chip network under different routing strategies. And carrying out routing strategy optimization training based on the deep neural network to obtain an optimized routing strategy. And finally, setting routing parameters of each node of the network-on-chip according to the optimized routing strategy. Thus, the routing strategy of the network on chip can be optimized. Compared with manual setting of routing strategies, the device can reduce manual intervention, simplify the routing control process and improve the routing strategy which is better.
In a specific embodiment of the present invention, the test data set obtaining module 101 is specifically configured to, when a network test model is used to sequentially deploy a routing test policy on a network on chip, respectively corresponding network performance of each node; the network performance includes: and simultaneously inputting the number of data packets, the injection rate, the number of channels, the single-channel cache capacity, the deadlock occurrence rate, the livelock occurrence rate, the waiting time of the data packets in the nodes and the node positions.
In an embodiment of the present invention, the deep neural network creating module 102 is specifically configured to create a deep neural network having a size that matches the number of nodes of the on-chip network.
In an embodiment of the present invention, the deep neural network creating module 102 is specifically configured to create a deep neural network including an input layer, a hidden layer, and an output layer; and the routing parameters in the routing strategy of the network on chip are distributed in the deep neural network.
In a specific embodiment of the present invention, the routing policy optimization module 103 includes:
the optimization training unit is used for inputting the test data set into the deep neural network for routing strategy optimization training;
the loss value calculation unit is used for calculating a loss value by using a network loss function matched with the network requirement;
and the routing strategy optimization unit is used for determining the current routing strategy as the optimized routing strategy when the loss value is smaller than a preset threshold value.
In a specific embodiment of the present invention, the optimization training unit is specifically configured to divide the test data set into a training set and a test set; training the deep neural network by using a training set; testing the deep neural network by using a test set, and fixing the current parameters as final routing strategy parameters if the test performance reaches the standard; otherwise, adding the training set and the test set to continue training and testing until the test performance reaches the standard.
In a specific embodiment of the present invention, the routing configuration module 104 is specifically configured to set priorities of packets in each direction and priorities of sending ports of each node according to an optimized routing policy.
Example three:
corresponding to the above method embodiment, an embodiment of the present invention further provides an on-chip network route optimization device, and the on-chip network route optimization device described below and the on-chip network route optimization method described above may be referred to in a corresponding manner.
Referring to fig. 4, the network-on-chip route optimization device includes:
a memory D1 for storing computer programs;
a processor D2, configured to implement the steps of the network-on-chip route optimization method of the above-described method embodiments when executing the computer program.
Specifically, referring to fig. 5, a specific structural diagram of the on-chip network route optimization device provided in this embodiment is shown, where the on-chip network route optimization device may generate relatively large differences due to different configurations or performances, and may include one or more processors (CPUs) 322 (e.g., one or more processors) and a memory 332, and one or more storage media 330 (e.g., one or more mass storage devices) storing an application 342 or data 344. Memory 332 and storage media 330 may be, among other things, transient storage or persistent storage. The program stored on the storage medium 330 may include one or more modules (not shown), each of which may include a series of instructions operating on a data processing device. Still further, the central processor 322 may be configured to communicate with the storage medium 330, and execute a series of instruction operations in the storage medium 330 on the network-on-chip route optimization device 301.
The network-on-chip route optimization apparatus 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input-output interfaces 358, and/or one or more operating systems 341. Such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
The steps in the above described network-on-chip route optimization method may be implemented by the structure of a network-on-chip route optimization device.
Example four:
corresponding to the above method embodiment, an embodiment of the present invention further provides a readable storage medium, and a readable storage medium described below and an on-chip network route optimization method described above may be referred to in a corresponding manner.
A readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the network-on-chip route optimization method of the above-mentioned method embodiments.
The readable storage medium may be a usb disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various readable storage media capable of storing program codes.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
Claims (10)
1. A method for optimizing network-on-chip routing, comprising:
testing the network on chip by using a network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies;
creating a deep neural network matched with the on-chip network; specifically, parameters in a routing strategy are uniformly distributed on each layer of nodes in the deep neural network, the input of the deep neural network is a data packet, the output of the deep neural network is a score of network performance, the score is calculated by a network loss function, and the score is test performance;
training a deep neural network by using the test data set to obtain an optimized routing strategy;
and setting routing parameters of each node of the network on chip according to the optimized routing strategy.
2. The method for optimizing routing in a network-on-chip according to claim 1, wherein the testing the network-on-chip using the network test model to obtain the test data set comprises:
when the network test model is used for deploying the routing test strategy on the network on chip in sequence, the nodes respectively correspond to the network performance; the network performance includes: and simultaneously inputting the number of data packets, the injection rate, the number of channels, the single-channel cache capacity, the deadlock occurrence rate, the livelock occurrence rate, the waiting time of the data packets in the nodes and the node positions.
3. The method for optimizing routing of a network on a chip according to claim 1, wherein the creating a deep neural network matching the network on a chip comprises:
creating a deep neural network having a size that matches the number of nodes of the network-on-chip.
4. The method for optimizing routing for a network-on-chip according to claim 3, wherein the creating a deep neural network whose size matches the number of nodes of the network-on-chip comprises:
a deep neural network is created that includes an input layer, a hidden layer, and an output layer.
5. The method for optimizing routing of a network on a chip according to claim 1, wherein training a deep neural network using the test data set comprises:
inputting the test data set into the deep neural network for training;
calculating a loss value by using a network loss function matched with the network requirement;
and when the loss value is smaller than a preset threshold value, determining the current routing strategy as the optimized routing strategy.
6. The method for optimizing routing of a network on a chip according to claim 5, wherein training a deep neural network using the test data set comprises:
dividing the test data set into a training set and a test set;
training the deep neural network by using the training set;
testing the deep neural network by using the test set, and fixing the current parameters as final routing strategy parameters if the test performance reaches the standard; otherwise, adding the training set and the test set to continue training and testing until the test performance reaches the standard.
7. The method for optimizing routing of a network on chip according to claim 1, wherein setting routing parameters of each node of the network on chip according to the optimized routing policy comprises:
and setting the priority of the data packet in each direction of each node and the priority of each sending port according to the optimized routing strategy.
8. An on-chip network route optimization device, comprising:
the test data set acquisition module is used for testing the network on chip by using the network test model to obtain a test data set; the test data set comprises different routing test strategies and network performances corresponding to various routing test strategies;
the deep neural network creating module is used for creating a deep neural network matched with the on-chip network; specifically, parameters in a routing strategy are uniformly distributed on each layer of nodes in the deep neural network, the input of the deep neural network is a data packet, the output of the deep neural network is a score of network performance, the score is calculated by a network loss function, and the score is test performance;
the routing strategy optimization module is used for training the deep neural network by utilizing the test data set so as to obtain an optimized routing strategy;
and the routing configuration module is used for setting routing parameters of each node of the network on chip according to the optimized routing strategy.
9. An on-chip network route optimization device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the network-on-chip route optimization method according to any of claims 1 to 7 when executing the computer program.
10. A readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the network-on-chip route optimization method according to any one of claims 1 to 7.
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