CN105072032B - A kind of method and system of definite network-on-chip routed path - Google Patents
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Abstract
The invention discloses a kind of method and system of definite network-on-chip routed path, including：It is moved to from the vertical busses where source node in the vertical busses where destination node, reaches the first position of purpose level course；According to the horizontal position value of the first position and the horizontal position value of the destination node, the first position is calculated to the horizontal hop count of the destination node；According to the node total number of the horizontal hop count and the level course, according to predeterminated level layer routing algorithm, the horizontal route from the first position arrival destination node is obtained；This method and system can be according to network state dynamic adjustment routed paths, and actual effect shows that this method can improve handling capacity and reduce network delay, balances the flow distribution in network.
Description
Technical Field
The present invention relates to the field of chip architecture, and in particular, to a method and system for determining a network-on-chip routing path.
Background
The three-dimensional network on chip is developed on the basis of a three-dimensional integrated circuit process and a two-dimensional network on chip, and is mainly used for solving the problems of communication bottleneck and the like of a high-integration chip. The vertical connection line and the horizontal connection line of the three-dimensional network on a chip (noc) have structural difference, the internal connection line of the horizontal layer needs to cross over resource nodes to be connected with other routing units, the length of the connection line is the width of the resource nodes, the typical value is thousands of micrometers, and the three-dimensional integrated circuit technology allows the horizontal layers to be directly overlapped with each other, so that the distance in the vertical direction is only dozens of micrometers. The V-Spidergon three-dimensional topological structure is a mixed three-dimensional topology, and the vertical bus of the structure deeply influences the performance of the topology. Due to the limitation of the three-dimensional integrated circuit production process, the horizontal sub-layers can be connected only in the vertical direction, and the resource nodes between the horizontal sub-layers cannot be connected obliquely. Therefore, how to optimize the on-chip network routing path is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method for determining a network-on-chip routing path, which can dynamically adjust the routing path according to the network state, and the practical effect shows that the method can improve the throughput, reduce the network delay and balance the flow distribution in the network; it is yet another object of the present invention to provide a system for determining network-on-chip routing paths.
In order to solve the above technical problem, the present invention provides a method for determining a network-on-chip routing path, comprising:
moving from the vertical bus where the source node is located to the vertical bus where the destination node is located to reach the first position of the destination horizontal layer;
calculating to obtain the horizontal hop count from the first position to the destination node according to the horizontal position value of the first position and the horizontal position value of the destination node;
and according to the horizontal hop count and the total number of the nodes of the horizontal layer, obtaining a horizontal path from the first position to the destination node according to a preset horizontal layer routing algorithm.
Preferably, the predetermined horizontal layer routing algorithm includes: a first predetermined algorithm, wherein the first predetermined algorithm comprises:
dividing the horizontal hop count by the total number of nodes in the horizontal layer;
when the division result is not more than one fourth of the total number of the nodes of the horizontal layer, moving to the destination node according to the anticlockwise direction;
when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise;
when the division result is more than one fourth and less than one half of the total number of the nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; the moving to opposite intermediate node specifically includes: calculating the hop count from the first location to an intermediate node having one-half the total number of nodes in the horizontal layer from the destination node, and moving the first location to a second location having the same hop count on a clockwise basis from the destination node;
when the division result is less than three-quarters and more than one half of the total number of nodes of the horizontal layer, moving the first position to an opposite second position, and moving the second position to the destination node in a counterclockwise direction;
moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
Preferably, the predetermined horizontal layer routing algorithm includes: a second predetermined algorithm, wherein the second predetermined algorithm comprises:
dividing the horizontal hop count by the total number of nodes in the horizontal layer;
when the division result is not more than one fourth of the total number of the nodes of the horizontal layer, moving to the destination node according to the anticlockwise direction;
when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise;
when the division result is more than one fourth and less than one half of the total number of nodes of the horizontal layer, moving the first position clockwise to an intermediate node which is one half of the total number of nodes of the horizontal layer away from the destination node, and moving the first position from the intermediate node to the destination node;
moving said first position from said intermediate node to said destination node in a counter-clockwise direction when the result of the division is less than three-quarters and greater than one-half the total number of nodes of said horizontal tier;
moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
Preferably, the predetermined horizontal layer routing algorithm includes a first predetermined algorithm and a second predetermined algorithm, and further includes:
and when the path hops from the first position to the destination node are the same, comparing the cache usage amounts of the output ports of the two paths, and using the path where the output port with the small cache usage amount is located to move the first position to the destination node.
Preferably, the method further comprises the following steps:
establishing two virtual channels in the vertical direction;
when the vertical position value of the source node is larger than that of the destination node, a first virtual channel is used;
when the vertical position value of the source node is smaller than that of the destination node, a second virtual channel is used;
and/or, two virtual channels are established in the horizontal direction;
when the horizontal position value of the first position is larger than the horizontal position value of the destination node, a first virtual channel is used;
and when the horizontal position value of the first position is smaller than the horizontal position value of the destination node, using a second virtual channel.
Preferably, the method further comprises the following steps:
when the vertical bus load is greater than a threshold, a free bus is determined by the horizontal sublayer.
The invention provides a system for determining a network-on-chip routing path, which comprises:
the vertical moving module is used for moving the source node from the vertical bus to the destination node and reaching the first position of the destination horizontal layer;
the calculation module is used for calculating the horizontal hop count from the first position to the destination node according to the horizontal position value of the first position and the horizontal position value of the destination node;
and the horizontal moving module is used for obtaining a horizontal path from the first position to the destination node according to the horizontal hop count and the total number of the nodes in the horizontal layer and a preset horizontal layer routing algorithm.
Preferably, the horizontal movement module includes: a first predetermined algorithm unit, wherein the first predetermined algorithm unit comprises:
a first calculation unit, configured to divide the horizontal hop count by a total number of nodes of the horizontal layer;
a first moving unit for moving to the destination node counterclockwise when the division result is not more than a quarter of the total number of nodes of the horizontal layer; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise; when the division result is more than one fourth and less than one half of the total number of the nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; the moving to opposite intermediate node specifically includes: calculating the hop count from the first location to an intermediate node having one-half the total number of nodes in the horizontal layer from the destination node, and moving the first location to a second location having the same hop count on a clockwise basis from the destination node; when the division result is less than three-quarters and more than one half of the total number of nodes of the horizontal layer, moving the first position to an opposite second position, and moving the second position to the destination node in a counterclockwise direction; moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
Preferably, the horizontal movement module includes: a second predetermined algorithm unit, wherein the first predetermined algorithm unit comprises:
a second calculation unit, configured to divide the horizontal hop count by a total number of nodes in the horizontal layer;
a second moving unit for moving to the destination node counterclockwise when the division result is not more than a quarter of the total number of nodes of the horizontal layer; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise; when the division result is more than one fourth and less than one half of the total number of nodes of the horizontal layer, moving the first position clockwise to an intermediate node which is one half of the total number of nodes of the horizontal layer away from the destination node, and moving the first position from the intermediate node to the destination node; moving said first position from said intermediate node to said destination node in a counter-clockwise direction when the result of the division is less than three-quarters and greater than one-half the total number of nodes of said horizontal tier; moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
Preferably, the method has both the first predetermined algorithm unit and the second predetermined algorithm unit, and further includes:
and the selection module is used for comparing the cache usage amount of the output ports of the two paths when the path hop numbers from the first position to the destination node are the same, and moving the first position to the destination node by using the path where the output port with the small cache usage amount is located.
The method and system for determining the network routing path on the chip provided by the invention comprises the following steps: moving from the vertical bus where the source node is located to the vertical bus where the destination node is located to reach the first position of the destination horizontal layer; calculating to obtain the horizontal hop count from the first position to the destination node according to the horizontal position value of the first position and the horizontal position value of the destination node; according to the horizontal hop count and the total number of the nodes of the horizontal layer, obtaining a horizontal path from the first position to the destination node according to a preset horizontal layer routing algorithm;
the method and the system can firstly carry out deterministic routing on the data packet in the vertical direction, and then self-adaptively select the two-dimensional routing algorithm to route to the destination node according to the link utilization rate after the data packet reaches the destination layer, thereby balancing the flow distribution in the network. The routing path is dynamically adjusted according to the network state, and the practical effect shows that the method can improve the throughput, reduce the network delay and balance the flow distribution in the network.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for determining a network-on-chip routing path according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a first predetermined algorithm effect provided by an embodiment of the present invention;
FIG. 3 is a diagram illustrating a second predetermined algorithm effect provided by the embodiment of the present invention;
fig. 4 is a block diagram of a system for determining a network-on-chip routing path according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a method for determining a network-on-chip routing path, which can dynamically adjust the routing path according to the network state, and the practical effect shows that the method can improve the throughput, reduce the network delay and balance the flow distribution in the network.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a method for determining a network routing path on a chip according to an embodiment of the present invention, where the method includes:
step s100, moving from the vertical bus where the source node is located to the vertical bus where the destination node is located, and reaching the first position of the destination horizontal layer;
step s110, calculating to obtain a horizontal hop count from the first position to the destination node according to the horizontal position value of the first position and the horizontal position value of the destination node;
and step s120, obtaining a horizontal path from the first position to the destination node according to the horizontal hop count and the total number of the nodes in the horizontal layer and a predetermined horizontal layer routing algorithm.
Firstly, enabling a data packet to reach a data bus where a destination node is located on a vertical layer, and finding a path in a horizontal direction by using a predetermined horizontal layer routing algorithm according to the hop count required from a first position to the destination node and the relationship between the hop count and the total number of nodes on the horizontal layer, namely the maximum hop count, on the basis of the hop count calculated on the horizontal layer; it can therefore be seen that the predetermined level algorithm determines the actual condition of the path at the level of the level, and the efficiency of the algorithm determines the network-on-chip routing path efficiency.
The process is illustrated by way of example:
let the node location in the network be (i, j), i denotes the location of the node in the horizontal layer, and j denotes its location in the vertical direction. The positions of the nodes in the horizontal layer direction are numbered in the clockwise direction. If the source node (i)src,jsrc) And a target node (i)dest,jdest) Distance in vertical direction | jdest-jsrcIf | is not equal to 0, then preferentially route in the vertical direction to | jdest-jsrcI equals 0 and then selects the exit in the horizontal layer according to the shortest path principle. The algorithm calculates the distance between the current node and the destination node on the horizontal layer according to the following formula:
Dist＝((idest-isrc)+m)mod m
in the above equation, m represents the number of nodes on the horizontal layer. In effect, Dist represents the number of horizontal hops in the clockwise direction for the current node and the target node. Here, the calculation is performed in a modulo manner, but of course, the hop count of the destination node and the first location in the horizontal plane may also be obtained in other manners.
Preferably, the predetermined horizontal layer routing algorithm may include: a first predetermined algorithm and/or a second predetermined algorithm; the present invention may have only the first predetermined algorithm, only the second predetermined algorithm, or both of them. The invention is herein by way of example only. One of the two algorithms is that the routing unit preferentially uses the channel connected to the opposite node, and if the distance between the destination node and the source node on the ring is not more than half of the total number of nodes on the ring, the data packet can select the clockwise direction or the anticlockwise direction as the channel outlet according to the shortest path principle. If the distance between the destination node and the source node on the ring exceeds half of the total number of the nodes on the ring, the data packet is firstly routed to the opposite node on the ring through a channel connected to the opposite node, and then the shortest path route is selected. The second option is to route the data packet opposite to the first to the node opposite to the destination node and then to the destination node through the opposite channel.
Referring to fig. 2, the first predetermined algorithm may include:
dividing the horizontal hop count by the total number of nodes in the horizontal layer;
when the division result is not more than one fourth of the total number of the nodes of the horizontal layer, moving to the destination node according to the anticlockwise direction;
for example, the four blocks identified as 1 through 4 in fig. 2 are all moved counterclockwise to destination node 0. The counter-clockwise direction may be a special case listed here, which may be changed according to the actual situation, i.e. when the division result is not more than a quarter of the total number of nodes of the horizontal layer, the destination node is moved in the first direction; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, moving to the destination node according to a second direction; the directions in the subsequent first predetermined algorithm are only lists, and can be changed according to the algorithm actually used by the user, and are not listed.
When the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise;
for example, the four blocks labeled 12 through 15 in fig. 2 are all moved clockwise to destination node 0.
When the division result is more than one fourth and less than one half of the total number of the nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; the moving to opposite intermediate node specifically includes: calculating the hop count from the first location to an intermediate node having one-half the total number of nodes in the horizontal layer from the destination node, and moving the first location to a second location having the same hop count on a clockwise basis from the destination node;
for example, three positions 5, 6 and 7 in fig. 2, if 5 is the first position, 5 is first moved to the second opposite position 13, and then moved from 13 to the destination node 0.
When the division result is less than three-quarters and more than one half of the total number of nodes of the horizontal layer, moving the first position to an opposite second position, and moving the second position to the destination node in a counterclockwise direction;
for example, three positions 11, 10 and 9 in fig. 2, if 10 is the first position, 10 is first moved to the second opposite position 3, and then moved from 3 to the destination node 0.
Moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier;
such as the location identified by 8 in fig. 2, to destination node 0.
The first predetermined algorithm may be adaptively changed in a counterclockwise order and a clockwise order, and the algorithm is a new algorithm.
Referring to fig. 3, the second predetermined algorithm may include:
dividing the horizontal hop count by the total number of nodes in the horizontal layer;
when the division result is not more than one fourth of the total number of the nodes of the horizontal layer, moving to the destination node according to the anticlockwise direction;
for example, the four blocks labeled 1 through 4 in fig. 3 are all moved counterclockwise to destination node 0.
When the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise;
for example, the four blocks labeled 12 through 15 in fig. 3 are all moved clockwise to destination node 0.
When the division result is more than one fourth and less than one half of the total number of nodes of the horizontal layer, moving the first position clockwise to an intermediate node which is one half of the total number of nodes of the horizontal layer away from the destination node, and moving the first position from the intermediate node to the destination node;
for example, three positions 5, 6 and 7 in fig. 3, if 5 is the first position, 5 is first moved to the intermediate node 8, and then moved from 8 to the opposite destination node 0.
Moving said first position from said intermediate node to said destination node in a counter-clockwise direction when the result of the division is less than three-quarters and greater than one-half the total number of nodes of said horizontal tier;
for example, three positions 11, 10 and 9 in fig. 3, if 9 is the first position, 9 is first moved to the intermediate node 8, and then moved from 8 to the opposite destination node 0.
Moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
For example, the location of the label 8 in fig. 3 may be moved directly to the destination node 0 by the move to opposite algorithm.
The second predetermined algorithm may be a new algorithm after adaptive transformation of the counterclockwise sequence and the clockwise sequence.
As can be seen from analysis in the algorithm, in the case that Dist is less than m/4 and greater than 3m/4, clockwise and counterclockwise directions are respectively selected to be shortest on the path, and the rest has two equivalent routing methods. The algorithm will select any one of the paths as the routing path according to the degree of blocking of the egress link.
Wherein the first predetermined algorithm and the second predetermined algorithm each have outlet passages in three directions, clockwise, counterclockwise and opposite.
The method for determining the routing path of the network-on-chip is based on a V-Spidergon structure, and has an outlet channel with clockwise direction, anticlockwise direction and opposite direction, and a channel with vertical direction. The data packet is firstly deterministically routed in the vertical direction, and then reaches a destination layer, and then a horizontal layer routing algorithm such as a first subscription algorithm is adaptively selected according to the link utilization rate to reach a destination node.
Based on the technical scheme, the method for determining the network-on-chip routing path provided by the embodiment of the invention is suitable for the self-adaptive routing algorithm of the V-Spidergon hybrid three-dimensional network structure. The routing path can be dynamically adjusted according to the network state, and the practical effect shows that the routing algorithm can improve the throughput and reduce the network delay. The algorithm has outlet channels in the clockwise, counter-clockwise and opposite directions, as well as channels in the vertical direction. The data packet is firstly subjected to deterministic routing in the vertical direction, and then is self-adaptively selected to be routed to a destination node according to the link utilization rate after reaching a destination layer, so that the flow distribution in a network can be balanced.
Based on the above technical solution, another specific embodiment of the present invention may further include:
establishing two virtual channels in the vertical direction;
when the vertical position value of the source node is larger than that of the destination node, a first virtual channel is used;
when the vertical position value of the source node is smaller than that of the destination node, a second virtual channel is used;
and/or, two virtual channels are established in the horizontal direction;
when the horizontal position value of the first position is larger than the horizontal position value of the destination node, a first virtual channel is used;
and when the horizontal position value of the first position is smaller than the horizontal position value of the destination node, using a second virtual channel.
All physical channels in the topology are divided into two virtual channels, and the using sequence of the virtual channels is established in the algorithm. The magnitude of the vertical source coordinates and the magnitude of the destination node coordinates may be compared first in the vertical direction. If the source coordinates are greater than the destination node coordinates, the first virtual channel VC1 is used, and the second virtual channel VC2 is used instead. The same judgment method is also used in the horizontal direction. At the moment, data in the virtual channel can only flow to one direction without generating a closed-loop condition of the channel, thereby ensuring that the method has no deadlock.
Namely, virtual channels are used to avoid deadlock problems based on a V-Spidergon topology, and two independent flit buffers are established in an output queue buffer to avoid the occurrence of ring link dependence in a path.
Based on the above technical solution, in another specific embodiment of the present invention, when the predetermined horizontal layer routing algorithm includes a first predetermined algorithm and a second predetermined algorithm, the method may further include:
and when the path hops from the first position to the destination node are the same, comparing the cache usage amounts of the output ports of the two paths, and using the path where the output port with the small cache usage amount is located to move the first position to the destination node.
The algorithm adaptively searches the equivalent minimum path between a source node and a destination node, and when two completely equivalent paths exist, the routing algorithm selects a port with lighter load as an output port according to the buffer use condition of the output port so as to balance the traffic distribution in the network.
The routing algorithm selects the shortest path to realize data transmission, so that the fixed port is selected as an output port when the node horizontal distance dist is less than m/4, more than 3m/4 and equal to m/2. In other cases, the topology has two completely equivalent paths, and the data flow is as shown in fig. 2 and fig. 3, then the port with lighter load is selected as the output port according to the buffer usage of the output port, so as to balance the traffic distribution in the network.
Based on the above technical solution, another specific embodiment of the present invention may further include, on the basis of any one of the above embodiments:
when the vertical bus load is greater than a threshold, a free bus is determined by the horizontal sublayer.
In consideration of the link congestion state and the balanced network traffic, the horizontal sublayer can be used for searching for a free vertical bus under the condition of high bus load so as to reduce the bus load and prevent link congestion.
Based on the technical scheme, the method for determining the network-on-chip routing path provided by the embodiment of the invention is suitable for the self-adaptive routing algorithm of the V-Spidergon hybrid three-dimensional network structure. The routing path can be dynamically adjusted according to the network state, and the practical effect shows that the routing algorithm can improve the throughput and reduce the network delay. The algorithm has outlet channels in the clockwise, counter-clockwise and opposite directions, as well as channels in the vertical direction. The data packet is firstly subjected to deterministic routing in the vertical direction, and then is self-adaptively selected to be routed to a destination node according to the link utilization rate after reaching a destination layer, so that the flow distribution in a network can be balanced. Dividing all physical channels in the topology into two virtual channels, and establishing the use sequence of the virtual channels in the algorithm to avoid the occurrence of deadlock; when two completely equivalent paths exist, the routing algorithm selects a port with lighter load as an output port according to the buffer use condition of the output port so as to balance the flow distribution in the network; under the condition of high bus load, a horizontal sublayer can firstly find a free vertical bus so as to reduce the bus load and prevent link congestion.
The embodiment of the invention provides a method for determining a network-on-chip routing path, which can dynamically adjust the routing path according to a network state.
In the following, the system for determining a network-on-chip routing path according to the embodiments of the present invention is introduced, and the system for determining a network-on-chip routing path described below and the method for determining a network-on-chip routing path described above may be referred to correspondingly.
Referring to fig. 4, fig. 4 is a block diagram illustrating a system for determining a network routing path on a chip according to an embodiment of the present invention; the system may include:
a vertical moving module 100, configured to move from a vertical bus where a source node is located to a vertical bus where a destination node is located, to a first position of a destination horizontal layer;
a calculating module 200, configured to calculate, according to the horizontal position value of the first position and the horizontal position value of the destination node, a horizontal hop count from the first position to the destination node;
a horizontal moving module 300, configured to obtain a horizontal path from the first location to the destination node according to a predetermined horizontal layer routing algorithm, according to the horizontal hop count and the total number of nodes in the horizontal layer.
Preferably, the horizontal movement module 300 includes: a first predetermined algorithm unit and/or a second predetermined algorithm unit; wherein,
the first predetermined algorithm unit comprises:
a first calculation unit, configured to divide the horizontal hop count by a total number of nodes of the horizontal layer;
a first moving unit for moving to the destination node clockwise when the division result is not more than a quarter of the total number of nodes of the horizontal layer; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise; when the division result is more than one fourth and less than one half of the total number of the nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; the moving to opposite intermediate node specifically includes: calculating the hop count from the first location to an intermediate node having one-half the total number of nodes in the horizontal layer from the destination node, and moving the first location to a second location having the same hop count on a clockwise basis from the destination node; when the division result is less than three-quarters and more than one half of the total number of nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier;
the second predetermined algorithm unit comprises:
a second calculation unit, configured to divide the horizontal hop count by a total number of nodes in the horizontal layer;
a second moving unit for moving to the destination node clockwise when the division result is not more than a quarter of the total number of nodes of the horizontal layer; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise; when the division result is more than one fourth and less than one half of the total number of nodes of the horizontal layer, moving the first position clockwise to an intermediate node which is one half of the total number of nodes of the horizontal layer away from the destination node, and moving the first position from the intermediate node to the destination node; when the division is less than three-quarters and greater than one-half of the total number of nodes of the horizontal tier, moving the first position clockwise from the intermediate node to the destination node to an intermediate node having one-half of the total number of nodes of the horizontal tier from the intermediate node to the destination node; moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
Preferably, the system has both the first predetermined algorithm unit and the second predetermined algorithm unit, and the system may further include:
and the selection module is used for comparing the cache usage amount of the output ports of the two paths when the path hop numbers from the first position to the destination node are the same, and moving the first position to the destination node by using the path where the output port with the small cache usage amount is located.
Preferably, based on the above system, the system may further include:
the vertical channel module is used for establishing two virtual channels in the vertical direction; when the vertical position value of the source node is larger than that of the destination node, a first virtual channel is used; when the vertical position value of the source node is smaller than that of the destination node, a second virtual channel is used; and/or the presence of a gas in the gas,
the horizontal channel module is used for establishing two virtual channels in the horizontal direction; when the horizontal position value of the first position is larger than the horizontal position value of the destination node, a first virtual channel is used; and when the horizontal position value of the first position is smaller than the horizontal position value of the destination node, using a second virtual channel.
Based on any of the above systems, the system may further include:
and the judging module is used for determining the idle bus through the horizontal sublayer when the load of the vertical bus is greater than the threshold value.
Based on the technical scheme, the system for determining the routing path of the network on chip provided by the embodiment of the invention is suitable for a self-adaptive routing algorithm of a V-Spidergon hybrid three-dimensional network structure. The routing path can be dynamically adjusted according to the network state, and the practical effect shows that the routing algorithm can improve the throughput and reduce the network delay. The algorithm has outlet channels in the clockwise, counter-clockwise and opposite directions, as well as channels in the vertical direction. The data packet is firstly subjected to deterministic routing in the vertical direction, and then is self-adaptively selected to be routed to a destination node according to the link utilization rate after reaching a destination layer, so that the flow distribution in a network can be balanced. Dividing all physical channels in the topology into two virtual channels, and establishing the use sequence of the virtual channels in the algorithm to avoid the occurrence of deadlock; when two completely equivalent paths exist, the routing algorithm selects a port with lighter load as an output port according to the buffer use condition of the output port so as to balance the flow distribution in the network; under the condition of high bus load, a horizontal sublayer can firstly find a free vertical bus so as to reduce the bus load and prevent link congestion.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The method and system for determining network routing path on chip provided by the present invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (6)
1. A method of determining a network-on-chip routing path, comprising:
moving from the vertical bus where the source node is located to the vertical bus where the destination node is located to reach the first position of the destination horizontal layer;
calculating to obtain the horizontal hop count from the first position to the destination node according to the horizontal position value of the first position and the horizontal position value of the destination node;
according to the horizontal hop count and the total number of the nodes of the horizontal layer, obtaining a horizontal path from the first position to the destination node according to a preset horizontal layer routing algorithm;
wherein the predetermined horizontal layer routing algorithm is a first predetermined algorithm and/or a second predetermined algorithm,
the first predetermined algorithm comprises:
dividing the horizontal hop count by the total number of nodes in the horizontal layer;
when the division result is not more than one fourth of the total number of the nodes of the horizontal layer, moving to the destination node according to the anticlockwise direction;
when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise;
when the division result is more than one fourth and less than one half of the total number of the nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; the moving to opposite intermediate node specifically includes: calculating the hop count from the first location to an intermediate node having one-half the total number of nodes in the horizontal layer from the destination node, and moving the first location to a second location having the same hop count on a clockwise basis from the destination node;
when the division result is less than three-quarters and more than one half of the total number of nodes of the horizontal layer, moving the first position to an opposite second position, and moving the second position to the destination node in a counterclockwise direction;
moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier;
the second predetermined algorithm comprises:
dividing the horizontal hop count by the total number of nodes in the horizontal layer;
when the division result is not more than one fourth of the total number of the nodes of the horizontal layer, moving to the destination node according to the anticlockwise direction;
when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise;
when the division result is more than one fourth and less than one half of the total number of nodes of the horizontal layer, moving the first position clockwise to an intermediate node which is one half of the total number of nodes of the horizontal layer away from the destination node, and moving the first position from the intermediate node to the destination node;
moving said first position from said intermediate node to said destination node in a counter-clockwise direction when the result of the division is less than three-quarters and greater than one-half the total number of nodes of said horizontal tier;
moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
2. The method of claim 1, wherein the predetermined horizontal layer routing algorithms comprise a first predetermined algorithm and a second predetermined algorithm, further comprising:
and when the path hops from the first position to the destination node are the same, comparing the cache usage amounts of the output ports of the two paths, and using the path where the output port with the small cache usage amount is located to move the first position to the destination node.
3. The method of claim 1, further comprising:
establishing two virtual channels in the vertical direction;
when the vertical position value of the source node is larger than that of the destination node, a first virtual channel is used;
when the vertical position value of the source node is smaller than that of the destination node, a second virtual channel is used;
and/or, two virtual channels are established in the horizontal direction;
when the horizontal position value of the first position is larger than the horizontal position value of the destination node, a first virtual channel is used;
and when the horizontal position value of the first position is smaller than the horizontal position value of the destination node, using a second virtual channel.
4. The method of claim 3, further comprising:
when the vertical bus load is greater than a threshold, a free bus is determined by the horizontal sublayer.
5. A system for determining a network-on-chip routing path, comprising:
the vertical moving module is used for moving the source node from the vertical bus to the destination node and reaching the first position of the destination horizontal layer;
the calculation module is used for calculating the horizontal hop count from the first position to the destination node according to the horizontal position value of the first position and the horizontal position value of the destination node;
a horizontal moving module, configured to obtain a horizontal path from the first location to the destination node according to a predetermined horizontal layer routing algorithm, according to the horizontal hop count and the total number of nodes in the horizontal layer;
wherein the horizontal movement module comprises a first predetermined algorithm unit and/or a second predetermined algorithm unit,
the first predetermined algorithm unit comprises:
a first calculation unit, configured to divide the horizontal hop count by a total number of nodes of the horizontal layer;
a first moving unit for moving to the destination node counterclockwise when the division result is not more than a quarter of the total number of nodes of the horizontal layer; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise; when the division result is more than one fourth and less than one half of the total number of the nodes of the horizontal layer, moving the first position to a second opposite position, and moving the second position to the destination node clockwise; the moving to opposite intermediate node specifically includes: calculating the hop count from the first location to an intermediate node having one-half the total number of nodes in the horizontal layer from the destination node, and moving the first location to a second location having the same hop count on a clockwise basis from the destination node; when the division result is less than three-quarters and more than one half of the total number of nodes of the horizontal layer, moving the first position to an opposite second position, and moving the second position to the destination node in a counterclockwise direction; moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier;
the second predetermined algorithm unit comprises:
a second calculation unit, configured to divide the horizontal hop count by a total number of nodes in the horizontal layer;
a second moving unit for moving to the destination node counterclockwise when the division result is not more than a quarter of the total number of nodes of the horizontal layer; when the division result is not less than the total number of the nodes of the three-quarter horizontal layer, the destination node is moved clockwise; when the division result is more than one fourth and less than one half of the total number of nodes of the horizontal layer, moving the first position clockwise to an intermediate node which is one half of the total number of nodes of the horizontal layer away from the destination node, and moving the first position from the intermediate node to the destination node; moving said first position from said intermediate node to said destination node in a counter-clockwise direction when the result of the division is less than three-quarters and greater than one-half the total number of nodes of said horizontal tier; moving the first location to the destination node when the result of the division equals one-half of the total number of nodes of the horizontal tier.
6. The system of claim 5, having both the first predetermined algorithm unit and the second predetermined algorithm unit, further comprising:
and the selection module is used for comparing the cache usage amount of the output ports of the two paths when the path hop numbers from the first position to the destination node are the same, and moving the first position to the destination node by using the path where the output port with the small cache usage amount is located.
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| US10454830B2 (en) * | 2016-05-05 | 2019-10-22 | City University Of Hong Kong | System and method for load balancing in a data network |
| CN110958177B (en) * | 2019-11-07 | 2022-02-18 | 浪潮电子信息产业股份有限公司 | Network-on-chip route optimization method, device, equipment and readable storage medium |
| CN111966595B (en) * | 2020-08-13 | 2024-04-05 | 安徽芯纪元科技有限公司 | Method for positioning core in software debugging system and method for transmitting debugging message |
| CN113709040B (en) * | 2021-08-31 | 2023-04-07 | 中国电子科技集团公司第五十八研究所 | Package-level network routing algorithm based on extensible interconnected die |
| CN115955429B (en) * | 2023-02-15 | 2023-07-21 | 北京象帝先计算技术有限公司 | Network-on-chip routing method, device, system and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388834A (en) * | 2008-10-20 | 2009-03-18 | 电子科技大学 | Method for constructing network on three-dimensional chip |
| CN102333038A (en) * | 2011-10-21 | 2012-01-25 | 上海交通大学 | Non deadlock routing method based on network on chip |
| CN104079480A (en) * | 2014-05-30 | 2014-10-01 | 中国科学院计算技术研究所 | Routing method and system of network on three-dimensional integrated circuit chip |
| CN104092617A (en) * | 2014-05-30 | 2014-10-08 | 中国科学院计算技术研究所 | Three-dimensional integrated circuit on-chip network routing method and system thereof |
-
2015
- 2015-09-17 CN CN201510594792.4A patent/CN105072032B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388834A (en) * | 2008-10-20 | 2009-03-18 | 电子科技大学 | Method for constructing network on three-dimensional chip |
| CN102333038A (en) * | 2011-10-21 | 2012-01-25 | 上海交通大学 | Non deadlock routing method based on network on chip |
| CN104079480A (en) * | 2014-05-30 | 2014-10-01 | 中国科学院计算技术研究所 | Routing method and system of network on three-dimensional integrated circuit chip |
| CN104092617A (en) * | 2014-05-30 | 2014-10-08 | 中国科学院计算技术研究所 | Three-dimensional integrated circuit on-chip network routing method and system thereof |
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