CN105577539B - A kind of method for routing and system towards irregular three dimensional integrated circuits network-on-chip - Google Patents
A kind of method for routing and system towards irregular three dimensional integrated circuits network-on-chip Download PDFInfo
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- CN105577539B CN105577539B CN201610057261.6A CN201610057261A CN105577539B CN 105577539 B CN105577539 B CN 105577539B CN 201610057261 A CN201610057261 A CN 201610057261A CN 105577539 B CN105577539 B CN 105577539B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/02—Topology update or discovery
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/12—Shortest path evaluation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/14—Routing performance; Theoretical aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/24—Multipath
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/48—Routing tree calculation
Abstract
The present invention proposes a kind of method for routing and system towards irregular three dimensional integrated circuits network-on-chip, this method includes the topological structure according to the irregular three dimensional integrated circuits network-on-chip, judge to route data packet using the Fault-tolerant Routing Algorithm based on Hamilton path, or the Fault-tolerant Routing Algorithm based on spanning tree route data packet；It is route data packet according to the Fault-tolerant Routing Algorithm based on the Hamilton path, is used according to the location determination of source node and destination node and carries out router operating system according to the sequence of node serial number monotone increasing or monotonic decreasing；It is route data packet according to the Fault-tolerant Routing Algorithm based on the spanning tree, then selects spanning-tree root node, according to the position of root node and source node and destination node, transmission path is selected to complete the transmission of the data packet.
Description
Technical field
The present invention relates to the technical fields of integrated circuit, more particularly to a kind of to surf the Internet towards irregular three dimensional integrated circuits piece
The method for routing and system of network.
Background technology
Three-dimensional integration technology is that a kind of device layers stack that chip is different gathers into folds, a kind of encapsulation of Vertical collection together
Technology (Banerjee K, et al., " 3-D ICs:a novel chip design for improving deep-
submicrometer interconnect performance and systems-on-chip integration,”in
Proceedings of the IEEE,Volume:89,Issue:5,2001,pp.602-633.).This technology can shorten
Physical connection length in chip has the function that reduce Time Delay of Systems and power consumption.Fig. 1 is a simple 4*2*3 three-dimensional chip
The schematic diagram of network-on-chip (network-on-chip, NoC), topological structure are common three-dimensional Mesh structures.There are 3 in figure
Different components layer, 24 processing units (processing element, PE) be separately connected respectively different router node (under
Claim " node "), it is interconnected by horizontally or vertically mode between node.
Network topology is an important framework attribute of network on three-dimensional chip, and the regular network topology of network on three-dimensional chip has
Many kinds, such as three-dimensional Mesh, three-dimensional Torus, three-dimensional Folded Torus and three-dimensional BFT (Butterfly Fat-Tree)
Deng, however, in actual industrial quarters three-dimensional multiprocessor chip (chip multi-processor, CMP), since processing is single
Member is generally used isomery mode and designs, and different processing units is usually arranged as different function modules to meet practical application
Demand, for example, certain processing units can dispose processor, other processing units can be embedded in two level or three-level cache
Deng, therefore, the network-on-chip topology of three-dimensional CMP is mostly irregular topology, specifically, in network each device layer structure
All differ, and each node and its vertical distribution linked up and down between corresponding neighbor node be also it is heterogeneous,
The irregular network on three-dimensional chip of typical case as shown in Figure 2.
Since the complexity and integrated level of three dimensional integrated circuits are continuously improved, the communication effect of network-on-chip is significantly impacted
Rate, while the failure occurrence probability of component in network being caused also accordingly to increase, in order to ensure the normal communication of network on three-dimensional chip,
It needs to introduce fault-tolerance approach appropriate, in general, the failure of network-on-chip is divided into transient state failure and permanent fault, these failures
It is likely to occur in the components such as the link between processing unit, network interface, router or router, in the present invention, we
It is primarily upon permanent link failure common in network, this kind of failure cannot be repaired if occurring, for network-on-chip
Communication will generate the influence even more serious than transient state link failure, it should be noted that due to the generation of permanent fault
The network topology structure of rule originally may also be caused to have the characteristics that irregular, this situation is equally applicable to proposition of the present invention
Method and system.
It is directed to the fault-tolerance approach research comparative maturity of traditional two-dimentional network-on-chip both at home and abroad, but for three-dimensional plate
The related ends of upper network, especially Irregular topology structure three-dimensional network-on-chip (calling in the following text " irregular network on three-dimensional chip ") are then
It is less, it is however generally that, towards there are the fault-tolerance approaches of the network-on-chip of permanent link failure to be generally divided into following a few classes：1) make
Inoperative component is replaced with redundant component；2) data packet is made to avoid faulty section by adding peripheral logical circuit around trouble unit
Domain；3) reliable routing method is used, data packet is directly controlled and bypasses broken link.
In general, how network-on-chip scale is smaller, the limited present situation of Resources on Chip for major applications design, design
The fault-tolerance approach of low cost and high reliability is most important for ensureing the communication quality of such network on three-dimensional chip, due to redundancy
Technology and periphery circuit design are required for being transformed the physical arrangement of chip, will produce a degree of area and power consumption
Expense, and the bigger expense of circuit scale is more apparent, on the other hand, reliable routing method is as a kind of network-on-chip of lightweight
Fault-tolerance approach will not only change the structure of chip, and can continue to complete communication task in network failure, and ensure compared with
High communication performance, such method are widely used in two and three dimensions network-on-chip, but are mainly limited to the three-dimensional of rule
Network topology structure.
Firstly, it is necessary to which explanation, Virtual Channel (virtual channel, VC) and steering limitation (steering model etc.) are
Two kinds of main network-on-chip communicating abstracts that can destroy rely on the formation of ring (calling in the following text " abstract ring "), to deadlock prevention phenomenon
The key technology of generation.
Existing achievement in research is main insufficient as follows：
1) need to avoid the generation of network lock-up using high-cost VC technologies.The use of Virtual Channel can introduce larger face
Product expense and complicated control logic, are not suitable for the circuit design stringent to cost requirement.
Even if 2) do not use Virtual Channel technology, and the steering model of low cost is used, or introduces new theory for keeping away
Exempt from deadlock, it is also possible to which the problem of bringing other, for example, since network structure is irregular, single steering model can cause it to draw
There is the situation that can not be executed in the routing algorithm led, and introduces the support that multiple steering models then need VC technologies；In addition, simple
Introducing certain specific path routing data packets, there is also hidden danger, i.e., possibly can not be looked in many irregular network on three-dimensional chip
Go out qualified specific path.
3) the port selection mechanism of many existing schemes uses randomly selected strategy, i.e., not unique in legal port
In the case of randomly choose a port output data packet, conflict area cannot be bypassed well, cause network communication performance relatively low.
Above 3 points directly result in existing achievement and have three big defects：First, it cannot be guaranteed that higher communication performance is (main
Including communication delay and throughput two indices)；Second, the reliability index of communication is relatively low；Third, higher overhead.
Invention content
In view of the deficiencies of the prior art, the present invention proposes a kind of routing towards irregular three dimensional integrated circuits network-on-chip
Method and system.
The present invention proposes a kind of method for routing towards irregular three dimensional integrated circuits network-on-chip, including：
Step 1, according to the topological structure of the irregular three dimensional integrated circuits network-on-chip, judge using based on Chinese Mill
The Fault-tolerant Routing Algorithm in path route data packet, or the Fault-tolerant Routing Algorithm based on spanning tree route data packet；
Step 2, according to based on the Hamilton path Fault-tolerant Routing Algorithm route data packet, according to source node with
The location determination of destination node is used carries out router operating system, the number according to the sequence of node serial number monotone increasing or monotonic decreasing
During being transmitted along the Hamilton path chosen according to packet, make data packet often pass through a node all apart from destination node more
Further；
Step 3, it is route data packet according to the Fault-tolerant Routing Algorithm based on the spanning tree, then selects spanning-tree root section
Point selects transmission path to complete the transmission of the data packet according to the position of root node and source node and destination node；
Step 4, when the data packet reaches node, the address of the address of node and the destination node of arrival is checked
Whether identical, if identical, the data packet reaches the destination node, and otherwise cycle executes step 2 or 3, until data packet
Reach destination node.
The step 1 includes：
If the Hamilton path of existence anduniquess in the irregular three dimensional integrated circuits network-on-chip, described in selection only
One Hamilton path executes the Fault-tolerant Routing Algorithm based on Hamilton path；If the irregular three dimensional integrated circuits piece
There are a plurality of Hamilton paths in upper network, then arbitrarily select one in a plurality of Hamilton path, execution is based on
The Fault-tolerant Routing Algorithm in Hamilton path；If not finding Hamilton path in network, using based on the fault-tolerant of spanning tree
Routing algorithm route data packet.
By the node in the irregular three dimensional integrated circuits network-on-chip according on Hamilton path in the step 2
Sequence number consecutively.
Root node described in the step 3 meets：
1)KrOn L layers, whereinKrFor the root node, J is the horizontal device number of plies, and L is water
A certain layer horizontal device in flat device；
2) the of the irregular three dimensional integrated circuits network-on-chip is setThere is an I node on layer, in middle level
Present node p, 0≤p≤I-1 that number is p, if ΔpiMost for i-th of node in present node p and layer in addition to node p
Short leapfrog number, then KrIt is N that node p is removed in layer with the average most short leapfrog number of exterior noder, NrFor：
The step 3 further includes：
Be always into, be always to, first enter to go out again into these three transmission directions select transmission path complete
The transmission of data packet.Data packet carries out in the spanning tree for determine root node in transmission process, and data packet is made often to pass through a section
Point all apart from destination node more further.
Further include：If the next-hop node in the step 2 or the step 3 is not unique, according to DP-3D mechanism,
The flow sensing situation of each legal port of present node is obtained, the legal port output that flow is minimum is selected, reduces message and touch
The probability hit, avoids hot spot region.
The present invention also proposes a kind of route system towards irregular three dimensional integrated circuits network-on-chip, including：
Judgment module judges to use base for the topological structure according to the irregular three dimensional integrated circuits network-on-chip
Fault-tolerant Routing Algorithm in Hamilton path route data packet, or the Fault-tolerant Routing Algorithm based on spanning tree route data packet；
Hamilton routing algorithm module, for being route according to the Fault-tolerant Routing Algorithm based on the Hamilton path
Data packet uses the sequence according to node serial number monotone increasing or monotonic decreasing according to the location determination of source node and destination node
Router operating system is carried out, during the data packet is transmitted along the Hamilton path chosen, data packet is made often to pass through one
Node all apart from destination node more further；
Spanning tree algorithm module is then selected for routeing data packet according to the Fault-tolerant Routing Algorithm based on the spanning tree
Spanning-tree root node is selected, according to the position of root node and source node and destination node, transmission path is selected to complete the data
The transmission of packet；
Destination node module is reached, for when the data packet reaches node, checking address of node and the institute of arrival
Whether the address for stating destination node is identical, if identical, the data packet reaches the destination node, otherwise described in cycle execution
Hamilton routing algorithm module or the spanning tree algorithm module, until data packet reaches destination node.
The judgment module includes：
If the Hamilton path of existence anduniquess in the irregular three dimensional integrated circuits network-on-chip, described in selection only
One Hamilton path executes the Fault-tolerant Routing Algorithm based on Hamilton path；If the irregular three dimensional integrated circuits piece
There are a plurality of Hamilton paths in upper network, then arbitrarily select one in a plurality of Hamilton path, execution is based on
The Fault-tolerant Routing Algorithm in Hamilton path；If not finding Hamilton path in network, using based on the fault-tolerant of spanning tree
Routing algorithm route data packet.
The node in the irregular three dimensional integrated circuits network-on-chip is pressed in the Hamilton routing algorithm module
According to the sequence number consecutively on Hamilton path.
Root node described in the spanning tree algorithm module meets：
1)KrOn L layers, whereinKrFor the root node, J is the horizontal device number of plies, and L is water
A certain layer horizontal device in flat device；
2) the of the irregular three dimensional integrated circuits network-on-chip is setThere is an I node on layer, in middle level
Present node p, 0≤p≤I-1 that number is p, if ΔpiMost for i-th of node in present node p and layer in addition to node p
Short leapfrog number, then KrIt is N that node p is removed in layer with the average most short leapfrog number of exterior noder, NrFor：
The spanning tree algorithm module further includes：
Be always into, be always to, first enter to go out again into these three transmission directions select transmission path complete
The transmission of data packet.Data packet carries out in the spanning tree for determine root node in transmission process, and data packet is made often to pass through a section
Point all apart from destination node more further.
Further include：If the Hamilton routing algorithm module or the spanning tree algorithm mould next-hop node in the block
It is not unique, then according to DP-3D mechanism, the flow sensing situation of each legal port of present node is obtained, selects flow minimum
Legal port output, reduces the probability of message transition collision, avoids hot spot region.
As it can be seen from the above scheme the advantage of the invention is that：
First point, the present invention can improve the communication performance of three dimensional integrated circuits network-on-chip, packet on the basis of fault-tolerant
Including reduces average communication time delay and raising network throughput.This point is primarily due to be based on Hamilton path or spanning tree
Shortest-path first algorithm and expand to the port selection mechanism of three-dimensional scenic, can avoid hot spot region, reduce data packet
The probability clashed.The routing self-adaption degree of the present invention is higher, can be added according to the physical fault situation occurred of network-on-chip
To judge, the minimum legal output port of selection conflict；
Second point, the present invention can utilize the own characteristic of the two graphtheoretic concepts of Hamilton path or spanning tree,
The possibility for being formed in network-on-chip and being abstracted ring is eliminated, three-dimensional scenic can be avoided in the case of without using expensive VC technologies
Under communication deadlock occur.From the low overhead three dimensional integrated circuits network-on-chip in the angle of cost of implementation, the present invention
Fault-tolerant Routing Algorithm has stronger engineering technology meaning；
Thirdly, present invention can ensure that higher communication reliability.One important indicator of network reliability be exactly
In the given time, the quantity for the data packet that destination node can be routed to by source node, which occupies, is injected into network in this period
The ratio of middle data packet total quantity.If the ratio is higher, the reliability of corresponding route designing method is higher.The present invention can
So that data packet routes to destination node in the short time as far as possible, ensure the reliability of communication within the set time.
Description of the drawings
Fig. 1 is the schematic diagram of a typical 4*2*3 three-dimensional Mesh network-on-chip；
Fig. 2 is the schematic diagram of a typical irregular network on three-dimensional chip；
Fig. 3 is the Hamilton path schematic diagram in irregular network on three-dimensional chip；
Fig. 4 is the spanning tree schematic diagram in irregular network on three-dimensional chip；
Fig. 5 is the routing algorithm exemplary plot based on Hamilton path；
Fig. 6 is the routing algorithm exemplary plot based on spanning tree.
Specific implementation mode
First, the technical background of the present invention is briefly introduced, i.e., two graph theorys introduced in routing algorithm are general
Read --- Hamilton path and spanning tree.
Concept 1：Given figure G, if there are a paths, just primary by each vertex in figure, this paths then claims
For figure G a Hamilton path (Ebrahimi M, Daneshtalab M, Plosila J. " Fault-tolerant
routing algorithm for 3D NoC using hamiltonian path strategy,”in Proceedings
of Design,Automation&Test in Europe Conference&Exhibition.Los Alamitos:IEEE
Computer Society Press,2013,pp.1601-1604.)。
By concept 1 it is found that Hamilton path is a basic conception in graph theory, in the three-dimensional Mesh structures of rule
In, a plurality of Hamilton path is certainly existed, all nodes are arranged according to number ascending or descending order just past primary, such as figure
It is an irregular three-D network-on-chip shown in 3, wherein the path representation of all four-headed arrows composition is one of the network
Hamilton path, the advantage that data packet is route based on this paths are that can avoid the occurrence of data transmission is abstracted circuit, no
It needs to use high-cost Virtual Channel (VC) technology.
It should be noted that the characteristics of due to Hamilton path itself, the node serial number rule in Fig. 3 is different from Fig. 2,
It needs to be numbered in order according to path, Hamilton path is then not present in the irregular network in Fig. 2, this also illustrates not to be institute
All there is Hamilton path in the irregular network on three-dimensional chip having, meanwhile, each scramble network is also likely to be present not only
One Hamilton path (different Hamilton paths can make node serial number that respective change occur).
On the other hand, the essence of the routing algorithm based on Hamilton path is conditional " most short " routing algorithm, but
It is not necessarily strictly route along Hamilton path, before " strictly being transmitted by node serial number ascending or descending order "
It carries, then selects other non-Hamilton paths that can't also introduce data transmission and be abstracted circuit, it still can be to avoid deadlock, example
Such as, node 6 is source node, and node 10 is destination node, then the path selected is 6 → 7 → 10 rather than 6 → 7 → 8 → 9 → 10,
But, if permanent linkage fault occurs on shortest path, the other legal paths of selection are needed, for example, link 7-10
It breaks down, then the data packet at node 7 can select link 7-8, continue to compile according to node according to 7 → 8 → 9 → 10 sequence
The routing of number ascending order, it is this to operate the reliability for also improving routing algorithm.
Concept 2：Given figure G, if there are all vertex to be linked together by side, and there is no the trees in circuit, then
The tree is called a spanning tree (Matsutani H, Bogdan P, Marculescu R, et al. " the A case for of figure G
wireless 3D NoCs for CMPs,”in Proceedings of the 18th Asia and South Pacific
Design Automation Conference.Los Alamitos:IEEE Computer Society Press,2013,
pp.23-28.)。
Concept equally as a graph theory, spanning tree itself is without directionality, in order to retain side as much as possible to protect
Hinder the quantity of network communication path, what spanning tree routing algorithm needed to be introduced into transmission direction to eliminate in network abstract is transmitted back to
Road, here, present invention introduces two transmission directions：Enter to (In) and goes out to (Out), thus on the basis of not generating circuit,
Retain more sides (link) in spanning tree, improves the communication reliability of network.In and Out is relative to spanning-tree root section
For point, other seven directions with three-dimensional network, i.e., eastern (East), southern (South), western (West), northern (North), on
(Up), (Down) and local (Local) is different under, and abstract processing has been done in above seven directions by In and Out both directions, such as
Shown in Fig. 4 (by taking the network in Fig. 2 as an example), if selecting node 12 as the root node of spanning tree, solid arrow indicates just
It is the path that transmission direction is In, and the path that the transmission direction that dotted arrow indicates is Out.
After introducing two transmission directions of In and Out, data packet is by being likewise supplied with one-way feature, so as to avoid net
Network deadlock is directly route in this mode specifically, if destination node can be through by the directions In or the directions Out
；Otherwise, then according to the first directions In, the routing of the directions Out (does not allow to occur 180 ° in network to turn to avoid being abstracted again
Circuit), still it is also possible to prevent deadlock.For example, in network shown in Fig. 4, source node is node 2, and destination node is
Node 5, then 2 → 1 → 0 → 5 or 2 → 1 → 4 → 5 be all feasible transmission path；If source node location is constant, destination node
Change node 6 into, then path 2 → 1 → 8 → 11 → 12 → 13 → 6 or 2 → 1 → 0 → 5 → 12 → 13 → 6 be all optional road
Diameter, it should be noted that first not necessarily to pass through root node according still further to the directions Out routing data packet according to the directions In, than
Such as, source node is still node 2, and destination node is node 10, then the transmission path of data packet is 2 → 1 → 8 → 11 → 10, together
When, the permanent linkage fault in network can then influence specific path planning once occurring.If for example, link 1-4
It breaks down, then source node is node 2, and destination node, which is the transmission path of node 5, still has 2 → 1 → 0 → 5 may be selected.
It should be noted that if there are multiple spanning trees (having multiple root nodes) and each spanning trees in network simultaneously
To instruct the Route Selection of network, then the Virtual Channel of respective numbers is needed to support, therefore, the present invention pertains only to single spanning tree
Design of Routing Algorithm, root node determine after, the structure of the spanning tree of network also determines therewith.
The routing algorithm and spanning tree routing algorithm based on Hamilton path being described above, can not make
With avoiding network lock-up under the premise of Virtual Channel mechanism, while data packet is routed into destination node, here, the present invention provides vacation
If 1, the reliability for ensureing the enforceability of Fault-tolerant Routing Algorithm and communication in irregular network.
Assuming that 1：No matter permanent linkage fault occurs for any position in network, is all not in inaccessible node.
Both routing algorithm and spanning tree routing algorithm based on Hamilton path essence are different, have respective spy
Point, in contrast, the former is stringenter to the structural requirement of network than the latter, such as described above, is not that each is irregular
All there is Hamilton path in network on three-dimensional chip, further, since Hamilton path can directly be carried out according to node serial number
Dull ascending or descending order routing, therefore its maximum leapfrog number can be subtracted each other by the number of source node and destination node and obtain,
If leapfrog number is N, the number of source node is NS, the number of destination node is ND, then N≤| ND–NS|, and the road of spanning tree algorithm
Very high by the position selection degree of correlation of leapfrog number and spanning-tree root node, different root node position can extreme influence this network
Core index, therefore, spanning tree routing algorithm will be brought relative to the routing algorithm based on Hamilton path to system performance
Certain uncertainty, needing to design corresponding technical solution as far as possible keeps its performance stable and is promoted.
If the number of nodes of irregular network on three-dimensional chip is K (node serial number in network is 0~K-1), water in network
Flat device number of layers is J (in network each layer number according to bottom-up be 0~J-1).
Due to Hamilton path, once it is determined that, according to path order number, (present invention presses bottom-up device to node
Layer sequence uses 0~K-1 of ascending order number to node), mutual reachable path also determines that between the node in network, relative to
Spanning tree routing algorithm has higher stability, does not have the case where Hamilton path in irregular three-D network
Under, then spanning tree Fault-tolerant Routing Algorithm must be executed, the coding rule of node is relatively simple, i.e., need only from the 0th layer to J-1 layers
It is numbered by row sequence at every layer, only (the network node number in Fig. 2 can be can refer to) as node label.
The core of spanning tree Fault-tolerant Routing Algorithm is the choosing method of its root node position, the tool of the position described herein
The scale of constructionization chooses thinking, considers from fairness angle, and the leapfrog number needs of root node and each node are as small as possible, in this way can
The node of distal end is avoided to be counted to up to destination node by more leapfrog, therefore, if number is KrNode be the spanning tree of network
Root node, the present invention select KrIt needs to meet following two constraintss：
1)KrOn L layers, wherein
2) the of irregular network is setThere is I node on layer, it is p to be numbered in layer, and 0≤p≤I-1 be (number
Sphere of action is only limited to this layer, only for convenience of description, unrelated with network node number).If ΔpiFor present node p and this layer its
The most short leapfrog number of his node (having i-th in I-1 node altogether in addition to node p), then KrOther nodes in layer
Average most short leapfrog number is NrFor：
If meeting the of formula (1)Layer interior nodes are not unique, then arbitrary selection one wherein.
It should be noted that the data traffic on spanning-tree root node periphery is usually larger, regional temperature raising, and shadow are easily led to
The normal function for ringing physical unit executes.Present invention assumes that chip heat radiator (i.e. the 0th layer lower section) under the bottom of chip,
Therefore when the device number of plies of three-dimensional chip is even number, the present invention is theIn layer, Er FeiIt is selected in layer
Spanning-tree root node, in favor of the timely dissipation of chip entirety heat.
On the other hand, Dynamic Programming (dynamic programming, DP) selection mechanism (Mak T, Cheung P Y K,
Lam K P,et al.“Adaptive routing in network-on-chips using a dynamic-
programming network,”IEEE Transactions on Industrial Electronics,2011,58(8),
Pp.3701-3716.), it is low overhead, an efficient port selection mechanism towards conventional two-dimensional network, DP mechanism does not have
According to the traffic conditions of present node close region, but according in real time by the update of the path planning of source node to destination node
Situation selects optimal transmission path in the alternative.Since DP mechanism has been obtained for preferable reality in two-dimensional network
Effect is tested, the present invention expands the mechanism into three dimensions, is denoted as the ports DP-3D selection mechanism, to obtain higher communication
Performance, DP-3D mechanism are combined together with Fault-tolerant Routing Algorithm, just constitute complete adaptive reliable routing proposed by the present invention
Method.
The present invention the specific steps are：
Step 100：According to the structure decision of irregular network on three-dimensional chip, it whether there is Hamilton path；
Step 200：According to the judgement structure of step 100, next step operation is carried out.If there are Hamilton paths in network
And it is unique, then select the path to execute the Fault-tolerant Routing Algorithm based on Hamilton path；If there are Hamilton roads in network
Diameter and not unique, then need arbitrarily to select one in these paths, then execute the fault tolerance rout ing based on Hamilton path and calculate
Method；If Hamilton path is not present in network, data packet is route using the Fault-tolerant Routing Algorithm based on spanning tree；
Step 201：If network on three-dimensional chip route data packet using the Fault-tolerant Routing Algorithm based on Hamilton path, first
It is first using according to the monotone increasing of node serial number or the sequence of decline according to the location determination of source node S and destination node D
Fault tolerance rout ing is carried out, this sequence can not then be changed once selecting.Data packet is in a network along the Hamilton path transmission chosen
During, should ensure as far as possible data packet often pass through a node all apart from destination node more further；
Step 202：If network on three-dimensional chip route data packet using the Fault-tolerant Routing Algorithm based on spanning tree, should select first
Suitable spanning-tree root node R is selected out, further according to the position of root node R and source node S and destination node D, is being always
In is always that Out and elder generation In select being routed through for suitable transmission path completion data packet in these three transmission directions of Out again
Journey.Data packet should ensure that data packet often passes through a node as far as possible during being transmitted in the spanning tree for determining root node
All more further apart from destination node；
Step 300：If the optional next-hop node in step 201 or 202 is not unique, according to DP-3D mechanism, obtain
The flow sensing situation of each legal port of present node selects the legal port output that flow is minimum, reduces message transition collision
Probability avoids hot spot region；
Step 400：After data packet reaches next node, first comparison node address, if the node is destination node D,
Destination node is then reached, otherwise, according to the difference of network load, executes the content in step 201 or 202, Yi Jibu again
Relevant operation in rapid 300 obtains the position of next-hop node；
Step 500：The content in step 400 is repeated, until data packet reaches destination node D.
For example, it is still illustrated by taking the scramble network in Fig. 3 as an example.It will be apparent that existing not in the network
Only one Hamilton path, illustrates by taking path shown in Fig. 3 as an example.If source node is node 2, destination node is
Node 17, as shown in Figure 5.Due to linking 6-13 failures, " most short " path 2 → 3 → 4 → 5 → 6 → 13 → 14 can not be used
→ 17 are route, then use another " most short " path 2 → 3 → 8 → 9 → 10 → 11 → 16 → 17.This example using
Carry out dull ascending order routing by node serial number, and vice versa reason.
As shown in fig. 6, being to execute spanning tree Fault-tolerant Routing Algorithm when Hamilton path is not present in scramble network
Example.Due to the constraints for needing to meet according to spanning tree of network root node, only node 8 and node 11 is met the requirements,
Therefore node 12 cannot be re-used as the root node of the spanning tree of network.Here node 11 is set as root node.When link 11-12 occurs forever
When long property failure, path 2 → 1 → 8 → 16 → 15 → 17 and 2 → 1 → 8 → 7 → 15 → 17 still all can be used, due to data packet
It is not unique by output port legal when node 8, it needs to carry out real-time judge according to port selection mechanism DP-3D, it is assumed that most
After selected 2 → 1 → 8 → 7 → 15 → 17 as data transfer path, experienced respectively 2 directions In (link 1-2 and 1-8) and
The transmission in subsequent 3 directions Out (link 7-8,7-15 and 15-17).
The present invention also proposes a kind of route system towards irregular three dimensional integrated circuits network-on-chip, including：
Judgment module judges to use base for the topological structure according to the irregular three dimensional integrated circuits network-on-chip
Fault-tolerant Routing Algorithm in Hamilton path route data packet, or the Fault-tolerant Routing Algorithm based on spanning tree route data packet；
Hamilton routing algorithm module, for being route according to the Fault-tolerant Routing Algorithm based on the Hamilton path
Data packet uses the sequence according to node serial number monotone increasing or monotonic decreasing according to the location determination of source node and destination node
Router operating system is carried out, during the data packet is transmitted along the Hamilton path chosen, data packet is made often to pass through one
Node all apart from destination node more further；
Spanning tree algorithm module is then selected for routeing data packet according to the Fault-tolerant Routing Algorithm based on the spanning tree
Spanning-tree root node is selected, according to the position of root node and source node and destination node, transmission path is selected to complete the data
The transmission of packet；
Destination node module is reached, for when the data packet reaches node, checking address of node and the institute of arrival
Whether the address for stating destination node is identical, if identical, the data packet reaches the destination node, otherwise described in cycle execution
Hamilton routing algorithm module or the spanning tree algorithm module, until data packet reaches destination node.
The judgment module includes：
If the Hamilton path of existence anduniquess in the irregular three dimensional integrated circuits network-on-chip, described in selection only
One Hamilton path executes the Fault-tolerant Routing Algorithm based on Hamilton path；If the irregular three dimensional integrated circuits piece
There are a plurality of Hamilton paths in upper network, then arbitrarily select one in a plurality of Hamilton path, execution is based on
The Fault-tolerant Routing Algorithm in Hamilton path；If not finding Hamilton path in network, using based on the fault-tolerant of spanning tree
Routing algorithm route data packet.
The node in the irregular three dimensional integrated circuits network-on-chip is pressed in the Hamilton routing algorithm module
According to the sequence number consecutively on Hamilton path.
Root node described in the spanning tree algorithm module meets：
1)KrOn L layers, whereinKrFor the root node, J is the horizontal device number of plies, and L is water
A certain layer horizontal device in flat device；
2) the of the irregular three dimensional integrated circuits network-on-chip is setThere is an I node on layer, in middle level
Present node p, 0≤p≤I-1 that number is p, if ΔpiMost for i-th of node in present node p and layer in addition to node p
Short leapfrog number, then KrIt is N that node p is removed in layer with the average most short leapfrog number of exterior noder, NrFor：
The spanning tree algorithm module further includes：
Be always into, be always to, first enter to go out again into these three transmission directions select transmission path complete
The transmission of data packet.Data packet carries out in the spanning tree for determine root node in transmission process, and data packet is made often to pass through a section
Point all apart from destination node more further.
Further include：If the Hamilton routing algorithm module or the spanning tree algorithm mould next-hop node in the block
It is not unique, then according to DP-3D mechanism, the flow sensing situation of each legal port of present node is obtained, selects flow minimum
Legal port output, reduces the probability of message transition collision, avoids hot spot region.
Specific embodiments of the present invention are described and illustrated above, it is example that these embodiments, which should be considered it,
Property, it is not used to limit the invention, the present invention should be explained according to the attached claims.
Claims (10)
1. a kind of method for routing towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that including：
Step 1, according to the topological structure of the irregular three dimensional integrated circuits network-on-chip, judge using based on Hamilton road
The Fault-tolerant Routing Algorithm of diameter route data packet, or the Fault-tolerant Routing Algorithm based on spanning tree route data packet；
Step 2, it is route data packet according to the Fault-tolerant Routing Algorithm based on the Hamilton path, according to source node and purpose
The location determination of node is used carries out router operating system, the data packet according to the sequence of node serial number monotone increasing or monotonic decreasing
During the Hamilton path chosen is transmitted, data packet is made often to pass through a node all apart from destination node closer to one
Step；
Step 3, it is route data packet according to the Fault-tolerant Routing Algorithm based on the spanning tree, then selects spanning-tree root node, root
According to the position of root node and source node and destination node, transmission path is selected to complete the transmission of the data packet；
Step 4, when the data packet reaches node, check the address of node of arrival and the destination node address whether
Identical, if identical, the data packet reaches the destination node, and otherwise cycle executes step 2 or 3, until data packet reaches
Destination node；
The wherein described step 1 includes：
If the Hamilton path of existence anduniquess in the irregular three dimensional integrated circuits network-on-chip, select described unique
Hamilton path executes the Fault-tolerant Routing Algorithm based on Hamilton path；If the irregular three dimensional integrated circuits piece online
There are a plurality of Hamilton paths in network, then one is arbitrarily selected in a plurality of Hamilton path, execute close based on the Chinese
The Fault-tolerant Routing Algorithm in your path；If not finding Hamilton path in network, the fault tolerance rout ing based on spanning tree is used
Algorithm route data packet.
2. the method for routing as described in claim 1 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that institute
It states the node in the irregular three dimensional integrated circuits network-on-chip in step 2 according to the sequence on Hamilton path successively
Number.
3. the method for routing as described in claim 1 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that institute
State the satisfaction of root node described in step 3：
1)KrOn L layers, whereinKrFor the root node, J is the horizontal device number of plies, and L is horizon equipment
A certain layer horizontal device in part；
2) the of the irregular three dimensional integrated circuits network-on-chip is setThere is I node on layer, is numbered in middle level
For present node p, 0≤p≤I-1 of p, if ΔpiFor the most short jump of i-th of node in present node p and layer in addition to node p
Step number, then KrIt is N that node p is removed in layer with the average most short leapfrog number of exterior noder, NrFor：
4. the method for routing as described in claim 1 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that institute
Stating step 3 further includes：
Be always into, be always to, first enter to go out again into these three transmission directions select transmission path complete data
The transmission of packet, data packet carry out in the spanning tree for determine root node in transmission process, and data packet is made often to pass through a node all
More further apart from destination node.
5. the method for routing as described in claim 1 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that also
Including：If the next-hop node in the step 2 or the step 3 is not unique, according to DP-3D mechanism, prosthomere is worked as in acquisition
The flow sensing situation of each legal port of point selects the legal port output that flow is minimum, reduces the probability of message transition collision, keep away
Open hot spot region；
Wherein Dynamic Programming selection mechanism is expanded into three dimensions, is denoted as the DP-3D mechanism.
6. a kind of route system towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that including：
Judgment module judges for the topological structure according to the irregular three dimensional integrated circuits network-on-chip using based on the Chinese
The Fault-tolerant Routing Algorithm in Milton path route data packet, or the Fault-tolerant Routing Algorithm based on spanning tree route data packet；
Hamilton routing algorithm module, for routeing data according to the Fault-tolerant Routing Algorithm based on the Hamilton path
Packet is used according to the location determination of source node and destination node and is carried out according to the sequence of node serial number monotone increasing or monotonic decreasing
Router operating system during the data packet is transmitted along the Hamilton path chosen, makes data packet often pass through a node
All more further apart from destination node；
Spanning tree algorithm module then selects to give birth to for routeing data packet according to the Fault-tolerant Routing Algorithm based on the spanning tree
Transmission path is selected to complete the data packet according to the position of root node and source node and destination node at root vertex
Transmission；
Destination node module is reached, for when the data packet reaches node, checking the address of node of arrival and the mesh
Address of node it is whether identical, if identical, the data packet reaches the destination node, and otherwise it is close to execute the Chinese for cycle
That routing algorithm module or the spanning tree algorithm module, until data packet reaches destination node；
The wherein described judgment module includes：
If the Hamilton path of existence anduniquess in the irregular three dimensional integrated circuits network-on-chip, select described unique
Hamilton path executes the Fault-tolerant Routing Algorithm based on Hamilton path；If the irregular three dimensional integrated circuits piece online
There are a plurality of Hamilton paths in network, then one is arbitrarily selected in a plurality of Hamilton path, execute close based on the Chinese
The Fault-tolerant Routing Algorithm in your path；If not finding Hamilton path in network, the fault tolerance rout ing based on spanning tree is used
Algorithm route data packet.
7. the route system as claimed in claim 6 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that institute
It states the node in the irregular three dimensional integrated circuits network-on-chip in Hamilton routing algorithm module according to Hamilton
Sequence number consecutively on path.
8. the route system as claimed in claim 6 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that institute
State the satisfaction of root node described in spanning tree algorithm module：
1)KrOn L layers, whereinKrFor the root node, J is the horizontal device number of plies, and L is horizon equipment
A certain layer horizontal device in part；
2) the of the irregular three dimensional integrated circuits network-on-chip is setThere is I node on layer, is numbered in middle level
For present node p, 0≤p≤I-1 of p, if ΔpiFor the most short jump of i-th of node in present node p and layer in addition to node p
Step number, then KrIt is N that node p is removed in layer with the average most short leapfrog number of exterior noder, NrFor：
9. the route system as claimed in claim 6 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that institute
Stating spanning tree algorithm module further includes：
Be always into, be always to, first enter to go out again into these three transmission directions select transmission path complete data
The transmission of packet, data packet carry out in the spanning tree for determine root node in transmission process, and data packet is made often to pass through a node all
More further apart from destination node.
10. the route system as claimed in claim 6 towards irregular three dimensional integrated circuits network-on-chip, which is characterized in that
Further include：If the Hamilton routing algorithm module or the spanning tree algorithm mould next-hop node in the block be not unique,
Then according to DP-3D mechanism, the flow sensing situation of each legal port of present node, the legal port for selecting flow minimum are obtained
Output, reduces the probability of message transition collision, avoids hot spot region；
Wherein Dynamic Programming selection mechanism is expanded into three dimensions, is denoted as the DP-3D mechanism.
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Application publication date: 20160511 Assignee: Zhongke Jianxin (Beijing) Technology Co.,Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: X2022990000752 Denomination of invention: A Routing Method and System for Irregular 3D Integrated Circuit Network on Chip Granted publication date: 20180810 License type: Exclusive License Record date: 20221009 |