CN103970939A - Layering and reconfigurable on-chip network modeling and simulation system - Google Patents

Abstract

The invention discloses a layered and reconfigurable on-chip network modeling and simulation system. The system includes three layers: a test layer, a main body layer and an operation layer. The core of the test layer is the reconfigurable routing unit and the network interface unit, which can dynamically change the network structure parameters; the main layer uses the resource node as the main component unit, provides a common OCP interface to connect with the routing unit through the network interface unit, and integrates traffic generation Mechanism, receiving mechanism and performance analysis logic unit; the operation layer provides a good human interaction interface with a software configuration module, which is used for flexible configuration and structure generation of on-chip network structure characteristic parameters and communication modes. The present invention can model on-chip network architectures using different topological structures, network scales, routing algorithms, buffer depths, etc., and perform network performance simulations under different communication modes and communication loads, providing an on-chip network architecture under different application requirements design basis.

Description

A Hierarchical Reconfigurable Network-on-Chip Modeling and Simulation System

technical field

The invention belongs to the technical field of network-on-chip systems, and in particular relates to a hierarchical and reconfigurable network-on-chip modeling and simulation system.

Background technique

With the rapid development of integrated circuits and semiconductor process technologies, the scale of SoCs is getting larger and larger. Network-on-Chip (NoC), as a new method to solve the global communication problem in large-scale system-on-chip, can significantly improve the performance of the system, and is considered to be an inevitable direction for the development of multi-core technology in system-on-chip in the future. NoC design includes topology selection, routing algorithm determination, and basic component design. Different design schemes in each link have huge differences in performance. Therefore, it is particularly important to build a general reconfigurable network-on-chip system modeling and simulation system. important.

Existing NoC simulation platforms can be divided into two categories. One is designed in a high-level language, which can quickly model and analyze NoC performance. However, due to the high level of abstraction, the impact of the physical layer on performance is ignored, which will cause evaluation problems. The result deviates greatly from the actual situation; the other is to directly use the hardware description language to simulate the NoC system, but this method has poor flexibility and slow simulation speed, and cannot accurately and detailedly design the details of the network on chip (such as topology, flow rate, etc. model, etc.) for research. Moreover, although the above-mentioned network-on-chip performance evaluation models or simulators have their own characteristics, they all lack the ability to dynamically configure the test environment.

Contents of the invention

The purpose of the present invention is to provide a layered and reconfigurable on-chip network modeling and simulation system aiming at the deficiencies of the current on-chip network simulation system. The system supports on-chip network architecture parameters such as different topologies, network scales, routing algorithms, and buffer depths, as well as flexible and dynamic configuration of various communication traffic modes, so as to realize various on-chip network architectures under different communication modes and communication loads. Rapid modeling and performance simulation.

Realize the technical scheme of the present invention as follows:

A hierarchical reconfigurable network-on-chip modeling and simulation system is characterized in that the system includes the following layers:

a) The test layer is composed of a reconfigurable routing unit and a network interface unit, which can dynamically change the characteristic parameters of the on-chip network structure to support various on-chip network structures;

b) The main layer is composed of resource nodes with OCP interfaces, which are connected to routing units through OCP interfaces. The resource nodes integrate traffic generation, reception and performance analysis modules to support multiple communication modes and communication loads, as well as communication data statistics analyze;

c) The operation layer, which is composed of software configuration modules, provides a good human-computer interaction interface for flexible configuration of on-chip network structure characteristic parameters and communication modes and on-chip network structure generation.

Compared with the prior art, the present invention has the following technical effects:

The present invention aims at the advantages and disadvantages of separately designing the simulation platform using high-level language and hardware description language, and constructs a hierarchical NoC simulation platform, including an operation layer composed of software configuration modules designed in high-level language, and an on-chip network communication designed in hardware description language The test layer and the main layer composed of nodes and resource nodes. Among them, the network-on-chip communication nodes and resource nodes are reconfigurable, and can dynamically configure the simulated NoC system structure and communication modes. The present invention further applies the open core protocol OCP to the NoC simulation system, designs a NoC resource node with an OCP interface, and communicates with the NoC routing unit through the OCP protocol to improve the versatility of the model, and integrates the flow generation mechanism, receiving The mechanism and performance analysis logic unit are integrated in the resource node, which makes the evaluation model simple in hierarchy, clear in structure, and flexible in configuration. The present invention can realize rapid modeling and performance simulation of different architecture on-chip networks under different communication modes and communication loads, perform accurate and comprehensive performance evaluation on NoC architectures designed based on various parameters, and provide specific application-oriented NoC design options Optimal interconnection architecture provides the basis.

Description of drawings

Figure 1 is a structural diagram of a hierarchical reconfigurable network-on-chip simulation system;

Fig. 2 is a structural diagram of a reconfigurable routing unit;

Fig. 3 is a structural diagram of the routing unit input module;

Figure 4 is a code structure diagram of the configurable input port generated by the loop control method;

Figure 5 is a structural diagram of the routing calculation module of the routing unit;

Figure 6 is a structural diagram of the routing unit arbitration module;

Fig. 7 is a reconfigurable structural diagram of the data exchange switch module in the routing unit;

Fig. 8 is a structural diagram of a routing unit output module;

Fig. 9 is a network interface structural diagram;

Fig. 10 is the OCP protocol fixed packet format;

Figure 11 is the data microchip format;

Figure 12 is a resource node structure diagram;

Fig. 13 is a structural diagram of a traffic generation module in a resource node;

Fig. 14 is a structural diagram of the traffic reception and performance analysis module in the resource node;

Fig. 15 is a network communication structure diagram based on the OCP interface;

Figure 16 is a flow chart of building a NoC model based on the operating layer software.

Detailed ways

Hereinafter, the present invention will be described in detail through specific embodiments in conjunction with the accompanying drawings.

The hierarchical and reconfigurable network-on-chip simulation system of the present invention includes three layers: an operation layer, a main body layer and a test layer, and is used for modeling key characteristics of the network-on-chip and statistically analyzing performance indicators. Its structure is shown in FIG. 1 . The functional composition and relationship of each layer are described as follows.

(1) The operation layer, which is directly oriented to the users of the simulation platform. Users interact with the simulation model through the software configuration module, set the network topology, network scale, routing algorithm, etc. The distribution model, data packet length, network injection rate, microchip size, etc. are convenient for testing various performance indicators of the on-chip network under different communication modes and communication loads. The performance results of the test are also displayed through the software configuration module.

(2) The main layer, which is composed of resource nodes S with OCP interface, which is used to simulate various functional IP cores in the network-on-chip system (such as dedicated hardware resources, embedded microprocessors, custom reconfigurable hardware or It is a combination of the above-mentioned various resources) communication tasks, including generating corresponding communication traffic into the network according to the configured space and time distribution, and performing performance analysis and calculating various performance indicators according to the communication status of the network. In addition, users can configure the number of resource nodes S according to the scale of the network. As shown in Figure 1, the performance evaluation of a 4×4 2D Mesh structure NoC is performed, and 16 resource nodes are allocated corresponding to the routing unit. When it is only necessary to test the communication of several pairs of nodes on a fixed path, only the resource nodes that need to send and receive data can be configured, which effectively controls the scale of the main layer.

(3) The test layer, where the on-chip network instance for testing is placed, and its core components are the reconfigurable routing unit R and the network interface unit NI. Reconstruct the routing unit according to the user's configuration information at the operation layer, and form a NoC instance with specified structural characteristic parameters (including topology, switching strategy, routing strategy, buffer size, port number, etc.) at the test layer. The NoC used in Figure 1 is a 4×4 2D Mesh network, each routing unit R communicates with adjacent routing units, and communicates with resource nodes through network interface units.

As mentioned above, the three levels of the above-mentioned simulation system are composed of core parts such as software configuration module, resource node with OCP interface, reconfigurable routing unit and network interface unit. Therefore, the key issue involved in the present invention is the design of these core components, and the specific structure and design method of the core components will be described in detail below.

The routing unit is the core of on-chip network communication. It is mainly responsible for receiving and storing data, and forwarding it to the next routing unit or resource node according to a specific routing algorithm protocol. The smallest unit for transmitting information is a microchip, which contains control information and load data. The control information is mainly used to identify the microchip type and indicate the status of the microchip; the payload data is the data content transmitted by the microchip. In order to improve the transmission efficiency, the present invention designs a dual-channel reconfigurable routing unit, which separates the transmission of the control signal from the load data. Its structural block diagram is shown in Figure 2. Composed of exchange switch module and output module. The function and structure of each part are as follows:

(1) Input module

The module analyzes the received microchip data, separates the control signal and load data, and stores them in the corresponding data buffer according to the specified routing algorithm protocol, and transmits the send request signal to the arbitration module. Its structure is shown in Figure 3, including an input port module, a routing calculation module and a data cache module.

The input module receives the chip sent by the upper-level routing unit, and through the analysis of the input port, separates the control signal ctr_in from the load data Data_in, and sends them to the corresponding data buffer module respectively. By obtaining the microchip type control bit in ctrl_in, the microchip type is judged. If it is the header microchip, the load data is sent to the routing calculation module for routing, and the routing result is sent to the cache controller. When the data cache module receives microchip data, it will trigger the cache controller to initiate a request command to the arbitration module. After receiving the sending permission signal from the arbitration module, the cache controller controls the data FIFO and the control signal, and the data cache module sends the data packet to the corresponding switch module.

For different NoC topologies, the number of input and output ports of the routing unit and the number of resource nodes connected to it are not the same. Therefore, the present invention generates an interface circuit with a configurable number of ports in a cyclic control manner. Taking the generation of 8 ports as an example, the code structure is shown in Figure 4. The parameter num_ports is defined as 8 in the code, and the for loop statement is used to instantiate the input module input_module 8 times.

In addition, in the input module, the routing calculation module receives the routing information in the header chip, routes the routing information according to a certain routing mechanism, and obtains the forwarding direction of the data packet. In order to reflect reconfigurability, the routing mechanism can be configured according to the network topology. The routing calculation module structure is shown in Figure 5, including a variety of routing algorithm sub-modules and customizable routing algorithm sub-modules.

Configure various parameters in the routing calculation interface module, such as the routing algorithm type control parameter router_type, the routing information bit width parameter router_info_width, the output result bit width parameter router_out_width, etc., select the sub-module of the specified routing algorithm, and realize the routing method of the algorithm. To implement the XY routing algorithm, you only need to configure the type parameter as ROUTING_TYPE_XY, configure the routing information bit width as 8bit, configure the output result bit width as 5bit, and select the XY routing algorithm submodule. If the routing algorithm used by the simulated network topology is not implemented in the existing routing algorithm sub-module library, the configuration type parameter is ROUTING_TYPE_DEFAULT and other corresponding parameter values, and a custom route can be added through the scalable custom routing algorithm interface The algorithm sub-module is transferred to the code project of the routing calculation module to realize the expansion of the routing algorithm.

The output result of the routing algorithm is the port number, and for different network topologies, the port numbers of the routing unit are also different. For example, the port numbers 0~3 of the routing unit in the grid network indicate the ports in the four directions of east, west, north, south, respectively, and the fourth port indicates the local connection port. The routing unit ports 0~3 of the tree network are distributed under the routing unit, responsible for To connect child nodes, ports 4~7 are distributed on the routing unit and are responsible for connecting to the parent node. When systems with different topologies are connected to routing units, they need to be connected according to the port numbers.

(2) Arbitration module

After receiving the request signal sent by each input module, the module makes a corresponding response according to the arbitration agreement, and controls the exchange switch module to exchange data. Its reconfigurability is mainly reflected in the selectivity of the arbitration algorithm and the variability of the number of sending requests. In order to improve the transmission efficiency, the present invention adopts the virtual channel technology in the routing unit. Therefore, the forwarding request sent by each port also needs to have a virtual channel arbitration function. The arbitration module is divided into two stages for data arbitration and distribution, divided into output Port application and output virtual channel application. The circuit structure of the module is shown in Figure 6.

In the figure, p0 is the number of routing unit ports, and v is the number of virtual channels in each port. The first stage applies to the output port for a virtual channel for forwarding data, requiring p0 arbitrators of v:1. The second stage is an arbiter of pi:1 for each output port, responding to port output requests. The input signal bit width parameter arbiter_width of the arbitration module changes with the position of the arbiter instance. In the first level of arbitration, the arbiter_width bit width is num_vcs, that is, the number of virtual channels, and in the second level of arbitration, it is num_ports, that is, the number of ports. Similar to the routing algorithm module, the reconstruction of the arbitration module is mainly to realize the selection of different arbitration algorithms. The selection of the arbitration algorithm is to select and instantiate different arbitration algorithms through the case statement. When using a custom arbitration algorithm, the secondary development of the custom arbitration algorithm module that defines the input and output signals is sufficient.

(3) Exchange switch module

The module is divided into a load data exchange module and a control signal exchange module, which is controlled by the arbitration module to realize the physical transmission of data from the input module to the output module. Taking the data exchange switch module as an example, its circuit structure diagram is shown in Figure 7.

The input signal of the module is composed of the data signal line data_in_ip and the cross port control signal ctrl_in_op_ip. The bit width of the data signal line is num_ports*data_width, and the total bit width is proportional to the number of routing unit ports to realize reconfiguration configuration. The control signal line is num_ports*num_ports, and the connection status of the distribution control input port and output port. switch_type is the control parameter of the switching array connection type, which is divided into three types: CROSSBAR_TYPE_TRISTATATE, CROSSBAR_TYPE_MUX, and CROSSBAR_TYPE_DIST_MUX, which respectively realize the switching connection modes of three-state matrix switch, full connection matrix and partial connection matrix.

(4) Output module

The module receives load data and control signals, controls the multiplexer according to the arbitration result, selects the corresponding port data for output, and outputs to the next routing unit or destination resource node. The circuit structure diagram of this module is shown in Figure 8. It is mainly composed of a multiplexer and an output controller, and the number of ports can be reconfigured in the same way as the input module.

Another core component of the test layer is the reconfigurable network interface unit NI, which is responsible for realizing the data connection between resource nodes and routing units. The data in the resource nodes is transmitted to the network interface unit NI in a fixed data packet format, and the network interface unit NI needs to repackage the data packets according to different network topologies to adapt to different topological structures. The structure diagram of the reconfigurable network interface unit is shown in Figure 9, which includes four modules: interface with resource nodes, data packetization and unpacking, input control and output control, and data cache. The function and structure of each part are as follows:

(1) Interface module with resource nodes: use OCP protocol to communicate with resource nodes in the NoC system to improve versatility;

(2) Data grouping and unpacking module: The data grouping module converts fixed-format data packets into data flakes suitable for transmission on the current on-chip network structure. It is a key module for reconfiguration in the network interface unit. , bit width, etc. all change with the change of the reconstruction parameters; unpacking is the reverse process of packeting, and the data unpacking module converts the data flake format transmitted from the network on chip into a data packet format that conforms to the OCP protocol communication.

(3) Input control and output control module: realize the scheduling of data microchip transmission, and allocate data transmission between resource nodes and routing units;

(4) Data cache module: store data packets in the form of microchips, and its depth is configurable.

Wherein, the defined OCP protocol fixed data packet format is shown in FIG. 10 . Route_trans_cnt is used to count the number of routing hops of data packets in network transmission. Every time a data packet passes through a routing unit, the flag bit count is increased by 1, which is used for statistical analysis of link hops; Packet_length is the length of the data packet, used to calculate the The data packet is divided into the number of microchips; Source_ID is the source address of the data packet, which is the coded address of the resource node; Destination_ID is the destination address of the data packet, which is also the coded address of the resource node; Reserved is a reserved word; Time_cnt is the recorded data The time delay from data sending to data receiving of packets is used to statistically analyze the delay performance of network topology transmission.

The reconfigurable network interface unit provided by the present invention has the function of converting fixed-format data packets into data flakes under reconstruction characteristics, and the composition and bit width of the data flakes are all changed with the change of reconfiguration parameters. According to the analysis of the data packet format, the data flake can be defined as the format shown in FIG. 11 . In Figure 11, the Ctrl part is the microchip control signal, which includes the effective signal flag V of the microchip, the virtual channel number VC where the microchip is located, the microchip type flag H (header, Header) and T (tail microchip, Tail ), and Data is the part of the data flake. In the head and tail flakes, Data contains the routing information Router_info, the flake length L, and the reserved word R. In different network topologies, data flakes with different bit widths can be realized by configuring the bit width parameters of these signals. For example, if a network on chip with a 4×4 2D Mesh structure is defined, the number of virtual channels is 4, and the maximum data packet length is 127, then the bit width of the control signal of the data chip is 5, and the bit width of the data signal is at least 11 bits ( The two-dimensional address width of the routing information is 4, and the data packet flake length bit width is 7).

The core component of the main layer is the resource node with OCP interface. The resource node adopts a modular design method to encapsulate the on-chip network traffic generation, receiving module, performance analysis module and interface module. The internal structure is shown in Figure 12. Each module can be individually modified during design. If a traffic distribution model needs to be added, only the traffic generation module needs to be modified accordingly, without affecting other modules, which facilitates the upgrade of the simulation platform. Using resource nodes to simulate the communication of the IP core of the network on chip makes the platform configuration more flexible. The flexibility is mainly reflected in the following two aspects: on the one hand, resource nodes can be configured according to the number of nodes that need to communicate, and for those that do not need to send data The nodes that receive and receive data do not configure resource nodes, which can reduce the scale of the main layer of the platform; on the other hand, for some communication nodes that only send data or only receive data, it is also possible to configure only traffic generation in resource nodes as needed module or flow receiving module, further saving on-chip resources. The function and structure of each module of the resource node are introduced in detail below.

(1) Traffic generation module

Traffic generation is the source of the entire performance evaluation work. The structure of the traffic generation module in the present invention is shown in Figure 13, including a random module, a Time interval module, an Addr_gen module and an Inject module.

The random module is used to generate random numbers satisfying the uniform distribution between 0 and 1 for use by the time distribution control module and the space distribution control module.

The time distribution control module Time interval is used to control the occurrence interval of network traffic in the time dimension. It integrates the operation logic of various traffic distribution models for selection during testing. The random numbers used in the time intervals of various time distributions supported in the platform (such as Poisson distribution, self-similar distribution, fixed time interval) are provided by the random module, and other parameters can be configured. When the clock cycle counter reaches the calculated time interval, the Time interval module sets the output signal WR_en to high level, notifies the Inject module to inject data into the network, and WR_en is automatically set to low level in the next clock cycle. For the ON-OFF model that needs to continuously send data, WR_en is always kept high during the burst period, and WR_en is always kept low during the idle period.

The spatial distribution control module Addr_gen is responsible for determining the communication relationship of network traffic in the spatial dimension. According to the user's configuration, the operational logic of various spatial distribution models integrated in the Addr_gen module calculates the target address that meets the specified distribution results as the current node communication, and the platform The spatial distributions supported in include uniform distribution, descending probability distribution, and fixed transmission path distribution. When traffic injection occurs each time, the Inject module uses the address number generated by the Addr_gen module as the target address of this communication. After the communication is completed, the Addr_gen module immediately updates the address number through calculation to provide a target address that satisfies the specified distribution for the next communication.

The Inject module reads the configuration file transmitted from the operation layer, selects the traffic distribution model that should be generated by the Time interval module and the Addr_gen module according to the configuration information, and sets various parameters of the specified distribution. The Inject module generates the data packet to be sent according to the microchip length specified by the user, takes the address subject to the specific distribution generated by the Addr_gen module as the communication target, and transmits the data and address to the network interface unit module at the same time when the signal WR_en is at a high level.

(2) Traffic reception and performance analysis module

The traffic reception and performance analysis module in the resource node includes a Receiver module and an Access module, and its structure is shown in Figure 14.

The Receiver module is a test data receiving module for storing data from the on-chip network. Every time a data packet is received, the arrival time of the data packet is recorded, and the parameter information such as the sending time of the data packet, the length of the data packet and the number of link hops in the data packet header chip are counted, and then these parameters are passed to the performance analysis The module Access performs analysis and processing.

According to the information that needs to be counted during the calculation of network performance indicators (including average delay, throughput, link utilization, etc.), combined with the necessary information during data transmission, the format of the data packet header of the test traffic can be determined, and the data microchips in the platform The length is 32 bits, and the header chip format is as follows.

data bit 31-27 26-22 21-17 16-12 11-0 data content routing hops packet length target address source address sending time

The data in the header microchip is written into the header microchip by the traffic generation module of the platform when the data is generated. The sending time is used to record the time when the data packet is transmitted to the on-chip network, and is used together with the data packet receiving time recorded by the Receiver module. It is used to calculate the average delay index of the network; the source address and destination address information provide the basis for the routing unit to calculate the transmission path; the data packet length information can provide important parameters for the calculation of network throughput and link utilization; the routing hop count records the data The number of links experienced during packet transmission is used to calculate link utilization and network power consumption. Its initial value is 0, and it will be incremented every time it is routed and forwarded. In the data information of the header chip, there is only The value of routing hops can be modified.

The Access module is a performance index calculation module, which integrates the algorithmic logic of various performance index formulas. In addition, the Access module also includes a global clock counter, which is used to calculate the running time of the platform. Combined with the statistics of the Receiver module and the network power consumption parameters from the operation layer, it provides the algorithm module with the necessary information for the calculation of performance indicators. Various parameters are required, and the final calculation results are summarized through the main layer and wait for the reading of the manipulation layer.

(3) OCP interface module

This module is responsible for realizing the communication between the resource node and the on-chip communication network, including two parts: the host interface and the slave interface. The host interface is connected to the traffic generation module, and sends commands and data to the routing unit in the adjacent on-chip communication network, and receives the feedback signal from the routing unit; the slave interface is connected to the traffic receiving performance analysis module, and receives according to the OCP sequence The data sent by the routing unit is transmitted to the performance analysis module for storage, and a feedback signal is sent to the data sender at the same time. The communication structure of the on-chip network based on the OCP interface is shown in Figure 15.

The constituent unit of the operation layer is the software configuration module. This module provides a good human interaction interface, and displays the extracted network characteristic parameters on the software interface for users to select and configure to generate various NoC models for simulation evaluation; according to the configured communication traffic pattern parameters, call the main layer The basic components of the test layer (resource node module), according to the configured topology, routing algorithm, number of virtual channels, buffer depth and other parameters, call the basic components of the test layer (reconfigurable routing unit and network interface unit), and expandable Custom modules (custom routing algorithm, arbitration algorithm, etc.) to complete the NoC system structure; input the generated NoC project files (including system structure code and simulation test data TestBench) to EDA simulation tools (such as Modelsim ), statistics of NoC network node sending and receiving data, delay and other performance data, and save the data in a text file; finally read the statistical data fed back by the EDA tool, analyze the data, and generate a network performance evaluation report. According to the above functional description, the software configuration module in the present invention is further divided into five modules of network topology configuration, routing unit configuration, network interface unit configuration, traffic parameter configuration and EDA simulation data analysis, and the functions of each part are as follows respectively, The process of building NoC simulation model based on this is shown in Figure 16.

(1) Network topology configuration module: mainly implements the configuration of topology parameters (topology structure, network scale, resource nodes, etc.), and establishes network node connections according to the configuration parameters to form a NoC network object, and performs network diameter, average Calculation of performance parameters such as distance and shortest path of network node routing;

(2) Routing unit structure configuration module: Combined with the configured topology parameters, further configure the routing unit structure parameters. Configurable parameters include routing algorithm type parameters, number of virtual channels, buffer depth, microchip bit width, switching mode type parameters, arbitration type parameters, congestion control type parameters, etc.

(3) Network interface configuration module: configure and realize the connection relationship between network nodes and resource nodes; configure network interface unit related parameters according to network topology parameters and routing unit structure parameters, so as to convert fixed-format data packets to adapt to the current topology structure A data chip format for network systems.

(4) Traffic parameter configuration module: configure the parameters of spatial distribution and time distribution generated by traffic, data packet length, number of resource nodes, etc., and generate EDA simulation test platform data and TestBench, etc.

(5) EDA simulation data analysis: analyze NoC performance parameter data collected by EDA simulation tools, and generate NoC performance evaluation reports, etc.

By applying the above method, a hierarchical reconfigurable network-on-chip modeling and simulation system can be constructed to realize correct and fast modeling of network-on-chip architectures with different topological structures, network scales, routing algorithms, buffer depths, etc. Perform network performance simulation under different communication modes and communication loads, evaluate the impact of various structural characteristic parameters on network performance, and provide an important basis for on-chip network architecture design under different application requirements.

Claims (5)

1. A hierarchical reconfigurable network-on-chip modeling and simulation system, characterized in that: the system comprises the following layers: a) The test layer is composed of a reconfigurable routing unit and a network interface unit, which can dynamically change the characteristic parameters of the on-chip network structure to support various on-chip network structures; b) The main layer is composed of resource nodes with OCP interfaces, which are connected to routing units through OCP interfaces. The resource nodes integrate traffic generation, reception and performance analysis modules to support multiple communication modes and communication loads, as well as communication data statistics analyze; c) The operation layer, which is composed of software configuration modules, provides a good human-computer interaction interface for flexible configuration of on-chip network structure characteristic parameters and communication modes and on-chip network structure generation. 2. The hierarchical reconfigurable network-on-chip modeling and simulation system according to claim 1, wherein the routing unit comprises the following parts: a1) Input module: It includes an interface circuit with a configurable number of input ports generated by loop control, independent and scalable routing algorithm sub-modules, and a variable-depth data buffer module; used to store the received microchip data Analyze, separate the control signal and load data, and store them in the corresponding data buffer according to the specified routing algorithm protocol, and transmit the sending request signal to the arbitration module; a2) Arbitration module: includes configurable input request port and arbitration algorithm module; it is used to respond to the request signal sent by each input module according to the arbitration protocol, and control the exchange switch module to perform data exchange; a3) Exchange switch module: including multiple exchange connection methods; used to realize the physical transmission of data from the input module to the output module; a4) The output module is composed of a multiplexer and an output controller. The number of output ports can be reconfigured to receive load data and control signals, control the multiplexer according to the arbitration result, and select the corresponding port data for output . 3. The hierarchical reconfigurable network-on-chip modeling and simulation system according to claim 1, characterized in that: the network interface unit is responsible for realizing the data connection between the resource node and the routing unit, including the following parts: 1) Interface module with resource nodes: use OCP protocol to communicate with resource nodes in the network-on-chip system to improve versatility; 2) Data grouping and unpacking module: The data grouping module converts fixed-format data packets into data flakes suitable for transmission on the current on-chip network structure. It is a key module for realizing reconstruction in the network interface unit. The composition of data flakes, The bit width changes with the change of the reconstruction parameters; unpacking is the reverse process of grouping, and the data unpacking module converts the data flake format transmitted from the on-chip network into a data packet format that conforms to the OCP protocol communication; 3) Input control and output control module: realize the scheduling of data microchip transmission, and allocate data transmission between resource nodes and routing units; 4) Data cache module: store data packets in the form of microchips, and its depth is configurable. 4. The hierarchical reconfigurable network-on-chip modeling and simulation system according to claim 1, wherein the resource node comprises the following parts: b1) Traffic generation module: generate test traffic conforming to a certain spatial distribution and time distribution; b2) Traffic reception and performance analysis module: receive and store data from the on-chip network, record the arrival time of the data packet, count the data packet parameter information in the data packet header microchip, and calculate the network performance index through the corresponding formula; b3) OCP interface module: responsible for realizing the communication between the resource node and the on-chip network, including two parts: the host interface and the slave interface. The host interface is connected to the traffic generation module, and sends commands and data to the adjacent on-chip network. The routing unit receives the feedback signal from the routing unit; the slave interface is connected to the traffic receiving and performance analysis module, receives the data sent by the routing unit according to the OCP sequence, and transmits the data to the performance analysis module for storage, and sends a feedback signal to the data at the same time sender. 5. The hierarchical reconfigurable network-on-chip modeling and simulation system according to claim 1, characterized in that: the software configuration module includes the following parts: c1) Network topology configuration module: realize the configuration of network topology parameters, establish network node connections according to the configuration parameters, form an on-chip network object, and perform performance parameter calculation on the object; c2) Routing unit structure configuration module: further configure the routing unit structure parameters in combination with the configured topology parameters; c3) Network interface configuration module: configure and realize the connection relationship between network nodes and resource nodes; configure network interface unit related parameters according to network topology parameters and routing unit structure parameters, so as to convert fixed-format data packets to adapt to the current topology network The data chip format of the system; c4) Traffic parameter configuration module: configure the parameters of spatial distribution and time distribution generated by traffic, data packet length, number of resource nodes, and generate EDA simulation test platform data and TestBench; c5) EDA simulation data analysis: analyze the on-chip network performance parameter data collected by the EDA simulation tool, and generate an on-chip network performance evaluation report.