CN110957983B - Three-frequency pseudo-random variable spread spectrum modulation method and filter-free pulse width modulator constructed by same - Google Patents
Three-frequency pseudo-random variable spread spectrum modulation method and filter-free pulse width modulator constructed by same Download PDFInfo
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Abstract
Description
技术领域Technical Field
本发明涉及免滤波数字D类音频功放领域,尤其涉及一种用于免滤波数字D类音频功放的三频率伪随机可变的扩频调制方法。The invention relates to the field of filter-free digital class D audio power amplifiers, and in particular to a three-frequency pseudo-random variable spread spectrum modulation method for filter-free digital class D audio power amplifiers.
背景技术Background Art
数字D类音频功放因其具有高电源效率、方便与数字音源接口、体积小等诸多优点普遍的应用在当今消费类电子产品中。传统数字D类音频功放的结构示意图如附图1所示,包括依次连接的脉冲宽度调制器、功率级和LC模拟低通滤波器。在传统数字D类音频功放中,功放输入的数字音频信号首先通过脉冲宽度调制器被调制成脉冲宽度调制(PulseWidth Modulation,PWM)信号,然后由功率级的大功率晶体管进行放大,最后通过电感电容(LC)模拟低通滤波器滤除高频成分后驱动扬声器发声。由于LC模拟低通滤波器占据了整个功放系统75%左右的体积,且耗费了30%左右的成本,极大地增加了功放系统的体积和成本,不符合当今视听产品小型化和便携化的发展趋势,因此,免滤波数字D类音频功放出现并成为研究热点。Digital Class D audio amplifiers are widely used in today's consumer electronic products because of their many advantages such as high power efficiency, convenient interface with digital audio sources, and small size. The structural schematic diagram of a traditional digital Class D audio amplifier is shown in Figure 1, including a pulse width modulator, a power stage, and an LC analog low-pass filter connected in sequence. In a traditional digital Class D audio amplifier, the digital audio signal input to the amplifier is first modulated into a pulse width modulation (PWM) signal by a pulse width modulator, then amplified by a high-power transistor of the power stage, and finally driven to produce sound after filtering out high-frequency components through an inductor capacitor (LC) analog low-pass filter. Since the LC analog low-pass filter occupies about 75% of the volume of the entire amplifier system and consumes about 30% of the cost, it greatly increases the volume and cost of the amplifier system, which does not conform to the development trend of miniaturization and portability of today's audio-visual products. Therefore, filter-free digital Class D audio amplifiers have emerged and become a research hotspot.
免滤波数字D类音频功放的结构示意图如附图2所示,其主要由免滤波脉冲宽度调制器和H桥式功率级组成。免滤波脉冲宽度调制器主要由插值滤波器、取反模块、Sigma-Delta调制器和均匀采样脉冲宽度调制(Uniform-sampling Pulse Width Modulation,UPWM)发生器组成,其利用过采样技术、量化噪声整形技术以及UPWM技术在基本保持输入信号基带信息不变的情况下,把数字音频信号转换为四路UPWM信号,该四路UPWM信号驱动H桥式功率级,会在扬声器负载上形成三级UPWM信号。由于三级UPWM让功放负载两端的电压在每个开关周期内的大部分时间等于零伏从而大幅减少了流过负载的电流,使功放在效率方面降低了对LC模拟低通滤波器的依赖。然而,免滤波数字D类音频功放输出信号在脉冲重复频率(Pulse Repetition Frequency,PRF)以及其谐波处有较高的能量,这些高频成分能量将导致功放输出信号产生较严重的电磁干扰(Electro-Magnetic Interference,EMI)。因此,为了进一步提高免滤波数字D类音频功放的实用性,需要利用特殊的方法来降低功放输出信号的高频能量尖峰,从而降低功放的EMI。对于D类音频功放的EMI抑制方法,主要分为两类:(1)从源头抑制,比如采用软开关技术、扩频调制技术等;(2)从传输路径抑制,比如板级系统布局布线优化设计,采用屏蔽技术等。由于扩频调制技术实现相对简单,且易于控制,因此成为解决D类音频功放EMI问题的主要办法。The structural diagram of the filter-free digital Class D audio power amplifier is shown in Figure 2, which is mainly composed of a filter-free pulse width modulator and an H-bridge power stage. The filter-free pulse width modulator is mainly composed of an interpolation filter, an inversion module, a Sigma-Delta modulator and a uniform-sampling pulse width modulation (UPWM) generator. It uses oversampling technology, quantization noise shaping technology and UPWM technology to convert the digital audio signal into four-way UPWM signals while basically keeping the input signal baseband information unchanged. The four-way UPWM signals drive the H-bridge power stage and form a three-level UPWM signal on the speaker load. Since the three-level UPWM makes the voltage across the power amplifier load equal to zero volts for most of the time in each switching cycle, the current flowing through the load is greatly reduced, so that the power amplifier reduces its dependence on the LC analog low-pass filter in terms of efficiency. However, the output signal of the filter-free digital Class D audio amplifier has high energy at the pulse repetition frequency (PRF) and its harmonics. These high-frequency component energies will cause the output signal of the amplifier to generate serious electromagnetic interference (EMI). Therefore, in order to further improve the practicality of the filter-free digital Class D audio amplifier, special methods are needed to reduce the high-frequency energy peaks of the amplifier output signal, thereby reducing the EMI of the amplifier. The EMI suppression methods of Class D audio amplifiers are mainly divided into two categories: (1) suppression from the source, such as using soft switching technology, spread spectrum modulation technology, etc.; (2) suppression from the transmission path, such as board-level system layout and wiring optimization design, using shielding technology, etc. Since spread spectrum modulation technology is relatively simple to implement and easy to control, it has become the main method to solve the EMI problem of Class D audio amplifiers.
目前已经公开发表的用于D类音频功放的扩频调制方法主要有:低功耗频率调制法(Yeh M L,Liou W R,Hsieh H P,et al.An electromagnetic interference(EMI)reduced high-efficiency switching power amplifier[J].IEEE Transactions onPower Electronics,2010,25(3):710-718.)、构造“PWM Chopping”模块法(Balmelli P,Khoury J M,Viegas E,et al.A low-EMI 3-W audio class-D amplifier compatiblewith AM/FM radio[J].IEEE Journal of Solid-State Circuits,2013,48(8):1771-1782.)、随机卷绕脉冲位置调制法(Adrian V,Keer C,Gwee B H,et al.A randomizedmodulation scheme for filterless digital class D audio amplifiers[C].Proceedings of the 2014IEEE International Symposium on Circuits andSystems.IEEE,2014:774-777.)、多频脉冲调制法(Karaca T,Auer M.Digital pulse-width modulator with spread-spectrum emission reduction.e&i Elektrotechnikund Informationstechnik,2018,135(1):48-53.)等。低功耗频率调制法通过构造一个超低功耗扩频时钟发生器实时改变功放PWM信号的PRF,在降低功放EMI的同时也很好的保持了功放的高效率,但此方法需要模拟电路实现或者需要模拟输入信号参与调制,因此只适用于模拟D类音频功放。构造“PWM Chopping”模块法利用零输入Sigma-Delta调制器的噪声整形功能对输出PWM信号进行逐帧控制,使功放负载两端的共模高频尖峰降低,但系统需要较高的主时钟频率。随机卷绕脉冲位置调制法通过对UPWM信号每个脉冲在当前开关周期内的位置随机化从而实现扩频,该方法由于是基于二级PWM技术的,因此,虽然能使功放拥有较低的EMI,但是却大幅降低了效率。多频率脉冲调制法通过两个可逆计数器来控制UPWM发生器的输出信号的PRF,从而达到扩频的目的,该方法虽然能一定程度的降低功放输出信号频谱的高频最大幅度,但会造成功放输出信号在基带内产生互调失真。The main spread spectrum modulation methods for class D audio amplifiers that have been published include: low-power frequency modulation method (Yeh M L, Liou W R, Hsieh H P, et al. An electromagnetic interference (EMI) reduced high-efficiency switching power amplifier [J]. IEEE Transactions on Power Electronics, 2010, 25 (3): 710-718.), construction of "PWM Chopping" module method (Balmelli P, Khoury J M, Viegas E, et al. A low-EMI 3-W audio class-D amplifier compatible with AM/FM radio [J]. IEEE Journal of Solid-State Circuits, 2013, 48 (8): 1771-1782.), random winding pulse position modulation method (Adrian V, Keer C, Gwee B H, et al. A randomized modulation scheme for filterless digital class D audio amplifiers [C]. Proceedings of the 2014 IEEE International Symposium on Circuits and Systems. IEEE, 2014: 774-777.), multi-frequency pulse modulation method (Karaca T, Auer M. Digital pulse-width modulator with spread-spectrum emission reduction. e&i Elektrotechnik und Informationstechnik, 2018, 135(1): 48-53.), etc. The low-power frequency modulation method changes the PRF of the power amplifier PWM signal in real time by constructing an ultra-low power spread spectrum clock generator, which reduces the EMI of the power amplifier while also maintaining the high efficiency of the power amplifier. However, this method requires analog circuit implementation or analog input signals to participate in modulation, so it is only suitable for analog Class D audio amplifiers. The "PWM Chopping" module method uses the noise shaping function of the zero-input Sigma-Delta modulator to control the output PWM signal frame by frame, so that the common-mode high-frequency spikes at both ends of the power amplifier load are reduced, but the system requires a higher master clock frequency. The random winding pulse position modulation method realizes spectrum spread by randomizing the position of each pulse of the UPWM signal in the current switching cycle. Since this method is based on the two-level PWM technology, although it can make the power amplifier have lower EMI, it greatly reduces the efficiency. The multi-frequency pulse modulation method controls the PRF of the output signal of the UPWM generator through two reversible counters to achieve the purpose of spectrum spread. Although this method can reduce the high-frequency maximum amplitude of the power amplifier output signal spectrum to a certain extent, it will cause the power amplifier output signal to produce intermodulation distortion in the baseband.
发明内容Summary of the invention
针对现有扩频调制方法的不足,本发明提供一种用于免滤波数字D类音频功放的扩频调制方法,该方法易于实现,且能够在降低系统THD的同时,大幅降低功放输出UPWM信号的高频成分幅度,达到降低EMI的目的。该方法的实现步骤为:In view of the shortcomings of the existing spread spectrum modulation method, the present invention provides a spread spectrum modulation method for a filter-free digital Class D audio power amplifier. The method is easy to implement and can significantly reduce the high-frequency component amplitude of the UPWM signal output by the power amplifier while reducing the system THD, thereby achieving the purpose of reducing EMI. The implementation steps of the method are:
步骤一:利用插值滤波器,把功放输入信号的采样频率fo提升N倍到采样频率fs,并根据该采样频率fs确定所需三个采样频率的中间频率fc,其中fc=fs/q,q为小于N的整数;Step 1: Use an interpolation filter to increase the sampling frequency f o of the power amplifier input signal by N times to the sampling frequency f s , and determine the intermediate frequency f c of the three required sampling frequencies according to the sampling frequency f s , where f c = f s /q, q is an integer less than N;
步骤二:利用频率合成技术,根据功放系统主时钟信号clk_m和已确定的中间频率fc确定另外两个采样频率fcs和fcl,其中,fcs为三者中最小的采样频率,Ns=p+v,fcl为三者中最大的采样频率,N1=p-v,v∈[1,p-1]且v为整数,fclk_m为主时钟信号clk m的频率,m为UPWM发生器的级数;Step 2: Using frequency synthesis technology, determine the other two sampling frequencies fcs and fcl according to the main clock signal clk_m of the power amplifier system and the determined intermediate frequency fc , where fcs is the smallest sampling frequency among the three. N s = p + v, f cl is the largest sampling frequency among the three, N 1 = pv, v∈[1, p-1] and v is an integer, f clk_m is the frequency of the main clock signal clk m, where m is the number of stages of the UPWM generator;
步骤三:构建一个可变倍数抽取器,在可变倍数抽取器中构建一个有限状态机和一个由2n级线性反馈移位寄存器构成的伪随机数生成器,该有限状态机利用该伪随机数生成器生成的n位伪随机数rand_num得出与之唯一对应的最终状态;有限状态机初始状态为S0,让一位变量K从该n位伪随机数最高位到最低位依次取值,有限状态机根据K值和当前状态确定下一个状态,直到K取到该伪随机数的最低位,输出最终状态,该有限状态机共有三种最终状态,分别为:S0、S1、S2;Step 3: Construct a variable multiple extractor, construct a finite state machine and a pseudo-random number generator composed of a 2n-level linear feedback shift register in the variable multiple extractor, and the finite state machine uses the n-bit pseudo-random number rand_num generated by the pseudo-random number generator to obtain the final state that uniquely corresponds to it; the initial state of the finite state machine is S 0 , and a variable K is allowed to take values from the highest bit to the lowest bit of the n-bit pseudo-random number in sequence. The finite state machine determines the next state according to the K value and the current state until K takes the lowest bit of the pseudo-random number and outputs the final state. The finite state machine has three final states, namely: S 0 , S 1 , and S 2 ;
步骤四:在可变倍数抽取器中构建一个阈值生成器、一个第一计数器和一个时钟生成器;阈值生成器根据上述有限状态机输出的最终状态,确定一个与之相对应的阈值thr_val,该阈值为当前可变倍数抽取器的抽取倍数,共有三个值,分别为:ts、tc、t1;第一计数器为加一计数器,其对时钟信号clk_bas的上升沿进行计数,时钟信号clk_bas由主时钟信号clk_m分频所得,其频率fclk_bas=fs,当计数值为零时,时钟生成器的输出时钟信号clk_s置于高电平,当计数器的值cou_val与当前阈值相同时,时钟信号clk_s置于低电平,当计数器的值cou_val与当前阈值thr_val相同时,时钟信号clk_s再次置于高电平,同时计数器清零,[]取整为舍去小数位取整;时钟生成器根据阈值thr_val、计数器的值cou_val和时钟信号clk_bas生成一个新的具有三个频率的时钟信号clk_s;Step 4: construct a threshold generator, a first counter and a clock generator in the variable multiple extractor; the threshold generator determines a corresponding threshold thr_val according to the final state output by the above finite state machine, and the threshold is the extraction multiple of the current variable multiple extractor, and there are three values in total, namely: ts , tc , t1 ; the first counter is an add-one counter, which counts the rising edges of the clock signal clk_bas, and the clock signal clk_bas is obtained by dividing the main clock signal clk_m, and its frequency fclk_bas = fs . When the count value is zero, the output clock signal clk_s of the clock generator is set to a high level. When the value of the counter cou_val is equal to the current threshold When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a low level. When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a high level again, and the counter is cleared at the same time. [] is rounded to the integer without decimal places. The clock generator generates a new clock signal clk_s with three frequencies according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas.
步骤五:在可变倍数抽取器中构建一个数据处理模块,当检测到时钟信号clk_s上升沿时,输出当前采样点的值,从而把插值滤波器输出的单一采样频率信号data处理为具有三个采样频率的信号data_t;Step 5: Build a data processing module in the variable multiple extractor. When the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, thereby processing the single sampling frequency signal data output by the interpolation filter into a signal data_t with three sampling frequencies;
步骤六:构建一个校正模块,当检测到时钟信号clk_s的上升沿时,利用校正算法对输入信号data_t中当前采样点的幅值重新计算并赋值,输出一个新的信号data_t′,使其经过后边沿UPWM发生器后得到的UPWM信号在时域上近似自然采样脉冲宽度调制(Natural-sampling Pulse Width Modulation,NPWM)信号;Step 6: Construct a correction module. When the rising edge of the clock signal clk_s is detected, the correction algorithm is used to recalculate and assign the amplitude of the current sampling point in the input signal data_t, and a new signal data_t′ is output, so that the UPWM signal obtained after passing through the trailing edge UPWM generator is similar to the natural sampling pulse width modulation (NPWM) signal in the time domain;
步骤七:构建m级后边沿UPWM发生器,在m级后边沿UPWM发生器中构建一个第二计数器,该计数器同样为加一计数器,其对时钟信号clk_m的上升沿进行计数,当检测到时钟信号clk_s的上升沿时,该计数器清零;Step 7: construct an m-level trailing edge UPWM generator, and construct a second counter in the m-level trailing edge UPWM generator. The counter is also an add-one counter, which counts the rising edge of the clock signal clk_m. When the rising edge of the clock signal clk_s is detected, the counter is reset;
步骤八:在m级后边沿UPWM发生器中构建一个幅值调整模块,由于后边沿UPWM发生器输入时钟信号clk_s的频率和后边沿UPWM发生器输入数字音频信号data_t′的采样频率同步可变,为使后边沿UPWM发生器输出的后边沿UPWM信号占空比相较未扩频时保持不变,该模块根据输入的时钟信号clk_s和阈值信号thr_val,通过当前的thr_val值判断当前clk_s的频率,从而实时调整后边沿UPWM发生器输入数字音频信号data_t′的各采样点幅值,输出一个新的信号data_t″;Step 8: construct an amplitude adjustment module in the m-level trailing edge UPWM generator. Since the frequency of the clock signal clk_s input to the trailing edge UPWM generator and the sampling frequency of the digital audio signal data_t′ input to the trailing edge UPWM generator are synchronously variable, in order to keep the duty cycle of the trailing edge UPWM signal output by the trailing edge UPWM generator unchanged compared to when the spectrum is not spread, the module judges the frequency of the current clk_s according to the current thr_val value based on the input clock signal clk_s and the threshold signal thr_val, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t′ input to the trailing edge UPWM generator in real time and outputting a new signal data_t″;
步骤九:在m级后边沿UPWM发生器中构建一个比较器,比较器在每个时钟信号clk_m的上升沿判断步骤七中第二计数器的输出值coun是否大于阈值y;若是,比较器输出为0,反之输出为1,从而输出具有三个采样频率的后边沿二级UPWM信号;其中,阈值y和幅值调整模块输出信号data_t″的当前采样点幅值相等。Step 9: A comparator is constructed in the m-level trailing edge UPWM generator. The comparator determines whether the output value coun of the second counter in
所述步骤三中,2n级线性反馈移位寄存器由2n个D触发器和若干门电路组成,受时钟信号clk_r和复位信号reset控制,时钟信号clk_r由主时钟信号clk_m分频所得,其频率fclk_r大于三个采样频率中最大值fc1,每经过一个clk_r的时钟周期,2n级线性反馈移位寄存器的后n个D触发器的输出值组成n位伪随机数rand_num。In the
所述步骤三中,有限状态机的状态判定规则为:若当前状态为S0,K取值为0,则下一个状态为S0;若当前状态为S0,K取值为1,则下一个状态为S1;若当前状态为S1,K取值为0,则下一个状态为S2;若当前状态为S1,K取值为1,则下一个状态为S0;若当前状态为S2,K取值为0,则下一个状态为S1;若当前状态为S2,K取值为1,则下一个状态为S2。In the step three, the state determination rule of the finite state machine is: if the current state is S 0 and the value of K is 0, the next state is S 0 ; if the current state is S 0 and the value of K is 1, the next state is S 1 ; if the current state is S 1 and the value of K is 0, the next state is S 2 ; if the current state is S 1 and the value of K is 1, the next state is S 0 ; if the current state is S 2 and the value of K is 0, the next state is S 1 ; if the current state is S 2 and the value of K is 1, the next state is S 2 .
所述步骤四中,阈值生成器生成阈值thr_val的规则是:在当前伪随机数对应的最终状态为S0时,阈值thr_val为t1;在当前伪随机数对应的最终状态为S1时,阈值thr_val为tc;在当前伪随机数对应的最终状态为S2时,阈值thr_val为ts。In
所述步骤四中,时钟信号clk_s的生成规则是:在当前阈值thr_val为t1时,时钟信号clk_s在当前周期的频率为fcs;在当前阈值thr_val为tc时,时钟信号clk_s在当前周期的频率为fc;在当前阈值thr_val为ts时,时钟信号clk_s在当前周期的频率为fc1。In
所述步骤六中,校正模块中使用的校正算法为:假设F1(x1,in1)、F2(x2,in2)和F3(x3,in3)为相邻的三个输入调制信号的采样点,其中F2为当前采样点,F1为前一个采样点,F3为后一个采样点,in1、in2和in3分别为该三个采样点的幅值,x2=0,f1和f2分别为采样点F1和F2所对应的采样频率;对载波信号和采样点的幅值进行归一化处理,使其最小值为0,最大值为1,则在采样点F2和F3之间的锯齿波载波波形表达式为:求该载波和由该三个采样点构造的二阶牛顿插值曲线的交点(伪自然采样点)幅值以代替当前采样点的幅值输入到后边沿UPWM发生器可使产生的后边沿UPWM信号在时域上近似后边沿NPWM信号,从而降低信号的谐波失真;该二阶牛顿插值曲线函数表达式为:inp(x)=λ1+λ2·(x-x1)+λ3·(x-x1)·x,其中,λ1=in1,令F(x)=inp(x)-cw(x)=0,设定x的初始值为利用牛顿-拉夫逊迭代方法可求得F(x)的近似解其中in′p(x)=λ2+λ3·x+λ3·(x-x1);最后,将xb代入到载波波形表达式,求得伪自然采样点幅值由inb经过后边沿UPWM发生器产生的后边沿UPWM信号在时域上近似后边沿NPWM信号。In
所述步骤八中,幅值调整模块的幅值调整规则为:在当前阈值信号thr_val为t1时,当前时钟信号clk_s的频率为fcs,当前采样点幅值的调整公式为:在当前阈值信号thr_val为tc时,当前时钟信号clk_s的频率为fc,当前采样点幅值的调整公式为:在当前阈值信号thr_val为ts时,当前时钟信号clk_s的频率为fc1,当前采样点幅值的调整公式为:其中,val_data′为当前采样点原幅值。In step eight, the amplitude adjustment rule of the amplitude adjustment module is: when the current threshold signal thr_val is t1 , the frequency of the current clock signal clk_s is fcs , and the adjustment formula of the current sampling point amplitude is: When the current threshold signal thr_val is t c , the frequency of the current clock signal clk_s is f c , and the adjustment formula of the current sampling point amplitude is: When the current threshold signal thr_val is ts , the frequency of the current clock signal clk_s is fc1 , and the adjustment formula of the current sampling point amplitude is: Among them, val_data′ is the original amplitude of the current sampling point.
利用上述三频率伪随机可变的扩频调制方法构建的免滤波脉冲宽度调制器,所述免滤波脉冲宽度调制器包括插值滤波器、可变倍数抽取器、取反模块、第一校正模块、第二校正模块、第一Sigma-Delta调制器、第二Sigma-Delta调制器、第一后边沿UPWM发生器和第二后边沿UPWM发生器;数字音频输入信号与插值滤波器相连接,插值滤波器与可变倍数抽取器相连接,可变倍数抽取器分别与第一校正模块和取反模块相连接,取反模块与第二校正模块相连接,第一校正模块与第一Sigma-Delta调制器相连接,第二校正模块与第二Sigma-Delta调制器相连接,第一Sigma-Delta调制器与第一后边沿UPWM发生器相连接,第二Sigma-Delta调制器与第二后边沿UPWM发生器相连接,第一后边沿UPWM发生器输出的两路后边沿UPWM信号和第二后边沿UPWM发生器输出的两路后边沿UPWM信号均与功放的H桥式功率级相连接。The filter-free pulse width modulator constructed by the above-mentioned three-frequency pseudo-random variable spread spectrum modulation method includes an interpolation filter, a variable multiple extractor, an inversion module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first trailing edge UPWM generator and a second trailing edge UPWM generator; the digital audio input signal is connected to the interpolation filter, the interpolation filter is connected to the variable multiple extractor, the variable multiple extractor is respectively connected to the first correction module and the inversion module, and the inversion module is connected to the first correction module. The inverse module is connected to the second correction module, the first correction module is connected to the first Sigma-Delta modulator, the second correction module is connected to the second Sigma-Delta modulator, the first Sigma-Delta modulator is connected to the first rear edge UPWM generator, the second Sigma-Delta modulator is connected to the second rear edge UPWM generator, and the two rear edge UPWM signals output by the first rear edge UPWM generator and the two rear edge UPWM signals output by the second rear edge UPWM generator are both connected to the H-bridge power stage of the power amplifier.
所述插值滤波器为32倍插值滤波器,所述第一Sigma-Delta调制器和第二Sigma-Delta调制器相同且均为8阶前馈内插式Sigma-Delta调制器,第一Sigma-Delta调制器和第二Sigma-Delta调制器都把24位高精度输入信号转换为7位65个量化等级的低精度信号以使第一后边沿UPWM发生器和第二后边沿UPWM发生器输出64级后边沿UPWM信号。The interpolation filter is a 32-fold interpolation filter, the first Sigma-Delta modulator and the second Sigma-Delta modulator are the same and are both 8th-order feedforward interpolation Sigma-Delta modulators, and the first Sigma-Delta modulator and the second Sigma-Delta modulator both convert a 24-bit high-precision input signal into a 7-bit low-precision signal with 65 quantization levels so that the first trailing edge UPWM generator and the second trailing edge UPWM generator output a 64-level trailing edge UPWM signal.
所述可变倍数抽取器包括第一计数器、时钟生成器、伪随机数生成器、阈值生成器、有限状态机和数据处理模块;系统主时钟信号与可变倍数抽取器相连;时钟信号clk_r分别与伪随机数生成器和有限状态机相连接,该时钟信号clk_r由主时钟信号clk_m分频所得,其频率fclk_r大于三个采样频率中最大值fcl,伪随机数生成器与有限状态机相连接,有限状态机和阈值生成器相连接,阈值生成器根据有限状态机输出的最终状态确定一个与之对应的阈值thr_val;时钟信号clk_bas分别与伪随机数生成器、有限状态机、第一计数器和时钟生成器相连接,第一计数器和阈值生成器均与时钟生成器相连接,时钟生成器利用频率合成技术生成一个新的时钟信号clk_s;时钟生成器和输入信号data均与数据处理模块相连接,数据处理模块根据时钟生成器产生的时钟信号clk_s对输入的数字音频信号data进行抽取处理,从而输出具有三个采样频率的数字音频信号data_t。The variable multiple extractor includes a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine and a data processing module; the system main clock signal is connected to the variable multiple extractor; the clock signal clk_r is connected to the pseudo-random number generator and the finite state machine respectively, and the clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f clk_r is greater than the maximum value f cl among the three sampling frequencies , the pseudo-random number generator is connected to the finite state machine, the finite state machine is connected to the threshold generator, and the threshold generator determines a threshold thr_val corresponding to the final state output by the finite state machine; the clock signal clk_bas is respectively connected to the pseudo-random number generator, the finite state machine, the first counter and the clock generator, the first counter and the threshold generator are both connected to the clock generator, and the clock generator generates a new clock signal clk_s using frequency synthesis technology; the clock generator and the input signal data are both connected to the data processing module, and the data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, thereby outputting a digital audio signal data_t with three sampling frequencies.
所述伪随机数生成器主要由一个16级的线性反馈移位寄存器构成,通过给线性反馈移位寄存器设置一个初始状态,每经过一个clk_r周期,线性反馈移位寄存器就产生一个8位的伪随机数并输入给有限状态机;有限状态机根据当前伪随机数计算得出与之对应的最终状态并输入给阈值生成器,阈值生成器根据当前最终状态确定当前可变倍数抽取器的抽取倍数。The pseudo-random number generator is mainly composed of a 16-stage linear feedback shift register. By setting an initial state for the linear feedback shift register, the linear feedback shift register generates an 8-bit pseudo-random number and inputs it to the finite state machine every clk_r cycle; the finite state machine calculates the corresponding final state according to the current pseudo-random number and inputs it to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state.
所述第一计数器对时钟信号clk_bas的上升沿进行计数,当检测到clk_bas的上升沿时,该计数器的值加1;当检测到该计数器的值与当前阈值thr_val相等时,计数器清零。The first counter counts the rising edges of the clock signal clk_bas. When the rising edge of clk_bas is detected, the value of the counter is increased by 1; when it is detected that the value of the counter is equal to the current threshold thr_val, the counter is cleared.
所述第一和第二校正模块相同,都是根据可变倍数抽取器输出的阈值信号thr_val、时钟信号clk_s和具有三个采样频率的数字音频信号data_t,利用校正技术重新计算每个采样点的幅值,从而输出一个新的信号data_t′。The first and second correction modules are the same, both of which use correction technology to recalculate the amplitude of each sampling point based on the threshold signal thr_val, clock signal clk_s and digital audio signal data_t with three sampling frequencies output by the variable multiple extractor, thereby outputting a new signal data_t′.
所述第一后边沿UPWM发生器和第二后边沿UPWM发生器相同,其包括幅值调整模块、第二计数器、比较器和取反模块;时钟信号clk_s分别与第二计数器和幅值调整模块相连,数字音频信号data_t′与幅值调整模块相连,时钟信号clk_m分别与第二计数器和比较器相连,幅值调整模块和第二计数器分别与比较器相连,比较器一路直接输出,一路与取反模块相连后输出;所述幅值调整模块根据调整规则对当前采样点幅值进行计算调整;所述第二计数器对时钟信号clk_m的上升沿进行计数,当检测到时钟信号clk_s的上升沿,该计数器清零;所述比较器对计数器值和调整后的信号幅值进行比较,一路直接输出为后边沿UPWM信号,另一路经取反模块取反后输出后边沿UPWM信号。The first trailing edge UPWM generator is the same as the second trailing edge UPWM generator, and includes an amplitude adjustment module, a second counter, a comparator and an inversion module; the clock signal clk_s is respectively connected to the second counter and the amplitude adjustment module, the digital audio signal data_t′ is connected to the amplitude adjustment module, the clock signal clk_m is respectively connected to the second counter and the comparator, the amplitude adjustment module and the second counter are respectively connected to the comparator, one path of the comparator is directly output, and the other path is connected to the inversion module and then output; the amplitude adjustment module calculates and adjusts the amplitude of the current sampling point according to the adjustment rule; the second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared; the comparator compares the counter value with the adjusted signal amplitude, one path is directly output as the trailing edge UPWM signal, and the other path is inverted by the inversion module and outputs the trailing edge UPWM signal.
与现有技术比较,本发明的有益效果是:Compared with the prior art, the beneficial effects of the present invention are:
1、本发明基于免滤波调制架构、后边沿UPWM技术和伪随机扩频调制技术,通过构造可变倍数抽取器将输入音频信号采样成为具有三个采样频率的音频信号,并合成一个与数字音频信号同步的时钟信号,之后利用校正模块对每个采样点的幅值进行校正,减少UPWM过程中引入的基带失真,从而在降低输出UPWM信号的高频峰值幅度的同时能很好的保证引入较少的谐波失真,以达到降低功放EMI和THD的目的。1. The present invention is based on a filter-free modulation architecture, a trailing edge UPWM technology and a pseudo-random spread spectrum modulation technology. By constructing a variable multiple decimator, the input audio signal is sampled into an audio signal with three sampling frequencies, and a clock signal synchronized with the digital audio signal is synthesized. Then, the amplitude of each sampling point is corrected by a correction module to reduce the baseband distortion introduced in the UPWM process. Thus, while reducing the high-frequency peak amplitude of the output UPWM signal, it can well ensure that less harmonic distortion is introduced, so as to achieve the purpose of reducing the EMI and THD of the power amplifier.
2、本发明提出的方法可全数字电路实现,并且可方便的应用到现有的免滤波数字D类音频功放系统中。2. The method proposed in the present invention can be implemented by a fully digital circuit and can be conveniently applied to the existing filter-free digital Class D audio power amplifier system.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
图1为传统数字D类音频功放的结构示意图;FIG1 is a schematic diagram of the structure of a conventional digital Class D audio power amplifier;
图2为免滤波数字D类音频功放的结构示意图;FIG2 is a schematic diagram of the structure of a filter-free digital Class D audio power amplifier;
图3为本发明实施例的免滤波脉冲宽度调制器结构示意图;FIG3 is a schematic structural diagram of a filter-free pulse width modulator according to an embodiment of the present invention;
图4为本发明的可变倍数抽取器结构示意图;FIG4 is a schematic diagram of the structure of a variable multiple decimator according to the present invention;
图5为本发明的线性反馈移位寄存器结构示意图;FIG5 is a schematic diagram of the structure of a linear feedback shift register according to the present invention;
图6为本发明的有限状态机状态转移图;FIG6 is a state transition diagram of a finite state machine of the present invention;
图7为本发明的校正算法示意图;FIG7 is a schematic diagram of a correction algorithm of the present invention;
图8为本发明的后边沿UPWM发生器结构示意图;FIG8 is a schematic diagram of the structure of a trailing edge UPWM generator of the present invention;
图9为本发明的测试系统示意图;FIG9 is a schematic diagram of a test system of the present invention;
图10为图9的测试系统采用不带扩频调制功能的免滤波脉冲宽度调制器输出的后边沿三级UPWM信号的基带频谱图;FIG10 is a baseband spectrum diagram of a trailing edge three-level UPWM signal output by the test system of FIG9 using a filter-free pulse width modulator without a spread spectrum modulation function;
图11为图9的测试系统采用基于本发明所提扩频调制方法的免滤波脉冲宽度调制器输出的后边沿三级UPWM信号的基带频谱图;11 is a baseband spectrum diagram of a trailing edge three-level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention;
图12为图9的测试系统采用不带扩频调制功能的免滤波脉冲宽度调制器输出的后边沿三级UPWM信号的高频频谱图;FIG12 is a high frequency spectrum diagram of the trailing edge three-level UPWM signal output by the test system of FIG9 using a filter-free pulse width modulator without spread spectrum modulation function;
图13为图9的测试系统采用基于本发明所提扩频调制方法的免滤波脉冲宽度调制器输出的后边沿三级UPWM信号的高频频谱图。FIG. 13 is a high frequency spectrum diagram of the trailing edge three-level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention.
具体实施方式DETAILED DESCRIPTION
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
一种用于免滤波数字D类音频功放的三频率伪随机可变的扩频调制方法,其步骤如下。A three-frequency pseudo-random variable spread spectrum modulation method for a filter-free digital class D audio power amplifier, the steps of which are as follows.
第一步:利用插值滤波器,把功放输入信号的采样频率fo提升N倍到采样频率fs,并根据该采样频率fs确定所需三个采样频率的中间频率fc,其中fc=fs/q,q为小于N的整数;Step 1: Use an interpolation filter to increase the sampling frequency f o of the power amplifier input signal by N times to the sampling frequency f s , and determine the intermediate frequency f c of the three required sampling frequencies based on the sampling frequency f s , where f c = f s /q, q is an integer less than N;
第二步:利用频率合成技术,根据功放系统主时钟信号clk_m和已确定的中间频率fc确定另外两个采样频率fcs和fc1,其中,fcs为三者中最小的采样频率,Ns=p+v,fc1为三者中最大的采样频率,N1=p-v,v∈[1,p-1]且v为整数,fclk_m为主时钟信号clk_m的频率,m为UPWM发生器的级数;Step 2: Use frequency synthesis technology to determine the other two sampling frequencies fcs and fc1 according to the main clock signal clk_m of the power amplifier system and the determined intermediate frequency fc, where fcs is the smallest sampling frequency among the three. Ns = p+v, fc1 is the largest sampling frequency among the three, N 1 = pv, v∈[1, p-1] and v is an integer, f clk_m is the frequency of the main clock signal clk_m, m is the number of stages of the UPWM generator;
第三步:构建一个可变倍数抽取器,在可变倍数抽取器中构建一个有限状态机和一个由2n级线性反馈移位寄存器构成的伪随机数生成器,该有限状态机利用该伪随机数生成器生成的n位伪随机数rand_num得出与之唯一对应的最终状态;2n级线性反馈移位寄存器由2n个D触发器和若干门电路组成,受时钟信号clk_r和复位信号reset控制,时钟信号clk_r由主时钟信号clk_m分频所得,其频率fclk_r大于三个采样频率中最大值fc1,每经过一个clk_r的时钟周期,2n级线性反馈移位寄存器的后n个D触发器的输出值组成n位伪随机数rand_num;有限状态机初始状态为S0,让一位变量K从该n位伪随机数最高位到最低位依次取值,有限状态机根据K值和当前状态确定下一个状态,直到K取到该伪随机数最低位,输出最终状态,该有限状态机共有三种最终状态,分别为:S0、S1、S2;该有限状态机的状态判定规则为:若当前状态为S0,K取值为0,则下一个状态为S0;若当前状态为S0,K取值为1,则下一个状态为S1;若当前状态为S1,K取值为0,则下一个状态为S2;若当前状态为S1,K取值为1,则下一个状态为S0;若当前状态为S2,K取值为0,则下一个状态为S1;若当前状态为S2,K取值为1,则下一个状态为S2;Step 3: Construct a variable multiple extractor, in which a finite state machine and a pseudo-random number generator consisting of a 2n-level linear feedback shift register are constructed. The finite state machine uses the n-bit pseudo-random number rand_num generated by the pseudo-random number generator to obtain the final state that is uniquely corresponding to it; the 2n-level linear feedback shift register is composed of 2n D flip-flops and several gate circuits, and is controlled by the clock signal clk_r and the reset signal reset. The clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f clk_r is greater than the maximum value f c1 of the three sampling frequencies. After each clock cycle of clk_r, the output values of the last n D flip-flops of the 2n-level linear feedback shift register form the n-bit pseudo-random number rand_num; the initial state of the finite state machine is S 0 , let a variable K take values from the highest bit to the lowest bit of the n-bit pseudo-random number in sequence, the finite state machine determines the next state according to the K value and the current state, until K takes the lowest bit of the pseudo-random number, and outputs the final state. The finite state machine has three final states, namely: S 0 , S 1 , S 2 ; the state determination rule of the finite state machine is: if the current state is S 0 , K value is 0, then the next state is S 0 ; if the current state is S 0 , K value is 1, then the next state is S 1 ; if the current state is S 1 , K value is 0, then the next state is S 2 ; if the current state is S 1 , K value is 1, then the next state is S 0 ; if the current state is S 2 , K value is 0, then the next state is S 1 ; if the current state is S 2 , K value is 1, then the next state is S 2 ;
第四步:在可变倍数抽取器中构建一个阈值生成器、一个第一计数器和一个时钟生成器;阈值生成器根据上述有限状态机输出的最终状态,确定一个与之相对应的阈值thr_val,该阈值为当前可变倍数抽取器的抽取倍数,共有三个值,分别为:ts、tc、t1;;该阈值thr_val的确定规则为:在当前伪随机数对应的最终状态为S0时,阈值thr_val为t1;在当前伪随机数对应的最终状态为S1时,阈值thr_val为tc;在当前伪随机数对应的最终状态为S2时,阈值thr_val为ts;第一计数器为加一计数器,其对时钟信号clk_bas的上升沿进行计数,计数值为零时,时钟信号clk_s置于高电平,当计数器的值cou_val与当前阈值相同时,时钟信号clk_s置于低电平,当计数器的值cou_val与当前阈值thr_val相同时,时钟信号clk_s再次置于高电平,同时计数器清零,[]取整为舍去小数位取整;时钟生成器根据阈值thr_val、计数器的值cou_val和时钟信号clk_bas生成一个新的具有三个频率的时钟信号clk_s(其频率分别为fcs、fc和fc1),其中时钟信号clk_bas由主时钟信号clk_m分频所得,其频率fclk_bas=fs;时钟信号clk_s的生成规则为:在当前阈值thr_val为t1时,时钟信号clk_s在当前周期的频率为fcs;在当前阈值thr_val为tc时,时钟信号clk_s在当前周期的频率为fc;在当前阈值thr_val为ts时,时钟信号clk_s在当前周期的频率为fcl;Step 4: construct a threshold generator, a first counter and a clock generator in the variable multiple extractor; the threshold generator determines a corresponding threshold thr_val according to the final state output by the above finite state machine, and the threshold is the extraction multiple of the current variable multiple extractor, and there are three values in total, namely: ts , tc, t1 ; the determination rule of the threshold thr_val is: when the final state corresponding to the current pseudo-random number is S0 , the threshold thr_val is t1 ; when the final state corresponding to the current pseudo-random number is S1 , the threshold thr_val is tc ; when the final state corresponding to the current pseudo-random number is S2 , the threshold thr_val is ts ; the first counter is an add-one counter, which counts the rising edges of the clock signal clk_bas. When the count value is zero, the clock signal clk_s is set to a high level. When the value of the counter cou_val is equal to the current threshold When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a low level. When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a high level again, and the counter is cleared at the same time. [] is rounded to the integer without a decimal place. The clock generator generates a new clock signal clk_s with three frequencies (whose frequencies are f cs , f c and f c1 respectively) according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas, wherein the clock signal clk_bas is obtained by dividing the main clock signal clk_m, and its frequency f clk_bas = f s . The generation rule of the clock signal clk_s is: when the current threshold thr_val is t 1 , the frequency of the clock signal clk_s in the current cycle is f cs ; when the current threshold thr_val is t c , the frequency of the clock signal clk_s in the current cycle is f c ; when the current threshold thr_val is t s , the frequency of the clock signal clk_s in the current cycle is f cl ;
第五步:在可变倍数抽取器中构建一个数据处理模块,当检测到时钟信号clk_s上升沿时,输出当前采样点的值,从而把插值滤波器输出的单一采样频率信号data处理为具有三个采样频率的信号data_t;Step 5: Build a data processing module in the variable multiple extractor. When the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, thereby processing the single sampling frequency signal data output by the interpolation filter into a signal data_t with three sampling frequencies.
第六步:构建一个校正模块,当检测到时钟信号clk_s的上升沿时,利用校正算法对输入信号data_t中当前采样点的幅值重新计算并赋值,输出一个新的信号data_t′,使其经UPWM发生器后得到的U PWM信号在时域上近似于NPWM信号;该校正模块中使用的校正算法为:假设F1(x1,in1)、F2(x2,in2)和F3(x3,in3)为相邻的三个输入调制信号的采样点,其中F2为当前采样点,F1为前一个采样点,F3为后一个采样点,in1、in2和in3分别为该三个采样点的幅值,x2=0,f1和f2分别为采样点F1和F2所对应的采样频率;对载波信号和采样点的幅值进行归一化处理,使其最小值为0,最大值为1,则在采样点F2和F3之间的载波波形表达式为:求该载波和由该三个采样点构造的二阶牛顿插值曲线的交点(伪自然采样点)幅值以代替当前采样点的幅值输入到后边沿UPWM发生器可使产生的后边沿UPWM信号在时域上近似后边沿NPWM信号,从而降低信号的谐波失真;该二阶牛顿插值曲线函数表达式为:inp(x)=λ1+λ2·(x-x1)+λ3·(x-x1)·x,其中,λ1=in1,令F(x)=inp(x)-cw(x)=0,设定x的初始值为利用牛顿-拉夫逊迭代方法可求得F(x)的近似解其中in′p(x)=λ2+λ3·x+λ3·(x-x1);最后,将xb代入到载波波形表达式,求得伪自然采样点幅值由inb经过后边沿UPWM发生器产生的后边沿UPWM信号在时域上近似后边沿NPWM信号;Step 6: Construct a correction module. When the rising edge of the clock signal clk_s is detected, the amplitude of the current sampling point in the input signal data_t is recalculated and assigned using the correction algorithm, and a new signal data_t′ is output, so that the U PWM signal obtained after passing through the UPWM generator is similar to the NPWM signal in the time domain; the correction algorithm used in the correction module is: assuming that F 1 (x 1 , in 1 ), F 2 (x 2 , in 2 ) and F 3 (x 3 , in 3 ) are three adjacent sampling points of the input modulation signal, where F 2 is the current sampling point, F 1 is the previous sampling point, F 3 is the next sampling point, in 1 , in 2 and in 3 are the amplitudes of the three sampling points respectively, x 2 = 0, f1 and f2 are the sampling frequencies corresponding to the sampling points F1 and F2 respectively; the amplitude of the carrier signal and the sampling point are normalized so that the minimum value is 0 and the maximum value is 1, then the carrier waveform expression between the sampling points F2 and F3 is: The amplitude of the intersection point (pseudo natural sampling point) between the carrier and the second-order Newton interpolation curve constructed by the three sampling points is calculated to replace the amplitude of the current sampling point and input into the trailing edge UPWM generator, so that the generated trailing edge UPWM signal can be approximated to the trailing edge NPWM signal in the time domain, thereby reducing the harmonic distortion of the signal; the function expression of the second-order Newton interpolation curve is: in p (x) = λ 1 +λ 2 ·(xx 1 )+λ 3 ·(xx 1 )·x, where λ 1 =in 1 , Let F(x) = in p (x) - cw(x) = 0, and set the initial value of x to The approximate solution of F(x) can be obtained by using the Newton-Raphson iterative method in in′ p (x) = λ 2 + λ 3 ·x + λ 3 ·(x 1 ); Finally, substitute x b into the carrier waveform expression to obtain the amplitude of the pseudo natural sampling point: The trailing edge UPWM signal generated by in b through the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain;
第七步:构建m级后边沿UPWM发生器,在m级后边沿UPWM发生器中构建一个第二计数器,该计数器同样为加一计数器,其对时钟信号clk_m的上升沿进行计数,当检测到时钟信号clk_s的上升沿时,该计数器清零;Step 7: construct an m-level trailing edge UPWM generator, and construct a second counter in the m-level trailing edge UPWM generator. The counter is also an add-one counter, which counts the rising edge of the clock signal clk_m. When the rising edge of the clock signal clk_s is detected, the counter is cleared.
第八步:在m级后边沿UPWM发生器中构建一个幅值调整模块,由于后边沿UPWM发生器输入时钟信号clk_s的频率和后边沿UPWM发生器输入数字音频信号data t′的采样频率同步可变,为使后边沿UPWM发生器输出的后边沿UPWM信号占空比相较未扩频时保持不变,该模块根据输入的时钟信号clk_s和阈值信号thr_val,通过当前的thr_val值判断当前clk_s的频率,从而实时调整后边沿UPWM发生器输入数字音频信号data_t′的各采样点幅值,输出一个新的信号data_t″;该幅值调整模块的幅值调整规则为:在当前阈值信号thr_val为t1时,当前时钟信号clk_s的频率为fcs,当前采样点幅值的调整公式为:在当前阈值信号thr_val为tc时,当前时钟信号clk_s的频率为fc,当前采样点幅值的调整公式为:在当前阈值信号thr_val为ts时,当前时钟信号clk_s的频率为fc1,当前采样点幅值的调整公式为:其中,val_data′为当前采样点原幅值。Step 8: construct an amplitude adjustment module in the m-level trailing edge UPWM generator. Since the frequency of the clock signal clk_s input to the trailing edge UPWM generator and the sampling frequency of the digital audio signal data t′ input to the trailing edge UPWM generator are synchronously variable, in order to keep the duty cycle of the trailing edge UPWM signal output by the trailing edge UPWM generator unchanged compared to when the spectrum is not spread, the module judges the frequency of the current clk_s according to the input clock signal clk_s and the threshold signal thr_val by the current thr_val value, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t′ input to the trailing edge UPWM generator in real time, and outputs a new signal data_t″; the amplitude adjustment rule of the amplitude adjustment module is: when the current threshold signal thr_val is t 1 , the frequency of the current clock signal clk_s is f cs , and the adjustment formula of the current sampling point amplitude is: When the current threshold signal thr_val is t c , the frequency of the current clock signal clk_s is f c , and the adjustment formula of the current sampling point amplitude is: When the current threshold signal thr_val is ts , the frequency of the current clock signal clk_s is fc1 , and the adjustment formula of the current sampling point amplitude is: Among them, val_data′ is the original amplitude of the current sampling point.
第九步:在m级后边沿UPWM发生器中构建一个比较器,比较器在每个时钟信号clk_m的上升沿判断步骤七中计数器的输出值coun是否大于阈值y;若是,比较器输出为0,反之输出为1,从而输出具有三个采样频率的后边沿二级UPWM信号;其中,阈值y和幅值调整模块输出信号data_t″的当前采样点幅值相等。免滤波数字D类音频功放内部每个UPWM发生器输出两路差分信号,两个UPWM发生器一共输出四路UPWM信号以驱动H桥式功率级,使功放负载两端形成三个电压等级,从而使功放在效率方面降低了对LC模拟低通滤波器的依赖,而由于每路UPWM信号的PRF可变,使功放负载两端信号在PRF及其谐波处的能量扩散到周边频带内,从而达到了降低功放EMI的目的。Step 9: A comparator is constructed in the m-level trailing edge UPWM generator. The comparator determines whether the output value coun of the counter in
利用上述三频率伪随机可变的扩频调制方法构建一个免滤波脉冲宽度调制器,其结构示意图如附图3所示。所述免滤波脉冲宽度调制器包括插值滤波器、可变倍数抽取器、取反模块、第一校正模块、第二校正模块、第一Sigma-Delta调制器、第二Sigma-Delta调制器、第一后边沿UPWM发生器和第二后边沿UPWM发生器;数字音频信号与插值滤波器相连接,插值滤波器与可变倍数抽取器相连接,可变倍数抽取器分别与第一校正模块和取反模块相连接,取反模块与第二校正模块相连接,第一校正模块与第一Sigma-Delta调制器相连接,第二校正模块与第二Sigma-Delta调制器相连接,第一Sigma-Delta调制器与第一后边沿UPWM发生器相连接,第二Sigma-Delta调制器与第二后边沿UPWM发生器相连接,第一后边沿UPWM发生器输出的两路后边沿UPWM信号和第二后边沿UPWM发生器输出的两路后边沿UPWM信号均与功放的H桥式功率级相连接。A filter-free pulse width modulator is constructed by using the above three-frequency pseudo-random variable spread spectrum modulation method, and its structural schematic diagram is shown in Figure 3. The filter-free pulse width modulator comprises an interpolation filter, a variable multiple extractor, an inversion module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first rear edge UPWM generator and a second rear edge UPWM generator; the digital audio signal is connected to the interpolation filter, the interpolation filter is connected to the variable multiple extractor, the variable multiple extractor is respectively connected to the first correction module and the inversion module, the inversion module is connected to the second correction module, the first correction module is connected to the first Sigma-Delta modulator, the second correction module is connected to the second Sigma-Delta modulator, the first Sigma-Delta modulator is connected to the first rear edge UPWM generator, the second Sigma-Delta modulator is connected to the second rear edge UPWM generator, and the two rear edge UPWM signals output by the first rear edge UPWM generator and the two rear edge UPWM signals output by the second rear edge UPWM generator are both connected to the H-bridge power stage of the power amplifier.
附图3中fo=48kHz为音频输入信号的采样频率,该免滤波脉冲宽度调制器使用的主时钟clk_m的频率fclk_m为98.304MHz。本发明设计的插值滤波器为实现32倍过采样的插值滤波器,统一把输入信号48kHz的采样频率提高到fs=1536kHz,该采样频率fs也为时钟信号clk_bas的频率。In FIG3, f o =48kHz is the sampling frequency of the audio input signal, and the frequency f clk_m of the master clock clk_m used by the filter-free pulse width modulator is 98.304MHz. The interpolation filter designed by the present invention is an interpolation filter that realizes 32 times oversampling, and uniformly increases the sampling frequency of the input signal 48kHz to f s =1536kHz, and the sampling frequency f s is also the frequency of the clock signal clk_bas.
为实现扩频目的,本发明设计的可变倍数抽取器结构示意图如附图4所示。可变倍数抽取器包括第一计数器、时钟生成器、伪随机数生成器、阈值生成器、有限状态机和数据处理模块。时钟信号clk_bas分别与伪随机数生成器、有限状态机、第一计数器和时钟生成器相连接,第一计数器和阈值生成器均与时钟生成器相连接,时钟生成器利用频率合成技术生成一个新的具有三个频率的时钟信号clk_s。在本系统中,令q=4,v=1,后边沿UPWM发生器的级数m=64,则fc=fs/q=384kHz,Ns=p+v=5,N1=p-v=3, 时钟信号clk_r分别与伪随机数生成器和有限状态机相连接,该时钟信号clk_r由主时钟信号clk_m分频所得,其频率fclk_r大于三个采样频率中最大值fcl,在本系统中,时钟信号clk_r的频率fclk_r为768kHz。16级线性反馈移位寄存器构成的8位伪随机数生成器与有限状态机相连接。该16级线性反馈移位寄存器结构示意图如附图5所示,其由16个D触发器、3个4输入或门、1个3输入或门、1个4输入或非门、4个异或门组成。该16级线性反馈移位寄存器受时钟信号clk_r和复位信号reset控制,每经过一个clk_r的时钟周期,该16级线性反馈移位寄存器中后8个D触发器的输出值组成8位伪随机数rand_num。该有限状态机的状态转移图如附图6所示,有限状态机初始状态为S0,让一位变量K从该8位伪随机数最高位到最低位依次取值,有限状态机根据K值和当前状态确定下一个状态,直到K取到该伪随机数最低位,输出最终状态,该有限状态机共有三种最终状态,分别为:S0、S1、S2。由图6可知,该有限状态机状态判定规则为:若当前状态为S0,K取值为0,则下一个状态为S0;若当前状态为S0时,K取值为1,则下一个状态为S1;若当前状态为S1,K取值为0,则下一个状态为S2;若当前状态为S1,K取值为1,则下一个状态为S0;若当前状态为S2,K取值为0,则下一个状态为S1;若当前状态为S2,K取值为1,则下一个状态为S2。有限状态机和阈值生成器相连接,阈值生成器根据有限状态机输出的最终状态确定一个与之对应的阈值thr_val。阈值生成器生成阈值thr_val的规则为:在当前伪随机数对应的最终状态为S0时,阈值thr_val为t1=fs/fcs=5;在当前伪随机数对应的最终状态为S1时,阈值thr_val为tc=fs/fc=4;在当前伪随机数对应的最终状态为S2时,阈值thr_val为ts=fs/fcl=3。第一计数器对时钟信号clk_bas的上升沿进行加1计数,计数值为零时,时钟生成器的输出时钟信号clk_s置于高电平,当计数器的值cou_val与当前阈值相同时,时钟信号clk_s置于低电平,当计数器的值cou_val与当前阈值thr_val相同时,时钟信号clk_s再次置于高电平,同时计数器清零,[]取整为舍去小数位取整。时钟生成器根据阈值thr_val、计数器的值cou_val和时钟信号clk_bas生成一个新的具有三个频率(307.2kHz、384kHz和512kHz)的时钟信号clk_s。时钟生成器和输入信号data均与数据处理模块相连接,数据处理模块根据时钟生成器产生的时钟信号clk_s对输入的数字音频信号data进行抽取处理,从而输出具有三个采样频率(307.2kHz、384kHz和512kHz)的数字音频信号data_t。In order to achieve the purpose of spectrum spread, the structural schematic diagram of the variable multiple extractor designed by the present invention is shown in Figure 4. The variable multiple extractor includes a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine and a data processing module. The clock signal clk_bas is connected to the pseudo-random number generator, the finite state machine, the first counter and the clock generator respectively. The first counter and the threshold generator are both connected to the clock generator. The clock generator uses frequency synthesis technology to generate a new clock signal clk_s with three frequencies. In this system, let q=4, v=1, and the number of stages of the trailing edge UPWM generator m=64, then fc = fs /q=384kHz, N s =p+v=5, N 1 =pv=3, The clock signal clk_r is connected to the pseudo-random number generator and the finite state machine respectively. The clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f clk_r is greater than the maximum value f cl among the three sampling frequencies. In this system, the frequency f clk_r of the clock signal clk_r is 768kHz. The 8-bit pseudo-random number generator composed of a 16-level linear feedback shift register is connected to the finite state machine. The structural schematic diagram of the 16-level linear feedback shift register is shown in Figure 5, which consists of 16 D flip-flops, 3 4-input OR gates, 1 3-input OR gate, 1 4-input NOR gate, and 4 XOR gates. The 16-level linear feedback shift register is controlled by the clock signal clk_r and the reset signal reset. After each clock cycle of clk_r, the output values of the last 8 D flip-flops in the 16-level linear feedback shift register form an 8-bit pseudo-random number rand_num. The state transition diagram of the finite state machine is shown in Figure 6. The initial state of the finite state machine is S 0 . Let a variable K take values from the highest bit to the lowest bit of the 8-bit pseudo-random number in sequence. The finite state machine determines the next state according to the K value and the current state until K takes the lowest bit of the pseudo-random number and outputs the final state. The finite state machine has three final states, namely: S 0 , S 1 , and S 2 . As shown in Figure 6, the state judgment rule of the finite state machine is: if the current state is S 0 and K is 0, the next state is S 0 ; if the current state is S 0 and K is 1, the next state is S 1 ; if the current state is S 1 and K is 0, the next state is S 2 ; if the current state is S 1 and K is 1, the next state is S 0 ; if the current state is S 2 and K is 0, the next state is S 1 ; if the current state is S 2 and K is 1, the next state is S 2. The finite state machine is connected to the threshold generator, and the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine. The threshold generator generates the threshold thr_val according to the following rule: when the final state corresponding to the current pseudo-random number is S 0 , the threshold thr_val is t 1 = f s / f cs = 5; when the final state corresponding to the current pseudo-random number is S 1 , the threshold thr_val is t c = f s / f c = 4; when the final state corresponding to the current pseudo-random number is S 2 , the threshold thr_val is t s = f s / f cl = 3. The first counter counts the rising edge of the clock signal clk_bas by 1. When the count value is zero, the output clock signal clk_s of the clock generator is set to a high level. When the value of the counter cou_val is equal to the current threshold When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a low level. When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a high level again, and the counter is cleared at the same time. [] is rounded to the nearest integer. The clock generator generates a new clock signal clk_s with three frequencies (307.2kHz, 384kHz and 512kHz) according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas. The clock generator and the input signal data are both connected to the data processing module. The data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, thereby outputting a digital audio signal data_t with three sampling frequencies (307.2kHz, 384kHz and 512kHz).
为了消除功放输出信号的谐波失真,校正模块把数字音频信号data_t校正为data_t′。该校正模块中使用的校正算法示意图如附图7所示。该算法利用NPWM无谐波失真的特性,对UPWM前的调制信号进行校正,使UPWM发生器最终输出的UPWM信号在时域上近似于NPWM信号以消除输出信号的谐波失真。根据调制信号当前采样点、前一个采样点以及后一个采样点,建立一个二阶牛顿插值曲线函数表达式,同时建立载波波形表达式,使用牛顿-拉夫逊迭代法求解载波波形与插值曲线的交点幅值,该点幅值通过后边沿UPWM发生器得到的后边沿UPWM波形在时域上近似于后边沿NPWM波形。In order to eliminate the harmonic distortion of the power amplifier output signal, the correction module corrects the digital audio signal data_t to data_t′. The schematic diagram of the correction algorithm used in the correction module is shown in Figure 7. The algorithm uses the characteristic of NPWM without harmonic distortion to correct the modulation signal before UPWM, so that the UPWM signal finally output by the UPWM generator is similar to the NPWM signal in the time domain to eliminate the harmonic distortion of the output signal. According to the current sampling point, the previous sampling point and the next sampling point of the modulation signal, a second-order Newton interpolation curve function expression is established, and a carrier waveform expression is established at the same time. The Newton-Raphson iteration method is used to solve the intersection amplitude of the carrier waveform and the interpolation curve. The rear edge UPWM waveform obtained by the rear edge UPWM generator at this point is similar to the rear edge NPWM waveform in the time domain.
后边沿UPWM发生器结构示意图如附图8所示,其包括幅值调整模块、第二计数器、比较器和取反模块。时钟信号clk_s分别与第二计数器和幅值调整模块相连,数字音频信号data_t′与幅值调整模块相连,时钟信号clk_m分别与第二计数器和比较器相连,幅值调整模块与比较器相连,第二计数器与比较器相连,比较器一路直接输出,一路与取反模块相连后输出。所述幅值调整模块的作用是:当时钟信号clk_s的频率为fcs时,当前采样点幅值的调整公式为:当时钟信号clk_s的频率为fc时,当前采样点幅值的调整公式为:当时钟信号clk_s的频率为fcl时,当前采样点幅值的调整公式为:其中,val_data′为当前采样点原幅值。所述第二计数器对时钟信号clk_m的上升沿进行计数,当检测到时钟信号clk_s的上升沿,该计数器清零;所述比较器在每个时钟信号clk_m的上升沿对计数器的输出计数值和调整后的信号幅值进行比较,若计数值小于调整后的信号幅值,比较器输出为1;若计数值大于等于调整后的信号幅值,比较器输出为0。反相器对比较器的其中一路输出信号反相从而使一个UPWM发生器输出两路差分UPWM信号。The schematic diagram of the structure of the trailing edge UPWM generator is shown in Figure 8, which includes an amplitude adjustment module, a second counter, a comparator and an inversion module. The clock signal clk_s is connected to the second counter and the amplitude adjustment module respectively, the digital audio signal data_t′ is connected to the amplitude adjustment module, the clock signal clk_m is connected to the second counter and the comparator respectively, the amplitude adjustment module is connected to the comparator, the second counter is connected to the comparator, the comparator directly outputs one way, and outputs one way after being connected to the inversion module. The function of the amplitude adjustment module is: when the frequency of the clock signal clk_s is f cs , the adjustment formula of the amplitude of the current sampling point is: When the frequency of the clock signal clk_s is f c , the adjustment formula for the amplitude of the current sampling point is: When the frequency of the clock signal clk_s is f cl , the adjustment formula for the amplitude of the current sampling point is: Among them, val_data′ is the original amplitude of the current sampling point. The second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is reset; the comparator compares the output count value of the counter with the adjusted signal amplitude at each rising edge of the clock signal clk_m, if the count value is less than the adjusted signal amplitude, the comparator output is 1; if the count value is greater than or equal to the adjusted signal amplitude, the comparator output is 0. The inverter inverts one of the output signals of the comparator so that one UPWM generator outputs two differential UPWM signals.
为了提高功放系统的输出保真度,本发明第一Sigma-Delta调制器和第二Sigma-Delta调制器均为8阶前馈内插式Sigma-Delta调制器,第一Sigma-Delta调制器和第二Sigma-Delta调制器把24位高精度输入信号转换为7位低精度信号以使第一UPWM发生器和第二UPWM发生器输出64级后边沿UPWM信号。由于附图3所示的免滤波脉冲宽度调制器含有两个UPWM发生器,其输出的四路UPWM信号正好分别驱动H桥式功率级的四个输入端,使功放负载两端形成三个电压等级,从而使功放在效率方面降低了对LC模拟低通滤波器的依赖,而由于每路UPWM信号都具有三个采样频率,使功放负载两端信号在采样频率及其谐波处的能量扩散到周边频带内,从而达到了降低功放EMI的目的。In order to improve the output fidelity of the power amplifier system, the first Sigma-Delta modulator and the second Sigma-Delta modulator of the present invention are both 8th order feedforward interpolation Sigma-Delta modulators, and the first Sigma-Delta modulator and the second Sigma-Delta modulator convert the 24-bit high-precision input signal into a 7-bit low-precision signal so that the first UPWM generator and the second UPWM generator output 64-level trailing edge UPWM signals. Since the filter-free pulse width modulator shown in FIG3 contains two UPWM generators, the four-way UPWM signals outputted by the generator just drive the four input terminals of the H-bridge power stage respectively, so that three voltage levels are formed at both ends of the power amplifier load, thereby reducing the dependence of the power amplifier on the LC analog low-pass filter in terms of efficiency, and since each UPWM signal has three sampling frequencies, the energy of the signal at both ends of the power amplifier load at the sampling frequency and its harmonics is diffused into the surrounding frequency band, thereby achieving the purpose of reducing the EMI of the power amplifier.
本发明利用现场可编程门阵列(Field-Programmable Gate Array,FPGA)对基于本发明所述扩频调制方法的免滤波脉冲宽度调制器进行实现,并搭建了如附图9所示的测试系统以验证本发明的有益效果。由附图9可见,数字音频测试信号源产生Sony/Philips数字接口格式(Sony/Philips Digital Interface Format,S/PDIF)、采样频率为48kHz的数字音频输入信号,数字音频接收器把该输入信号处理为I2S格式的数据,FPGA实现的基于本发明所提扩频调制方法的免滤波脉冲宽度调制器对该I2S格式的数据进行处理并输出四路后边沿二级UPWM信号,该四路后边沿二级UPWM信号输入到USB模块处理成对应的后边沿三级UPWM信号,然后USB模块把该后边沿三级UPWM信号传输到计算机中进行频谱分析。The present invention uses a field programmable gate array (FPGA) to implement a filter-free pulse width modulator based on the spread spectrum modulation method of the present invention, and builds a test system as shown in Figure 9 to verify the beneficial effects of the present invention. As shown in Figure 9, the digital audio test signal source generates a digital audio input signal in Sony/Philips Digital Interface Format (S/PDIF) with a sampling frequency of 48kHz, and the digital audio receiver processes the input signal into data in I 2 S format. The filter-free pulse width modulator based on the spread spectrum modulation method of the present invention implemented by FPGA processes the data in I 2 S format and outputs four-way rear edge secondary UPWM signals, which are input into a USB module to be processed into corresponding rear edge tertiary UPWM signals, and then the USB module transmits the rear edge tertiary UPWM signals to a computer for spectrum analysis.
在测试信号为幅度为0dBFS、频率为6.6kHz、精度为24-bit、采样频率为48kHz的单频正弦数字信号的情况下,经过不带扩频调制功能的免滤波脉冲宽度调制器(后边沿UPWM发生器输出的二级后边沿UPWM信号的PRF恒定为384kHz)输出的三级UPWM信号的基带频谱如附图10所示;经过基于本发明所提扩频调制方法的免滤波脉冲宽度调制器输出的三级UPWM信号的基带频谱如附图11所示;经过不带扩频调制功能的免滤波脉冲宽度调制器输出的三级UPWM信号的高频频谱如附图12所示;经过基于本发明所提扩频调制方法的免滤波脉冲宽度调制器输出的三级UPWM信号的高频频谱如附图13所示。When the test signal is a single-frequency sinusoidal digital signal with an amplitude of 0 dBFS, a frequency of 6.6 kHz, an accuracy of 24-bit, and a sampling frequency of 48 kHz, the baseband spectrum of the three-level UPWM signal output by the filter-free pulse width modulator without spread spectrum modulation function (the PRF of the secondary trailing edge UPWM signal output by the trailing edge UPWM generator is constant at 384 kHz) is shown in FIG10; the baseband spectrum of the three-level UPWM signal output by the filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention is shown in FIG11; the high-frequency spectrum of the three-level UPWM signal output by the filter-free pulse width modulator without spread spectrum modulation function is shown in FIG12; the high-frequency spectrum of the three-level UPWM signal output by the filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention is shown in FIG13.
由附图10和附图11可知,当使用本发明所提扩频调制方法时,系统输出的三级UPWM信号频谱在三次输入信号谐波处有更低的幅度,且系统的THD为0.009%,小于不带扩频调制功能的系统输出的三级UPWM信号的THD(0.094%)。由附图12和附图13可知,当使用本发明所提扩频调制方法时,系统输出的三级UPWM信号频谱在带外的峰值幅度为-28.25dBFS,而当系统没有使用扩频调制方法时,系统输出的三级UPWM信号频谱在带外的峰值幅度为-10.5dBFS。相比不带扩频调制功能的系统,基于本发明所提扩频调制方法的系统输出的三级UPWM信号带外频谱峰值幅度降低了17.75dB。由此可知,本发明所提供的扩频调制方法能很好的对免滤波数字D类音频功放输出UPWM信号高频成分上的能量尖峰进行降幅处理,同时使功放的输出THD降低,在降低功放EMI的同时减少了UPWM引入的失真。As shown in Figures 10 and 11, when the spread spectrum modulation method proposed in the present invention is used, the three-level UPWM signal spectrum output by the system has a lower amplitude at the third harmonic of the input signal, and the THD of the system is 0.009%, which is less than the THD (0.094%) of the three-level UPWM signal output by the system without the spread spectrum modulation function. As shown in Figures 12 and 13, when the spread spectrum modulation method proposed in the present invention is used, the peak amplitude of the three-level UPWM signal spectrum output by the system is -28.25dBFS out of the band, while when the system does not use the spread spectrum modulation method, the peak amplitude of the three-level UPWM signal spectrum output by the system is -10.5dBFS out of the band. Compared with the system without the spread spectrum modulation function, the peak amplitude of the three-level UPWM signal out of the band spectrum output by the system based on the spread spectrum modulation method proposed in the present invention is reduced by 17.75dB. It can be seen that the spread spectrum modulation method provided by the present invention can effectively reduce the energy peak on the high-frequency component of the UPWM signal output by the filter-free digital Class D audio amplifier, while reducing the output THD of the amplifier, thereby reducing the distortion introduced by UPWM while reducing the EMI of the amplifier.
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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