CN110957983B - Three-frequency pseudo-random variable spread spectrum modulation method and filter-free pulse width modulator constructed by same - Google Patents

Abstract

The invention provides a three-frequency pseudo-random variable spread spectrum modulation method and a filtering-free pulse width modulator constructed by the method, wherein the method firstly utilizes a frequency synthesis technology to determine three sampling frequencies; then after the input audio signal is oversampled, the audio signal is sampled by a variable-multiple decimator, a digital signal with the three sampling frequencies is generated, a synchronous clock signal clk_s is generated at the same time, the digital signal is pre-corrected by a correction module, the UPWM signal generated after the digital signal passes through a trailing edge UPWM generator is similar to the NPWM signal in time domain, and finally the trailing edge UPWM generator generates the UPWM signal with the three pulse repetition frequencies; meanwhile, a corresponding filter-free pulse width modulator is designed based on the spread spectrum modulation method. The invention can obviously reduce the amplitude of high-frequency components of UPWM signals output by the power amplifier, thereby reducing EMI and leading the power amplifier to have lower THD.

Description

A three-frequency pseudo-random variable spread spectrum modulation method and a filter-free pulse width modulator constructed using this method

Technical Field

The invention relates to the field of filter-free digital class D audio power amplifiers, and in particular to a three-frequency pseudo-random variable spread spectrum modulation method for filter-free digital class D audio power amplifiers.

Background Art

Digital Class D audio amplifiers are widely used in today's consumer electronic products because of their many advantages such as high power efficiency, convenient interface with digital audio sources, and small size. The structural schematic diagram of a traditional digital Class D audio amplifier is shown in Figure 1, including a pulse width modulator, a power stage, and an LC analog low-pass filter connected in sequence. In a traditional digital Class D audio amplifier, the digital audio signal input to the amplifier is first modulated into a pulse width modulation (PWM) signal by a pulse width modulator, then amplified by a high-power transistor of the power stage, and finally driven to produce sound after filtering out high-frequency components through an inductor capacitor (LC) analog low-pass filter. Since the LC analog low-pass filter occupies about 75% of the volume of the entire amplifier system and consumes about 30% of the cost, it greatly increases the volume and cost of the amplifier system, which does not conform to the development trend of miniaturization and portability of today's audio-visual products. Therefore, filter-free digital Class D audio amplifiers have emerged and become a research hotspot.

The structural diagram of the filter-free digital Class D audio power amplifier is shown in Figure 2, which is mainly composed of a filter-free pulse width modulator and an H-bridge power stage. The filter-free pulse width modulator is mainly composed of an interpolation filter, an inversion module, a Sigma-Delta modulator and a uniform-sampling pulse width modulation (UPWM) generator. It uses oversampling technology, quantization noise shaping technology and UPWM technology to convert the digital audio signal into four-way UPWM signals while basically keeping the input signal baseband information unchanged. The four-way UPWM signals drive the H-bridge power stage and form a three-level UPWM signal on the speaker load. Since the three-level UPWM makes the voltage across the power amplifier load equal to zero volts for most of the time in each switching cycle, the current flowing through the load is greatly reduced, so that the power amplifier reduces its dependence on the LC analog low-pass filter in terms of efficiency. However, the output signal of the filter-free digital Class D audio amplifier has high energy at the pulse repetition frequency (PRF) and its harmonics. These high-frequency component energies will cause the output signal of the amplifier to generate serious electromagnetic interference (EMI). Therefore, in order to further improve the practicality of the filter-free digital Class D audio amplifier, special methods are needed to reduce the high-frequency energy peaks of the amplifier output signal, thereby reducing the EMI of the amplifier. The EMI suppression methods of Class D audio amplifiers are mainly divided into two categories: (1) suppression from the source, such as using soft switching technology, spread spectrum modulation technology, etc.; (2) suppression from the transmission path, such as board-level system layout and wiring optimization design, using shielding technology, etc. Since spread spectrum modulation technology is relatively simple to implement and easy to control, it has become the main method to solve the EMI problem of Class D audio amplifiers.

The main spread spectrum modulation methods for class D audio amplifiers that have been published include: low-power frequency modulation method (Yeh M L, Liou W R, Hsieh H P, et al. An electromagnetic interference (EMI) reduced high-efficiency switching power amplifier [J]. IEEE Transactions on Power Electronics, 2010, 25 (3): 710-718.), construction of "PWM Chopping" module method (Balmelli P, Khoury J M, Viegas E, et al. A low-EMI 3-W audio class-D amplifier compatible with AM/FM radio [J]. IEEE Journal of Solid-State Circuits, 2013, 48 (8): 1771-1782.), random winding pulse position modulation method (Adrian V, Keer C, Gwee B H, et al. A randomized modulation scheme for filterless digital class D audio amplifiers [C]. Proceedings of the 2014 IEEE International Symposium on Circuits and Systems. IEEE, 2014: 774-777.), multi-frequency pulse modulation method (Karaca T, Auer M. Digital pulse-width modulator with spread-spectrum emission reduction. e&i Elektrotechnik und Informationstechnik, 2018, 135(1): 48-53.), etc. The low-power frequency modulation method changes the PRF of the power amplifier PWM signal in real time by constructing an ultra-low power spread spectrum clock generator, which reduces the EMI of the power amplifier while also maintaining the high efficiency of the power amplifier. However, this method requires analog circuit implementation or analog input signals to participate in modulation, so it is only suitable for analog Class D audio amplifiers. The "PWM Chopping" module method uses the noise shaping function of the zero-input Sigma-Delta modulator to control the output PWM signal frame by frame, so that the common-mode high-frequency spikes at both ends of the power amplifier load are reduced, but the system requires a higher master clock frequency. The random winding pulse position modulation method realizes spectrum spread by randomizing the position of each pulse of the UPWM signal in the current switching cycle. Since this method is based on the two-level PWM technology, although it can make the power amplifier have lower EMI, it greatly reduces the efficiency. The multi-frequency pulse modulation method controls the PRF of the output signal of the UPWM generator through two reversible counters to achieve the purpose of spectrum spread. Although this method can reduce the high-frequency maximum amplitude of the power amplifier output signal spectrum to a certain extent, it will cause the power amplifier output signal to produce intermodulation distortion in the baseband.

Summary of the invention

In view of the shortcomings of the existing spread spectrum modulation method, the present invention provides a spread spectrum modulation method for a filter-free digital Class D audio power amplifier. The method is easy to implement and can significantly reduce the high-frequency component amplitude of the UPWM signal output by the power amplifier while reducing the system THD, thereby achieving the purpose of reducing EMI. The implementation steps of the method are:

Step 1: Use an interpolation filter to increase the sampling frequency f _o of the power amplifier input signal by N times to the sampling frequency f _s , and determine the intermediate frequency f _c of the three required sampling frequencies according to the sampling frequency f _s , where f _c = f _s /q, q is an integer less than N;

N_s＝p+v，f_cl为三者中最大的采样频率，

N₁＝p-v，v∈[1，p-1]且v为整数，

f_{clk_m}为主时钟信号clk m的频率，m为UPWM发生器的级数；Step 2: Using frequency synthesis technology, determine the other two sampling frequencies _fcs and _fcl according to the main clock signal clk_m of the power amplifier system and the determined intermediate frequency _fc , where _fcs is the smallest sampling frequency among the three.

N _s = p + v, f _cl is the largest sampling frequency among the three,

N ₁ = pv, v∈[1, p-1] and v is an integer,

f _{clk_m} is the frequency of the main clock signal clk m, where m is the number of stages of the UPWM generator;

Step 3: Construct a variable multiple extractor, construct a finite state machine and a pseudo-random number generator composed of a 2n-level linear feedback shift register in the variable multiple extractor, and the finite state machine uses the n-bit pseudo-random number rand_num generated by the pseudo-random number generator to obtain the final state that uniquely corresponds to it; the initial state of the finite state machine is S ₀ , and a variable K is allowed to take values from the highest bit to the lowest bit of the n-bit pseudo-random number in sequence. The finite state machine determines the next state according to the K value and the current state until K takes the lowest bit of the pseudo-random number and outputs the final state. The finite state machine has three final states, namely: S ₀ , S ₁ , and S ₂ ;

相同时，时钟信号clk_s置于低电平，当计数器的值cou_val与当前阈值thr_val相同时，时钟信号clk_s再次置于高电平，同时计数器清零，[]_取整为舍去小数位取整；时钟生成器根据阈值thr_val、计数器的值cou_val和时钟信号clk_bas生成一个新的具有三个频率的时钟信号clk_s；Step 4: construct a threshold generator, a first counter and a clock generator in the variable multiple extractor; the threshold generator determines a corresponding threshold thr_val according to the final state output by the above finite state machine, and the threshold is the extraction multiple of the current variable multiple extractor, and there are three values in total, namely: _ts , _tc , _t1 ; the first counter is an add-one counter, which counts the rising edges of the clock signal clk_bas, and the clock signal clk_bas is obtained by dividing the main clock signal clk_m, and its frequency _{fclk_bas} = _fs . When the count value is zero, the output clock signal clk_s of the clock generator is set to a high level. When the value of the counter cou_val is equal to the current threshold

When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a low level. When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a high level again, and the counter is cleared at the same time. [] _{is rounded} to the integer without decimal places. The clock generator generates a new clock signal clk_s with three frequencies according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas.

Step 5: Build a data processing module in the variable multiple extractor. When the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, thereby processing the single sampling frequency signal data output by the interpolation filter into a signal data_t with three sampling frequencies;

Step 6: Construct a correction module. When the rising edge of the clock signal clk_s is detected, the correction algorithm is used to recalculate and assign the amplitude of the current sampling point in the input signal data_t, and a new signal data_t′ is output, so that the UPWM signal obtained after passing through the trailing edge UPWM generator is similar to the natural sampling pulse width modulation (NPWM) signal in the time domain;

Step 7: construct an m-level trailing edge UPWM generator, and construct a second counter in the m-level trailing edge UPWM generator. The counter is also an add-one counter, which counts the rising edge of the clock signal clk_m. When the rising edge of the clock signal clk_s is detected, the counter is reset;

Step 8: construct an amplitude adjustment module in the m-level trailing edge UPWM generator. Since the frequency of the clock signal clk_s input to the trailing edge UPWM generator and the sampling frequency of the digital audio signal data_t′ input to the trailing edge UPWM generator are synchronously variable, in order to keep the duty cycle of the trailing edge UPWM signal output by the trailing edge UPWM generator unchanged compared to when the spectrum is not spread, the module judges the frequency of the current clk_s according to the current thr_val value based on the input clock signal clk_s and the threshold signal thr_val, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t′ input to the trailing edge UPWM generator in real time and outputting a new signal data_t″;

Step 9: A comparator is constructed in the m-level trailing edge UPWM generator. The comparator determines whether the output value coun of the second counter in step 7 is greater than the threshold value y at the rising edge of each clock signal clk_m; if so, the comparator outputs 0, otherwise the output is 1, thereby outputting a trailing edge secondary UPWM signal with three sampling frequencies; wherein the threshold value y is equal to the current sampling point amplitude of the amplitude adjustment module output signal data_t″.

In the step 3, the 2n-stage linear feedback shift register is composed of 2n D flip-flops and a plurality of gate circuits, and is controlled by a clock signal clk_r and a reset signal reset. The clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f _{clk_r} is greater than the maximum value f _c1 among the three sampling frequencies. After each clock cycle of clk_r, the output values of the last n D flip-flops of the 2n-stage linear feedback shift register form an n-bit pseudo-random number rand_num.

In the step three, the state determination rule of the finite state machine is: if the current state is S ₀ and the value of K is 0, the next state is S ₀ ; if the current state is S ₀ and the value of K is 1, the next state is S ₁ ; if the current state is S ₁ and the value of K is 0, the next state is S ₂ ; if the current state is S ₁ and the value of K is 1, the next state is S ₀ ; if the current state is S ₂ and the value of K is 0, the next state is S ₁ ; if the current state is S ₂ and the value of K is 1, the next state is S ₂ .

In step 4, the threshold generator generates the threshold thr_val according to the following rules: when the final state corresponding to the current pseudo-random number is _S0 , the threshold thr_val is _t1 ; when the final state corresponding to the current pseudo-random number is _S1 , the threshold thr_val is _tc ; when the final state corresponding to the current pseudo-random number is _S2 , the threshold thr_val is _ts .

In step 4, the generation rule of the clock signal clk_s is: when the current threshold thr_val is _t1 , the frequency of the clock signal clk_s in the current cycle is _fcs ; when the current threshold thr_val is _tc , the frequency of the clock signal clk_s in the current cycle is _fc ; when the current threshold thr_val is _ts , the frequency of the clock signal clk_s in the current cycle is _fc1 .

x₂＝0，

f₁和f₂分别为采样点F₁和F₂所对应的采样频率；对载波信号和采样点的幅值进行归一化处理，使其最小值为0，最大值为1，则在采样点F₂和F₃之间的锯齿波载波波形表达式为：

求该载波和由该三个采样点构造的二阶牛顿插值曲线的交点(伪自然采样点)幅值以代替当前采样点的幅值输入到后边沿UPWM发生器可使产生的后边沿UPWM信号在时域上近似后边沿NPWM信号，从而降低信号的谐波失真；该二阶牛顿插值曲线函数表达式为：in_p(x)＝λ₁+λ₂·(x-x₁)+λ₃·(x-x₁)·x，其中，λ₁＝in₁，

令F(x)＝in_p(x)-cw(x)＝0，设定x的初始值为

利用牛顿-拉夫逊迭代方法可求得F(x)的近似解

其中

in′_p(x)＝λ₂+λ₃·x+λ₃·(x-x₁)；最后，将x_b代入到载波波形表达式，求得伪自然采样点幅值

由in_b经过后边沿UPWM发生器产生的后边沿UPWM信号在时域上近似后边沿NPWM信号。In step 6, the correction algorithm used in the correction module is: assuming that _F1 ( _x1 , _in1 ), _F2 ( _x2 , _in2 ) and _F3 ( _x3 , _in3 ) are three adjacent sampling points of the input modulation signal, where _F2 is the current sampling point, _F1 is the previous sampling point, _F3 is the next sampling point, _in1 , _in2 and _in3 are the amplitudes of the three sampling points respectively,

x ₂ = 0,

_f1 and _f2 are the sampling frequencies corresponding to the sampling points _F1 and _F2 respectively; the amplitude of the carrier signal and the sampling point is normalized so that its minimum value is 0 and its maximum value is 1, then the sawtooth carrier waveform expression between the sampling points _F2 and _F3 is:

The amplitude of the intersection point (pseudo natural sampling point) between the carrier and the second-order Newton interpolation curve constructed by the three sampling points is calculated to replace the amplitude of the current sampling point and input into the trailing edge UPWM generator, so that the generated trailing edge UPWM signal can be approximated to the trailing edge NPWM signal in the time domain, thereby reducing the harmonic distortion of the signal; the function expression of the second-order Newton interpolation curve is: in _p (x) = λ ₁ +λ ₂ ·(xx ₁ )+λ ₃ ·(xx ₁ )·x, where λ ₁ =in ₁ ,

Let F(x) = in _p (x) - cw(x) = 0, and set the initial value of x to

The approximate solution of F(x) can be obtained by using the Newton-Raphson iterative method

in

in′ _p (x) = λ ₂ + λ ₃ ·x + λ ₃ ·(x ₁ ); Finally, substitute x _b into the carrier waveform expression to obtain the amplitude of the pseudo natural sampling point:

The trailing edge UPWM signal generated by in _b through the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain.

在当前阈值信号thr_val为t_c时，当前时钟信号clk_s的频率为f_c，当前采样点幅值的调整公式为：

在当前阈值信号thr_val为t_s时，当前时钟信号clk_s的频率为f_c1，当前采样点幅值的调整公式为：

其中，val_data′为当前采样点原幅值。In step eight, the amplitude adjustment rule of the amplitude adjustment module is: when the current threshold signal thr_val is _t1 , the frequency of the current clock signal clk_s is _fcs , and the adjustment formula of the current sampling point amplitude is:

When the current threshold signal thr_val is t _c , the frequency of the current clock signal clk_s is f _c , and the adjustment formula of the current sampling point amplitude is:

When the current threshold signal thr_val is _ts , the frequency of the current clock signal clk_s is _fc1 , and the adjustment formula of the current sampling point amplitude is:

Among them, val_data′ is the original amplitude of the current sampling point.

The filter-free pulse width modulator constructed by the above-mentioned three-frequency pseudo-random variable spread spectrum modulation method includes an interpolation filter, a variable multiple extractor, an inversion module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first trailing edge UPWM generator and a second trailing edge UPWM generator; the digital audio input signal is connected to the interpolation filter, the interpolation filter is connected to the variable multiple extractor, the variable multiple extractor is respectively connected to the first correction module and the inversion module, and the inversion module is connected to the first correction module. The inverse module is connected to the second correction module, the first correction module is connected to the first Sigma-Delta modulator, the second correction module is connected to the second Sigma-Delta modulator, the first Sigma-Delta modulator is connected to the first rear edge UPWM generator, the second Sigma-Delta modulator is connected to the second rear edge UPWM generator, and the two rear edge UPWM signals output by the first rear edge UPWM generator and the two rear edge UPWM signals output by the second rear edge UPWM generator are both connected to the H-bridge power stage of the power amplifier.

The interpolation filter is a 32-fold interpolation filter, the first Sigma-Delta modulator and the second Sigma-Delta modulator are the same and are both 8th-order feedforward interpolation Sigma-Delta modulators, and the first Sigma-Delta modulator and the second Sigma-Delta modulator both convert a 24-bit high-precision input signal into a 7-bit low-precision signal with 65 quantization levels so that the first trailing edge UPWM generator and the second trailing edge UPWM generator output a 64-level trailing edge UPWM signal.

The variable multiple extractor includes a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine and a data processing module; the system main clock signal is connected to the variable multiple extractor; the clock signal clk_r is connected to the pseudo-random number generator and the finite state machine respectively, and the clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f _{clk_r} is greater than the maximum value f _cl among the three sampling frequencies , the pseudo-random number generator is connected to the finite state machine, the finite state machine is connected to the threshold generator, and the threshold generator determines a threshold thr_val corresponding to the final state output by the finite state machine; the clock signal clk_bas is respectively connected to the pseudo-random number generator, the finite state machine, the first counter and the clock generator, the first counter and the threshold generator are both connected to the clock generator, and the clock generator generates a new clock signal clk_s using frequency synthesis technology; the clock generator and the input signal data are both connected to the data processing module, and the data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, thereby outputting a digital audio signal data_t with three sampling frequencies.

The pseudo-random number generator is mainly composed of a 16-stage linear feedback shift register. By setting an initial state for the linear feedback shift register, the linear feedback shift register generates an 8-bit pseudo-random number and inputs it to the finite state machine every clk_r cycle; the finite state machine calculates the corresponding final state according to the current pseudo-random number and inputs it to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state.

The first counter counts the rising edges of the clock signal clk_bas. When the rising edge of clk_bas is detected, the value of the counter is increased by 1; when it is detected that the value of the counter is equal to the current threshold thr_val, the counter is cleared.

The first and second correction modules are the same, both of which use correction technology to recalculate the amplitude of each sampling point based on the threshold signal thr_val, clock signal clk_s and digital audio signal data_t with three sampling frequencies output by the variable multiple extractor, thereby outputting a new signal data_t′.

The first trailing edge UPWM generator is the same as the second trailing edge UPWM generator, and includes an amplitude adjustment module, a second counter, a comparator and an inversion module; the clock signal clk_s is respectively connected to the second counter and the amplitude adjustment module, the digital audio signal data_t′ is connected to the amplitude adjustment module, the clock signal clk_m is respectively connected to the second counter and the comparator, the amplitude adjustment module and the second counter are respectively connected to the comparator, one path of the comparator is directly output, and the other path is connected to the inversion module and then output; the amplitude adjustment module calculates and adjusts the amplitude of the current sampling point according to the adjustment rule; the second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared; the comparator compares the counter value with the adjusted signal amplitude, one path is directly output as the trailing edge UPWM signal, and the other path is inverted by the inversion module and outputs the trailing edge UPWM signal.

Compared with the prior art, the beneficial effects of the present invention are:

1. The present invention is based on a filter-free modulation architecture, a trailing edge UPWM technology and a pseudo-random spread spectrum modulation technology. By constructing a variable multiple decimator, the input audio signal is sampled into an audio signal with three sampling frequencies, and a clock signal synchronized with the digital audio signal is synthesized. Then, the amplitude of each sampling point is corrected by a correction module to reduce the baseband distortion introduced in the UPWM process. Thus, while reducing the high-frequency peak amplitude of the output UPWM signal, it can well ensure that less harmonic distortion is introduced, so as to achieve the purpose of reducing the EMI and THD of the power amplifier.

2. The method proposed in the present invention can be implemented by a fully digital circuit and can be conveniently applied to the existing filter-free digital Class D audio power amplifier system.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of the structure of a conventional digital Class D audio power amplifier;

FIG2 is a schematic diagram of the structure of a filter-free digital Class D audio power amplifier;

FIG3 is a schematic structural diagram of a filter-free pulse width modulator according to an embodiment of the present invention;

FIG4 is a schematic diagram of the structure of a variable multiple decimator according to the present invention;

FIG5 is a schematic diagram of the structure of a linear feedback shift register according to the present invention;

FIG6 is a state transition diagram of a finite state machine of the present invention;

FIG7 is a schematic diagram of a correction algorithm of the present invention;

FIG8 is a schematic diagram of the structure of a trailing edge UPWM generator of the present invention;

FIG9 is a schematic diagram of a test system of the present invention;

FIG10 is a baseband spectrum diagram of a trailing edge three-level UPWM signal output by the test system of FIG9 using a filter-free pulse width modulator without a spread spectrum modulation function;

11 is a baseband spectrum diagram of a trailing edge three-level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention;

FIG12 is a high frequency spectrum diagram of the trailing edge three-level UPWM signal output by the test system of FIG9 using a filter-free pulse width modulator without spread spectrum modulation function;

FIG. 13 is a high frequency spectrum diagram of the trailing edge three-level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

A three-frequency pseudo-random variable spread spectrum modulation method for a filter-free digital class D audio power amplifier, the steps of which are as follows.

Step 1: Use an interpolation filter to increase the sampling frequency f _o of the power amplifier input signal by N times to the sampling frequency f _s , and determine the intermediate frequency f _c of the three required sampling frequencies based on the sampling frequency f _s , where f _c = f _s /q, q is an integer less than N;

N_s＝p+v，f_c1为三者中最大的采样频率，

N₁＝p-v，v∈[1，p-1]且v为整数，

f_{clk_m}为主时钟信号clk_m的频率，m为UPWM发生器的级数；Step 2: _Use frequency synthesis technology to determine the other two sampling frequencies _fcs and _fc1 according to the main clock signal clk_m of the power amplifier system and the determined intermediate frequency fc, where _fcs is the smallest sampling frequency among the three.

_Ns = p+v, _fc1 is the largest sampling frequency among the three,

N ₁ = pv, v∈[1, p-1] and v is an integer,

f _{clk_m} is the frequency of the main clock signal clk_m, m is the number of stages of the UPWM generator;

Step 3: Construct a variable multiple extractor, in which a finite state machine and a pseudo-random number generator consisting of a 2n-level linear feedback shift register are constructed. The finite state machine uses the n-bit pseudo-random number rand_num generated by the pseudo-random number generator to obtain the final state that is uniquely corresponding to it; the 2n-level linear feedback shift register is composed of 2n D flip-flops and several gate circuits, and is controlled by the clock signal clk_r and the reset signal reset. The clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f _{clk_r} is greater than the maximum value f _c1 of the three sampling frequencies. After each clock cycle of clk_r, the output values of the last n D flip-flops of the 2n-level linear feedback shift register form the n-bit pseudo-random number rand_num; the initial state of the finite state machine is S ₀ , let a variable K take values from the highest bit to the lowest bit of the n-bit pseudo-random number in sequence, the finite state machine determines the next state according to the K value and the current state, until K takes the lowest bit of the pseudo-random number, and outputs the final state. The finite state machine has three final states, namely: S ₀ , S ₁ , S ₂ ; the state determination rule of the finite state machine is: if the current state is S ₀ , K value is 0, then the next state is S ₀ ; if the current state is S ₀ , K value is 1, then the next state is S ₁ ; if the current state is S ₁ , K value is 0, then the next state is S ₂ ; if the current state is S ₁ , K value is 1, then the next state is S ₀ ; if the current state is S ₂ , K value is 0, then the next state is S ₁ ; if the current state is S ₂ , K value is 1, then the next state is S ₂ ;

相同时，时钟信号clk_s置于低电平，当计数器的值cou_val与当前阈值thr_val相同时，时钟信号clk_s再次置于高电平，同时计数器清零，[]_取整为舍去小数位取整；时钟生成器根据阈值thr_val、计数器的值cou_val和时钟信号clk_bas生成一个新的具有三个频率的时钟信号clk_s(其频率分别为f_cs、f_c和f_c1)，其中时钟信号clk_bas由主时钟信号clk_m分频所得，其频率f_{clk_bas}＝f_s；时钟信号clk_s的生成规则为：在当前阈值thr_val为t₁时，时钟信号clk_s在当前周期的频率为f_cs；在当前阈值thr_val为t_c时，时钟信号clk_s在当前周期的频率为f_c；在当前阈值thr_val为t_s时，时钟信号clk_s在当前周期的频率为f_cl；Step 4: construct a threshold generator, a first counter and a clock generator in the variable multiple extractor; the threshold generator determines a corresponding threshold thr_val according to the final state output by the above finite state machine, and the threshold is the extraction multiple of the current variable multiple extractor, and there are three values in total, namely: _ts , tc, _t1 ; the determination rule of the threshold thr_val is: when the final state corresponding to the current pseudo-random number is _S0 , the threshold thr_val is _t1 ; when the final state corresponding to the current pseudo-random number is _S1 , the threshold thr_val is _tc ; when the final state corresponding to the current pseudo-random number is _S2 , the threshold thr_val is _{ts ;} the first counter is an add-one counter, which counts the rising edges of the clock signal clk_bas. When the count value is zero, the clock signal clk_s is set to a high level. When the value of the counter cou_val is equal to the current threshold

When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s _{is set to a low level. When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a high level again, and the counter is cleared at the same time. [] is rounded} to the integer without a decimal place. The clock generator generates a new clock signal clk_s with three frequencies (whose frequencies are f _cs , f _c and f _c1 respectively) according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas, wherein the clock signal clk_bas is obtained by dividing the main clock signal clk_m, and its frequency f _{clk_bas} = f _s . The generation rule of the clock signal clk_s is: when the current threshold thr_val is t ₁ , the frequency of the clock signal clk_s in the current cycle is f _cs ; when the current threshold thr_val is t _c , the frequency of the clock signal clk_s in the current cycle is f _c ; when the current threshold thr_val is t _s , the frequency of the clock signal clk_s in the current cycle is f _cl ;

Step 5: Build a data processing module in the variable multiple extractor. When the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, thereby processing the single sampling frequency signal data output by the interpolation filter into a signal data_t with three sampling frequencies.

x₂＝0，

f₁和f₂分别为采样点F₁和F₂所对应的采样频率；对载波信号和采样点的幅值进行归一化处理，使其最小值为0，最大值为1，则在采样点F₂和F₃之间的载波波形表达式为：

求该载波和由该三个采样点构造的二阶牛顿插值曲线的交点(伪自然采样点)幅值以代替当前采样点的幅值输入到后边沿UPWM发生器可使产生的后边沿UPWM信号在时域上近似后边沿NPWM信号，从而降低信号的谐波失真；该二阶牛顿插值曲线函数表达式为：in_p(x)＝λ₁+λ₂·(x-x₁)+λ₃·(x-x₁)·x，其中，λ₁＝in₁，

令F(x)＝in_p(x)-cw(x)＝0，设定x的初始值为

利用牛顿-拉夫逊迭代方法可求得F(x)的近似解

其中

in′_p(x)＝λ₂+λ₃·x+λ₃·(x-x₁)；最后，将x_b代入到载波波形表达式，求得伪自然采样点幅值

由in_b经过后边沿UPWM发生器产生的后边沿UPWM信号在时域上近似后边沿NPWM信号；Step 6: Construct a correction module. When the rising edge of the clock signal clk_s is detected, the amplitude of the current sampling point in the input signal data_t is recalculated and assigned using the correction algorithm, and a new signal data_t′ is output, so that the U PWM signal obtained after passing through the UPWM generator is similar to the NPWM signal in the time domain; the correction algorithm used in the correction module is: assuming that F ₁ (x ₁ , in ₁ ), F ₂ (x ₂ , in ₂ ) and F ₃ (x ₃ , in ₃ ) are three adjacent sampling points of the input modulation signal, where F ₂ is the current sampling point, F ₁ is the previous sampling point, F ₃ is the next sampling point, in ₁ , in ₂ and in ₃ are the amplitudes of the three sampling points respectively,

x ₂ = 0,

_f1 and _f2 are the sampling frequencies corresponding to the sampling points _F1 and _F2 respectively; the amplitude of the carrier signal and the sampling point are normalized so that the minimum value is 0 and the maximum value is 1, then the carrier waveform expression between the sampling points _F2 and _F3 is:

The amplitude of the intersection point (pseudo natural sampling point) between the carrier and the second-order Newton interpolation curve constructed by the three sampling points is calculated to replace the amplitude of the current sampling point and input into the trailing edge UPWM generator, so that the generated trailing edge UPWM signal can be approximated to the trailing edge NPWM signal in the time domain, thereby reducing the harmonic distortion of the signal; the function expression of the second-order Newton interpolation curve is: in _p (x) = λ ₁ +λ ₂ ·(xx ₁ )+λ ₃ ·(xx ₁ )·x, where λ ₁ =in ₁ ,

Let F(x) = in _p (x) - cw(x) = 0, and set the initial value of x to

The approximate solution of F(x) can be obtained by using the Newton-Raphson iterative method

in

in′ _p (x) = λ ₂ + λ ₃ ·x + λ ₃ ·(x ₁ ); Finally, substitute x _b into the carrier waveform expression to obtain the amplitude of the pseudo natural sampling point:

The trailing edge UPWM signal generated by in _b through the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain;

Step 7: construct an m-level trailing edge UPWM generator, and construct a second counter in the m-level trailing edge UPWM generator. The counter is also an add-one counter, which counts the rising edge of the clock signal clk_m. When the rising edge of the clock signal clk_s is detected, the counter is cleared.

在当前阈值信号thr_val为t_c时，当前时钟信号clk_s的频率为f_c，当前采样点幅值的调整公式为：

在当前阈值信号thr_val为t_s时，当前时钟信号clk_s的频率为f_c1，当前采样点幅值的调整公式为：

其中，val_data′为当前采样点原幅值。Step 8: construct an amplitude adjustment module in the m-level trailing edge UPWM generator. Since the frequency of the clock signal clk_s input to the trailing edge UPWM generator and the sampling frequency of the digital audio signal data t′ input to the trailing edge UPWM generator are synchronously variable, in order to keep the duty cycle of the trailing edge UPWM signal output by the trailing edge UPWM generator unchanged compared to when the spectrum is not spread, the module judges the frequency of the current clk_s according to the input clock signal clk_s and the threshold signal thr_val by the current thr_val value, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t′ input to the trailing edge UPWM generator in real time, and outputs a new signal data_t″; the amplitude adjustment rule of the amplitude adjustment module is: when the current threshold signal thr_val is t ₁ , the frequency of the current clock signal clk_s is f _cs , and the adjustment formula of the current sampling point amplitude is:

When the current threshold signal thr_val is t _c , the frequency of the current clock signal clk_s is f _c , and the adjustment formula of the current sampling point amplitude is:

When the current threshold signal thr_val is _ts , the frequency of the current clock signal clk_s is _fc1 , and the adjustment formula of the current sampling point amplitude is:

Among them, val_data′ is the original amplitude of the current sampling point.

Step 9: A comparator is constructed in the m-level trailing edge UPWM generator. The comparator determines whether the output value coun of the counter in step 7 is greater than the threshold value y at the rising edge of each clock signal clk_m; if so, the comparator outputs 0, otherwise the output is 1, thereby outputting a trailing edge secondary UPWM signal with three sampling frequencies; wherein the threshold value y is equal to the current sampling point amplitude of the output signal data_t″ of the amplitude adjustment module. Each UPWM generator inside the filter-free digital class D audio amplifier outputs two differential signals, and the two UPWM generators output a total of four UPWM signals to drive the H-bridge power stage, so that three voltage levels are formed at both ends of the power amplifier load, thereby reducing the power amplifier's dependence on the LC analog low-pass filter in terms of efficiency. Since the PRF of each UPWM signal is variable, the energy of the signal at both ends of the power amplifier load at the PRF and its harmonics is diffused into the surrounding frequency band, thereby achieving the purpose of reducing the EMI of the power amplifier.

A filter-free pulse width modulator is constructed by using the above three-frequency pseudo-random variable spread spectrum modulation method, and its structural schematic diagram is shown in Figure 3. The filter-free pulse width modulator comprises an interpolation filter, a variable multiple extractor, an inversion module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first rear edge UPWM generator and a second rear edge UPWM generator; the digital audio signal is connected to the interpolation filter, the interpolation filter is connected to the variable multiple extractor, the variable multiple extractor is respectively connected to the first correction module and the inversion module, the inversion module is connected to the second correction module, the first correction module is connected to the first Sigma-Delta modulator, the second correction module is connected to the second Sigma-Delta modulator, the first Sigma-Delta modulator is connected to the first rear edge UPWM generator, the second Sigma-Delta modulator is connected to the second rear edge UPWM generator, and the two rear edge UPWM signals output by the first rear edge UPWM generator and the two rear edge UPWM signals output by the second rear edge UPWM generator are both connected to the H-bridge power stage of the power amplifier.

In FIG3, f _o =48kHz is the sampling frequency of the audio input signal, and the frequency f _{clk_m} of the master clock clk_m used by the filter-free pulse width modulator is 98.304MHz. The interpolation filter designed by the present invention is an interpolation filter that realizes 32 times oversampling, and uniformly increases the sampling frequency of the input signal 48kHz to f _s =1536kHz, and the sampling frequency f _s is also the frequency of the clock signal clk_bas.

N_s＝p+v＝5，N₁＝p-v＝3，

时钟信号clk_r分别与伪随机数生成器和有限状态机相连接，该时钟信号clk_r由主时钟信号clk_m分频所得，其频率f_{clk_r}大于三个采样频率中最大值f_cl，在本系统中，时钟信号clk_r的频率f_{clk_r}为768kHz。16级线性反馈移位寄存器构成的8位伪随机数生成器与有限状态机相连接。该16级线性反馈移位寄存器结构示意图如附图5所示，其由16个D触发器、3个4输入或门、1个3输入或门、1个4输入或非门、4个异或门组成。该16级线性反馈移位寄存器受时钟信号clk_r和复位信号reset控制，每经过一个clk_r的时钟周期，该16级线性反馈移位寄存器中后8个D触发器的输出值组成8位伪随机数rand_num。该有限状态机的状态转移图如附图6所示，有限状态机初始状态为S₀，让一位变量K从该8位伪随机数最高位到最低位依次取值，有限状态机根据K值和当前状态确定下一个状态，直到K取到该伪随机数最低位，输出最终状态，该有限状态机共有三种最终状态，分别为：S₀、S₁、S₂。由图6可知，该有限状态机状态判定规则为：若当前状态为S₀，K取值为0，则下一个状态为S₀；若当前状态为S₀时，K取值为1，则下一个状态为S₁；若当前状态为S₁，K取值为0，则下一个状态为S₂；若当前状态为S₁，K取值为1，则下一个状态为S₀；若当前状态为S₂，K取值为0，则下一个状态为S₁；若当前状态为S₂，K取值为1，则下一个状态为S₂。有限状态机和阈值生成器相连接，阈值生成器根据有限状态机输出的最终状态确定一个与之对应的阈值thr_val。阈值生成器生成阈值thr_val的规则为：在当前伪随机数对应的最终状态为S₀时，阈值thr_val为t₁＝f_s/f_cs＝5；在当前伪随机数对应的最终状态为S₁时，阈值thr_val为t_c＝f_s/f_c＝4；在当前伪随机数对应的最终状态为S₂时，阈值thr_val为t_s＝f_s/f_cl＝3。第一计数器对时钟信号clk_bas的上升沿进行加1计数，计数值为零时，时钟生成器的输出时钟信号clk_s置于高电平，当计数器的值cou_val与当前阈值

相同时，时钟信号clk_s置于低电平，当计数器的值cou_val与当前阈值thr_val相同时，时钟信号clk_s再次置于高电平，同时计数器清零，[]_取整为舍去小数位取整。时钟生成器根据阈值thr_val、计数器的值cou_val和时钟信号clk_bas生成一个新的具有三个频率(307.2kHz、384kHz和512kHz)的时钟信号clk_s。时钟生成器和输入信号data均与数据处理模块相连接，数据处理模块根据时钟生成器产生的时钟信号clk_s对输入的数字音频信号data进行抽取处理，从而输出具有三个采样频率(307.2kHz、384kHz和512kHz)的数字音频信号data_t。In order to achieve the purpose of spectrum spread, the structural schematic diagram of the variable multiple extractor designed by the present invention is shown in Figure 4. The variable multiple extractor includes a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine and a data processing module. The clock signal clk_bas is connected to the pseudo-random number generator, the finite state machine, the first counter and the clock generator respectively. The first counter and the threshold generator are both connected to the clock generator. The clock generator uses frequency synthesis technology to generate a new clock signal clk_s with three frequencies. In this system, let q=4, v=1, and the number of stages of the trailing edge UPWM generator m=64, then _fc = _fs /q=384kHz,

N _s =p+v=5, N ₁ =pv=3,

The clock signal clk_r is connected to the pseudo-random number generator and the finite state machine respectively. The clock signal clk_r is obtained by dividing the main clock signal clk_m, and its frequency f _{clk_r} is greater than the maximum value f _cl among the three sampling frequencies. In this system, the frequency f _{clk_r} of the clock signal clk_r is 768kHz. The 8-bit pseudo-random number generator composed of a 16-level linear feedback shift register is connected to the finite state machine. The structural schematic diagram of the 16-level linear feedback shift register is shown in Figure 5, which consists of 16 D flip-flops, 3 4-input OR gates, 1 3-input OR gate, 1 4-input NOR gate, and 4 XOR gates. The 16-level linear feedback shift register is controlled by the clock signal clk_r and the reset signal reset. After each clock cycle of clk_r, the output values of the last 8 D flip-flops in the 16-level linear feedback shift register form an 8-bit pseudo-random number rand_num. The state transition diagram of the finite state machine is shown in Figure 6. The initial state of the finite state machine is S ₀ . Let a variable K take values from the highest bit to the lowest bit of the 8-bit pseudo-random number in sequence. The finite state machine determines the next state according to the K value and the current state until K takes the lowest bit of the pseudo-random number and outputs the final state. The finite state machine has three final states, namely: S ₀ , S ₁ , and S ₂ . As shown in Figure 6, the state judgment rule of the finite state machine is: if the current state is S ₀ and K is 0, the next state is S ₀ ; if the current state is S ₀ and K is 1, the next state is S ₁ ; if the current state is S ₁ and K is 0, the next state is S ₂ ; if the current state is S ₁ and K is 1, the next state is S ₀ ; if the current state is S ₂ and K is 0, the next state is S ₁ ; if the current state is S ₂ and K is 1, the next state is S _2. The finite state machine is connected to the threshold generator, and the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine. The threshold generator generates the threshold thr_val according to the following rule: when the final state corresponding to the current pseudo-random number is S ₀ , the threshold thr_val is t ₁ = f _s / f _cs = 5; when the final state corresponding to the current pseudo-random number is S ₁ , the threshold thr_val is t _c = f _s / f _c = 4; when the final state corresponding to the current pseudo-random number is S ₂ , the threshold thr_val is t _s = f _s / f _cl = 3. The first counter counts the rising edge of the clock signal clk_bas by 1. When the count value is zero, the output clock signal clk_s of the clock generator is set to a high level. When the value of the counter cou_val is equal to the current threshold

When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s _{is set to a low level. When the counter value cou_val is the same as the current threshold thr_val, the clock signal clk_s is set to a high level again, and the counter is cleared at the same time. [] is rounded} to the nearest integer. The clock generator generates a new clock signal clk_s with three frequencies (307.2kHz, 384kHz and 512kHz) according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas. The clock generator and the input signal data are both connected to the data processing module. The data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, thereby outputting a digital audio signal data_t with three sampling frequencies (307.2kHz, 384kHz and 512kHz).

In order to eliminate the harmonic distortion of the power amplifier output signal, the correction module corrects the digital audio signal data_t to data_t′. The schematic diagram of the correction algorithm used in the correction module is shown in Figure 7. The algorithm uses the characteristic of NPWM without harmonic distortion to correct the modulation signal before UPWM, so that the UPWM signal finally output by the UPWM generator is similar to the NPWM signal in the time domain to eliminate the harmonic distortion of the output signal. According to the current sampling point, the previous sampling point and the next sampling point of the modulation signal, a second-order Newton interpolation curve function expression is established, and a carrier waveform expression is established at the same time. The Newton-Raphson iteration method is used to solve the intersection amplitude of the carrier waveform and the interpolation curve. The rear edge UPWM waveform obtained by the rear edge UPWM generator at this point is similar to the rear edge NPWM waveform in the time domain.

当时钟信号clk_s的频率为f_c时，当前采样点幅值的调整公式为：

当时钟信号clk_s的频率为f_cl时，当前采样点幅值的调整公式为：

其中，val_data′为当前采样点原幅值。所述第二计数器对时钟信号clk_m的上升沿进行计数，当检测到时钟信号clk_s的上升沿，该计数器清零；所述比较器在每个时钟信号clk_m的上升沿对计数器的输出计数值和调整后的信号幅值进行比较，若计数值小于调整后的信号幅值，比较器输出为1；若计数值大于等于调整后的信号幅值，比较器输出为0。反相器对比较器的其中一路输出信号反相从而使一个UPWM发生器输出两路差分UPWM信号。The schematic diagram of the structure of the trailing edge UPWM generator is shown in Figure 8, which includes an amplitude adjustment module, a second counter, a comparator and an inversion module. The clock signal clk_s is connected to the second counter and the amplitude adjustment module respectively, the digital audio signal data_t′ is connected to the amplitude adjustment module, the clock signal clk_m is connected to the second counter and the comparator respectively, the amplitude adjustment module is connected to the comparator, the second counter is connected to the comparator, the comparator directly outputs one way, and outputs one way after being connected to the inversion module. The function of the amplitude adjustment module is: when the frequency of the clock signal clk_s is f _cs , the adjustment formula of the amplitude of the current sampling point is:

When the frequency of the clock signal clk_s is f _c , the adjustment formula for the amplitude of the current sampling point is:

When the frequency of the clock signal clk_s is f _cl , the adjustment formula for the amplitude of the current sampling point is:

Among them, val_data′ is the original amplitude of the current sampling point. The second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is reset; the comparator compares the output count value of the counter with the adjusted signal amplitude at each rising edge of the clock signal clk_m, if the count value is less than the adjusted signal amplitude, the comparator output is 1; if the count value is greater than or equal to the adjusted signal amplitude, the comparator output is 0. The inverter inverts one of the output signals of the comparator so that one UPWM generator outputs two differential UPWM signals.

In order to improve the output fidelity of the power amplifier system, the first Sigma-Delta modulator and the second Sigma-Delta modulator of the present invention are both 8th order feedforward interpolation Sigma-Delta modulators, and the first Sigma-Delta modulator and the second Sigma-Delta modulator convert the 24-bit high-precision input signal into a 7-bit low-precision signal so that the first UPWM generator and the second UPWM generator output 64-level trailing edge UPWM signals. Since the filter-free pulse width modulator shown in FIG3 contains two UPWM generators, the four-way UPWM signals outputted by the generator just drive the four input terminals of the H-bridge power stage respectively, so that three voltage levels are formed at both ends of the power amplifier load, thereby reducing the dependence of the power amplifier on the LC analog low-pass filter in terms of efficiency, and since each UPWM signal has three sampling frequencies, the energy of the signal at both ends of the power amplifier load at the sampling frequency and its harmonics is diffused into the surrounding frequency band, thereby achieving the purpose of reducing the EMI of the power amplifier.

The present invention uses a field programmable gate array (FPGA) to implement a filter-free pulse width modulator based on the spread spectrum modulation method of the present invention, and builds a test system as shown in Figure 9 to verify the beneficial effects of the present invention. As shown in Figure 9, the digital audio test signal source generates a digital audio input signal in Sony/Philips Digital Interface Format (S/PDIF) with a sampling frequency of 48kHz, and the digital audio receiver processes the input signal into data in I ² S format. The filter-free pulse width modulator based on the spread spectrum modulation method of the present invention implemented by FPGA processes the data in I ² S format and outputs four-way rear edge secondary UPWM signals, which are input into a USB module to be processed into corresponding rear edge tertiary UPWM signals, and then the USB module transmits the rear edge tertiary UPWM signals to a computer for spectrum analysis.

When the test signal is a single-frequency sinusoidal digital signal with an amplitude of 0 dBFS, a frequency of 6.6 kHz, an accuracy of 24-bit, and a sampling frequency of 48 kHz, the baseband spectrum of the three-level UPWM signal output by the filter-free pulse width modulator without spread spectrum modulation function (the PRF of the secondary trailing edge UPWM signal output by the trailing edge UPWM generator is constant at 384 kHz) is shown in FIG10; the baseband spectrum of the three-level UPWM signal output by the filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention is shown in FIG11; the high-frequency spectrum of the three-level UPWM signal output by the filter-free pulse width modulator without spread spectrum modulation function is shown in FIG12; the high-frequency spectrum of the three-level UPWM signal output by the filter-free pulse width modulator based on the spread spectrum modulation method proposed in the present invention is shown in FIG13.

As shown in Figures 10 and 11, when the spread spectrum modulation method proposed in the present invention is used, the three-level UPWM signal spectrum output by the system has a lower amplitude at the third harmonic of the input signal, and the THD of the system is 0.009%, which is less than the THD (0.094%) of the three-level UPWM signal output by the system without the spread spectrum modulation function. As shown in Figures 12 and 13, when the spread spectrum modulation method proposed in the present invention is used, the peak amplitude of the three-level UPWM signal spectrum output by the system is -28.25dBFS out of the band, while when the system does not use the spread spectrum modulation method, the peak amplitude of the three-level UPWM signal spectrum output by the system is -10.5dBFS out of the band. Compared with the system without the spread spectrum modulation function, the peak amplitude of the three-level UPWM signal out of the band spectrum output by the system based on the spread spectrum modulation method proposed in the present invention is reduced by 17.75dB. It can be seen that the spread spectrum modulation method provided by the present invention can effectively reduce the energy peak on the high-frequency component of the UPWM signal output by the filter-free digital Class D audio amplifier, while reducing the output THD of the amplifier, thereby reducing the distortion introduced by UPWM while reducing the EMI of the amplifier.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The three-frequency pseudo-random variable spread spectrum modulation method is characterized by comprising the following steps:

step one: the interpolation filter is utilized to amplify the sampling frequency f of the input signal _o Lifting N times to sampling frequency f _s And according to the sampling frequency f _s Determining the intermediate frequency f of the required three sampling frequencies _c Wherein f _c ＝f _s Q, q is an integer less than N;

step two: based on the power amplification system master clock signal clk_m and the determined intermediate frequency f by using frequency synthesis technology _c Determining two other sampling frequencies f _cs And f _c1 Wherein f _cs For the smallest sampling frequency among the three,

N _s ＝p+v，f _c1 for the maximum sampling frequency of the three>

N1＝p-v，v∈[1，p-1]And v is an integer number of times,

f _{clk_m} for the frequency of the master clock signal clk_m, m is the number of stages of a uniform sampling pulse width modulation generator, "uniform sampling pulse width modulation" abbreviated as "UPWM";

step three: constructing a variable-magnification number extractor, and constructing a finite state machine and a pseudo-random number generator consisting of a 2 n-level linear feedback shift register in the variable-magnification number extractor, wherein the finite state machine obtains a final state uniquely corresponding to the n-bit pseudo-random number random_num generated by the pseudo-random number generator; the initial state of the finite state machine is S ₀ And (3) sequentially taking the value of a one-bit variable K from the highest bit to the lowest bit of the n-bit pseudo-random number, determining the next state by a finite state machine according to the value of K and the current state until the lowest bit of the pseudo-random number is taken by K, and outputting a final state, wherein the finite state machine has three final states respectively: s is S ₀ 、S ₁ 、S ₂ ；

Step four: constructing a threshold generator, a first counter and a clock generator in the variable multiplier decimator; the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and three values are respectively: t is t _s 、t _c 、t ₁ The method comprises the steps of carrying out a first treatment on the surface of the The first counter is an up-counter which counts the rising edge of the clock signal clk_bas, which is divided by the main clock signal clk_m, at a frequency f _{clk_bas} ＝f _s When the counter value is zero, the output clock signal clk_s of the clock generator is set at high level, and when the counter value cou_val is equal to the current threshold value

At the same time, the clock signal clk_s is set to low level, whenWhen the value cou_val of the counter is the same as the current threshold thr_val, the clock signal clk_s is again set to high level, and the counter is cleared [ the same ] ] _{Rounding up} Rounding off decimal places; the clock generator generates a new clock signal clk_s with three frequencies according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas;

step five: a data processing module is built in the variable multiple decimator, and when the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, so that the single sampling frequency signal data output by the interpolation filter is processed into a signal data_t with three sampling frequencies;

step six: when detecting the rising edge of a clock signal clk_s, a correction module is constructed, the amplitude of the current sampling point in an input signal data_t is recalculated and assigned by using a correction algorithm, a new signal data_t' is output, so that a UPWM signal obtained after the new signal passes through a rear edge UPWM generator approximates a natural sampling pulse width modulation signal in a time domain, and the natural sampling pulse width modulation is abbreviated as NPWM;

step seven: constructing an m-level trailing edge UPWM generator, constructing a second counter in the m-level trailing edge UPWM generator, wherein the counter is also an up-counter which counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared;

Step eight: an amplitude adjustment module is constructed in the m-level back edge UPWM generator, and as the frequency of the clock signal clk_s input by the back edge UPWM generator and the sampling frequency of the digital audio signal data_t ' input by the back edge UPWM generator are synchronous and variable, the duty ratio of the back edge UPWM signal output by the back edge UPWM generator is kept unchanged compared with that of the back edge UPWM signal which is not spread, the module judges the frequency of the current clk_s according to the input clock signal clk_s and the threshold signal thr_val through the current thr_val value, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t ' input by the back edge UPWM generator in real time and outputting a new signal data_t ';

step nine: constructing a comparator in the m-level trailing edge UPWM generator, and judging whether the output value count of the second counter in the step seven is larger than a threshold y or not at the rising edge of each clock signal clk_m by the comparator; if yes, the comparator outputs 0, otherwise outputs 1, so that a trailing edge two-level UPWM signal with three sampling frequencies is output; the current sampling point amplitude of the output signal data_t' of the threshold y and the amplitude adjustment module is equal.

2. The method according to claim 1, wherein in the third step, the 2 n-stage linear feedback shift register is composed of 2n D flip-flops and gates, and is controlled by a clock signal clk_r and a reset signal reset, the clock signal clk_r is obtained by dividing a frequency of a master clock signal clk_m, and the frequency f thereof _{clk_r} Greater than the maximum f of three sampling frequencies _c1 The output values of the last n D flip-flops of the 2 n-level linear feedback shift register form an n-bit pseudo random number rand_num after each clock period of clk_r;

in the third step, the state decision rule of the finite state machine is: if the current state is S ₀ K is 0, the next state is S ₀ The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S ₀ K takes a value of 1, then the next state is S ₁ The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S ₁ K is 0, the next state is S ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S ₁ K takes a value of 1, then the next state is S ₀ The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S ₂ K is 0, the next state is S ₁ The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S ₂ K takes a value of 1, then the next state is S ₂ 。

3. The method of three-frequency pseudo-random variable spread spectrum modulation according to claim 1, wherein in the fourth step, the rule for generating the threshold thr_val by the threshold generator is: at the final state corresponding to the current pseudo random number S ₀ At the time, the threshold thr_val is t ₁ The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S ₁ At the time, the threshold thr_val is t _c The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S ₂ At the time, the threshold thr_val is t _s ；

In the fourth step, the generation rule of the clock signal clk_s is: at the current threshold thr_val is t ₁ At the present period, the clock signal clk_s has a frequency f _cs The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t _c At the present period, the clock signal clk_s has a frequency f _c The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t _s At the present period, the clock signal clk_s has a frequency f _c1 。

4. The method according to claim 1, wherein in the sixth step, the correction algorithm used in the correction module is: suppose F ₁ (x ₁ ，in ₁ )、F ₂ (x ₂ ，in ₂ ) And F ₃ (x ₃ ，in ₃ ) For sampling points of adjacent three input modulated signals, where F ₂ F as the current sampling point ₁ For the previous sampling point, F ₃ For the latter sampling point, in ₁ 、in ₂ Sum in ₃ The amplitudes of the three sampling points are respectively,

x ₂ ＝0，

f ₁ and f ₂ Respectively are sampling points F ₁ And F ₂ The corresponding sampling frequency; normalizing the amplitude values of the carrier signal and the sampling point to make the minimum value be 0 and the maximum value be 1, and then at the sampling point F ₂ And F ₃ The saw-tooth wave carrier wave waveform expression between the two is:

Solving the intersection point of the carrier wave and a second-order Newton interpolation curve constructed by the three sampling points, namely, the amplitude of a pseudo natural sampling point to replace the amplitude of a current sampling point, and inputting the amplitude of the current sampling point to a rear edge UPWM generator, so that the generated rear edge UPWM signal approximates to a rear edge NPWM signal in a time domain, thereby reducing the harmonic distortion of the signal; the two parts The expression of the function of the order Newton interpolation curve is: in _p (x)＝λ ₁ +λ ₂ ·(x-x ₁ )+λ ₃ ·(x-x ₁ ) X, where λ ₁ ＝in ₁ ，

Let F (x) =in _p (x) -cw (x) =0, the initial value of x is set to +.>

The approximate solution of F (x) can be determined by Newton-Laportson iteration>

Wherein->

in′ _p (x)＝λ ₂ +λ ₃ ·x+λ ₃ ·(x-x ₁ ) The method comprises the steps of carrying out a first treatment on the surface of the Finally, x is _b Substituting into the carrier wave waveform expression to obtain the pseudo-natural sampling point amplitude +.>

From in _b The trailing edge UPWM signal generated by the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain.

5. The method of claim 1, wherein in the eighth step, the amplitude adjustment rule of the amplitude adjustment module is: at the current threshold signal thr_val is t ₁ When the frequency of the current clock signal clk_s is f _cs The current sampling point amplitude adjustment formula is:

at the current threshold signal thr_val is t _c When the frequency of the current clock signal clk_s is f _c The current sampling point amplitude adjustment formula is:

at the current threshold signal thr_val is t _s When the frequency of the current clock signal clk_s is f _c1 The current sampling point amplitude adjustment formula is:

Wherein val_data' is the original amplitude value of the current sampling point.

6. A filter-free pulse width modulator constructed by a three-frequency pseudo-random variable spread spectrum modulation method according to any one of the preceding claims 1-5, said filter-free pulse width modulator comprising an interpolation filter, a variable-multiple decimator, a negating module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first trailing edge UPWM generator and a second trailing edge UPWM generator; the digital audio input signal is connected with an interpolation filter, the interpolation filter is connected with a variable-power extractor, the variable-power extractor is respectively connected with a first correction module and an inversion module, the inversion module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first back edge UPWM generator, the second Sigma-Delta modulator is connected with a second back edge UPWM generator, and two paths of back edge UPWM signals output by the first back edge UPWM generator and two paths of back edge UPWM signals output by the second back edge UPWM generator are connected with an H bridge power level of a power amplifier.

7. The filter-less pulse width modulator of claim 6, wherein the interpolation filter is a 32-fold interpolation filter, the first Sigma-Delta modulator and the second Sigma-Delta modulator are identical and each an 8-order feedforward interpolation Sigma-Delta modulator, the first Sigma-Delta modulator and the second Sigma-Delta modulator each convert a 24-bit high-precision input signal to a low-precision signal of 7 bits 65 quantization levels such that the first trailing edge UPWM generator and the second trailing edge UPWM generator output 64-level trailing edge UPWM signals.

8. The filter-less pulse width modulator of claim 6, wherein the variable multiple decimator comprises a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine, and a data processing module; the system master clock signal is connected with the variable-multiple number extractor; the clock signal clk_r is respectively connected with the pseudo-random number generator and the finite state machine, and is obtained by dividing the frequency f of the clock signal clk_r by the main clock signal clk_m _{clk_r} Greater than the maximum f of three sampling frequencies _c1 The pseudo-random number generator is connected with the finite state machine, the finite state machine is connected with the threshold generator, and the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine; the clock signal clk_bas is respectively connected with a pseudo-random number generator, a finite state machine, a first counter and a clock generator, the first counter and the threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal clk_s by utilizing a frequency synthesis technology; the clock generator and the input signal data are both connected with the data processing module, and the data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, so that the digital audio signal data_t with three sampling frequencies is output.

9. The filter-less pwm according to claim 8, wherein the pseudo-random number generator is mainly composed of a 16-stage linear feedback shift register, and the linear feedback shift register generates an 8-bit pseudo-random number and inputs it to the finite state machine every time a clk_r period passes by setting an initial state to the linear feedback shift register; the finite state machine calculates a final state corresponding to the current pseudo-random number according to the current pseudo-random number and inputs the final state to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state;

the first counter counts the rising edge of the clock signal clk_bas, and when the rising edge of clk_bas is detected, the value of the first counter is increased by 1; when detecting that the value of the counter is equal to the current threshold thr_val, resetting the counter;

the first and second correction modules are identical, and recalculate the amplitude of each sampling point by using a correction technology according to the threshold signal thr_val, the clock signal clk_s and the digital audio signal data_t with three sampling frequencies output by the variable-multiple decimator, so as to output a new signal data_t'.

10. The filter-less pulse width modulator of claim 8, wherein the first trailing edge UPWM generator and the second trailing edge UPWM generator are identical comprising an amplitude adjustment module, a second counter, a comparator, and an inverter; the clock signal clk_s is respectively connected with the second counter and the amplitude adjustment module, the digital audio signal data_t' is connected with the amplitude adjustment module, the clock signal clk_m is respectively connected with the second counter and the comparator, the amplitude adjustment module and the second counter are respectively connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the inverter and then is output; the amplitude adjustment module calculates and adjusts the amplitude of the current sampling point according to an adjustment rule; the second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared; the comparator compares the counter value with the adjusted signal amplitude, one path of the signal is directly output as a rear edge UPWM signal, and the other path of the signal is inverted through the inverter and then outputs the rear edge UPWM signal.

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