CN110957983B - Three-frequency pseudo-random variable spread spectrum modulation method and filter-free pulse width modulator constructed by same - Google Patents

Three-frequency pseudo-random variable spread spectrum modulation method and filter-free pulse width modulator constructed by same Download PDF

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CN110957983B
CN110957983B CN201911252480.XA CN201911252480A CN110957983B CN 110957983 B CN110957983 B CN 110957983B CN 201911252480 A CN201911252480 A CN 201911252480A CN 110957983 B CN110957983 B CN 110957983B
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于泽琦
白鸽
张珂
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Zhengzhou University of Light Industry
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    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
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    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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Abstract

The invention provides a three-frequency pseudo-random variable spread spectrum modulation method and a filtering-free pulse width modulator constructed by the method, wherein the method firstly utilizes a frequency synthesis technology to determine three sampling frequencies; then after the input audio signal is oversampled, the audio signal is sampled by a variable-multiple decimator, a digital signal with the three sampling frequencies is generated, a synchronous clock signal clk_s is generated at the same time, the digital signal is pre-corrected by a correction module, the UPWM signal generated after the digital signal passes through a trailing edge UPWM generator is similar to the NPWM signal in time domain, and finally the trailing edge UPWM generator generates the UPWM signal with the three pulse repetition frequencies; meanwhile, a corresponding filter-free pulse width modulator is designed based on the spread spectrum modulation method. The invention can obviously reduce the amplitude of high-frequency components of UPWM signals output by the power amplifier, thereby reducing EMI and leading the power amplifier to have lower THD.

Description

Three-frequency pseudo-random variable spread spectrum modulation method and filter-free pulse width modulator constructed by same
Technical Field
The invention relates to the field of filter-free digital class-D audio power amplification, in particular to a three-frequency pseudo-randomly variable spread spectrum modulation method for a filter-free digital class-D audio power amplifier.
Background
The digital D-type audio power amplifier has the advantages of high power efficiency, convenience, digital audio interface, small volume and the like, and is widely applied to the current consumer electronic products. The structure diagram of the traditional digital D-class audio power amplifier is shown in fig. 1, and the traditional digital D-class audio power amplifier comprises a pulse width modulator, a power stage and an LC analog low-pass filter which are connected in sequence. In a conventional digital class D audio power amplifier, a digital audio signal input by the power amplifier is modulated into a pulse width modulation (Pulse Width Modulation, PWM) signal by a pulse width modulator, amplified by a high-power transistor of a power stage, and finally filtered by an inductance-capacitance (LC) analog low-pass filter to remove high-frequency components and then sound the speaker. Because the LC analog low-pass filter occupies about 75% of the whole power amplification system and consumes about 30% of the cost, the volume and the cost of the power amplification system are greatly increased, and the development trend of miniaturization and portability of current audio-visual products is not met, therefore, the filter-free digital D-type audio power amplifier appears and becomes a research hotspot.
The structure diagram of the filtering-free digital D-class audio power amplifier is shown in fig. 2, and mainly comprises a filtering-free pulse width modulator and an H-bridge type power stage. The filtering-free pulse width modulator mainly comprises an interpolation filter, an inversion module, a Sigma-Delta modulator and a Uniform sampling pulse width modulation (UPWM) generator, and converts a digital audio signal into four UPWM signals under the condition that the baseband information of an input signal is basically kept unchanged by using an oversampling technology, a quantization noise shaping technology and a UPWM technology, wherein the four UPWM signals drive an H bridge power level and form three-level UPWM signals on a loudspeaker load. The three-stage UPWM enables the voltage at two ends of the power amplifier load to be equal to zero volt in most of the time in each switching period, so that the current flowing through the load is greatly reduced, and the dependence on an LC analog low-pass filter is reduced in the aspect of efficiency of the power amplifier. However, the filter-free digital class D audio power amplifier output signal has higher energy at the pulse repetition frequency (Pulse Repetition Frequency, PRF) and its harmonics, which high frequency component energy will cause the power amplifier output signal to generate more severe electromagnetic interference (Electro-Magnetic Interference, EMI). Therefore, in order to further improve the practicability of the filtering-free digital class D audio power amplifier, a special method is required to reduce the high-frequency energy peak of the power amplifier output signal, thereby reducing the EMI of the power amplifier. The EMI suppression method for the class D audio power amplifier is mainly divided into two types: (1) Source suppression, such as soft switching technology, spread spectrum modulation technology, etc.; (2) From transmission path suppression, such as board-level system layout wiring optimization design, shielding technology and the like are adopted. The spread spectrum modulation technology is relatively simple to realize and easy to control, so that the method becomes a main method for solving the problem of the EMI of the class D audio power amplifier.
The spread spectrum modulation method for the D-class audio power amplifier disclosed and published at present mainly comprises the following steps: low power frequency modulation (Yeh M L, liou W R, hsieh H P, et al an electromagnetic interference (EMI) reduced high-efficiency switching power amplifier [ J ]. IEEE Transactions on Power Electronics,2010,25 (3): 710-718.), construction of the "PWM Chopping" module method (Balmelli P, khory J M, viegas E, et al A low-EMI 3-W audio class-D amplifier compatible with AM/FM radio [ J ]. IEEE Journal of Solid-State Circuits,2013,48 (8): 1771-1782), random wrap pulse position modulation (Adrian V, keer C, gwee B H, et al A randomized modulation scheme for filterless digital class D audio amplifiers [ C ]. Proceedings of the 2014IEEE International Symposium on Circuits and Systems.IEEE,2014:774-777.), multiple frequency pulse modulation (Karaca T, auer M.digital pulse-width modulator with spread-spectrum emission reduction.e & i Elektrotechnik und Informationstechnik,2018,135 (1-53)), and the like. The low-power frequency modulation method changes the PRF of the PWM signal of the power amplifier in real time by constructing an ultralow-power spread spectrum clock generator, reduces the EMI of the power amplifier and simultaneously well maintains the high efficiency of the power amplifier, but the method needs an analog circuit to realize or needs an analog input signal to participate in modulation, thus being only suitable for analog D-type audio power amplifier. The constructed PWM Chopping module method utilizes the noise shaping function of a zero-input Sigma-Delta modulator to control the output PWM signal frame by frame, so that common mode high frequency peaks at two ends of a power amplifier load are reduced, but the system needs higher main clock frequency. The random winding pulse position modulation method realizes spread spectrum by randomizing the position of each pulse of the UPWM signal in the current switching period, and is based on a two-level PWM technology, so that the power amplifier has lower EMI, but the efficiency is greatly reduced. The multi-frequency pulse modulation method controls the PRF of the output signal of the UPWM generator through two reversible counters so as to achieve the purpose of spreading frequency.
Disclosure of Invention
Aiming at the defects of the existing spread spectrum modulation method, the invention provides a spread spectrum modulation method for a filtering-free digital D-type audio power amplifier, which is easy to realize, can greatly reduce the amplitude of high-frequency components of a UPWM signal output by the power amplifier while reducing the THD of a system, and achieves the aim of reducing EMI. The method comprises the following implementation steps:
step one: the interpolation filter is utilized to amplify the sampling frequency f of the input signal o Lifting N times to sampling frequency f s And according to the sampling frequency f s Determining the intermediate frequency f of the required three sampling frequencies c Wherein f c ＝f s Q, q is an integer less than N;
step two: based on the power amplification system master clock signal clk_m and the determined intermediate frequency f by using frequency synthesis technology c Determining two other sampling frequencies f cs And f cl Wherein f cs For the smallest sampling frequency among the three,
Figure SMS_1
N s ＝p+v，f cl for the maximum sampling frequency of the three>
Figure SMS_2
N 1 ＝p-v，v∈[1，p-1]And v is an integer number of times,
Figure SMS_3
f clk_m the frequency of the main clock signal clk m is the number of stages of the UPWM generator;
step three: constructing a variable-magnification number extractor, and constructing a finite state machine and a pseudo-random number generator consisting of a 2 n-level linear feedback shift register in the variable-magnification number extractor, wherein the finite state machine obtains a final state uniquely corresponding to the n-bit pseudo-random number random_num generated by the pseudo-random number generator; finite state machine initialization The initial state is S 0 And (3) sequentially taking the value of a one-bit variable K from the highest bit to the lowest bit of the n-bit pseudo-random number, determining the next state by a finite state machine according to the value of K and the current state until the lowest bit of the pseudo-random number is taken by K, and outputting a final state, wherein the finite state machine has three final states respectively: s is S 0 、S 1 、S 2 ；
Step four: constructing a threshold generator, a first counter and a clock generator in the variable multiplier decimator; the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and three values are respectively: t is t s 、t c 、t 1 The method comprises the steps of carrying out a first treatment on the surface of the The first counter is an up-counter which counts the rising edge of the clock signal clk_bas, which is divided by the main clock signal clk_m, at a frequency f clk_bas ＝f s When the counter value is zero, the output clock signal clk_s of the clock generator is set at high level, and when the counter value cou_val is equal to the current threshold value
Figure SMS_4
When the value of the counter cou_val is the same as the current threshold thr_val, the clock signal clk_s is set at the low level, and when the value of the counter cou_val is the same as the current threshold thr_val, the clock signal clk_s is set at the high level again, and the counter is cleared [ ] Rounding up Rounding off decimal places; the clock generator generates a new clock signal clk_s with three frequencies according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas;
step five: a data processing module is built in the variable multiple decimator, and when the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, so that the single sampling frequency signal data output by the interpolation filter is processed into a signal data_t with three sampling frequencies;
step six: when the rising edge of the clock signal clk_s is detected, a correction module is constructed, the amplitude of the current sampling point in the input signal data_t is recalculated and assigned by using a correction algorithm, a new signal data_t' is output, and a UPWM signal obtained after the new signal passes through a rear edge UPWM generator approximates to a Natural sampling pulse width modulation (Natural-sampling Pulse Width Modulation, NPWM) signal in a time domain;
step seven: constructing an m-level trailing edge UPWM generator, constructing a second counter in the m-level trailing edge UPWM generator, wherein the counter is also an up-counter which counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared;
Step eight: an amplitude adjustment module is constructed in the m-level back edge UPWM generator, and as the frequency of the clock signal clk_s input by the back edge UPWM generator and the sampling frequency of the digital audio signal data_t ' input by the back edge UPWM generator are synchronous and variable, the duty ratio of the back edge UPWM signal output by the back edge UPWM generator is kept unchanged compared with that of the back edge UPWM signal which is not spread, the module judges the frequency of the current clk_s according to the input clock signal clk_s and the threshold signal thr_val through the current thr_val value, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t ' input by the back edge UPWM generator in real time and outputting a new signal data_t ';
step nine: constructing a comparator in the m-level trailing edge UPWM generator, and judging whether the output value count of the second counter in the step seven is larger than a threshold y or not at the rising edge of each clock signal clk_m by the comparator; if yes, the comparator outputs 0, otherwise outputs 1, so that a trailing edge two-level UPWM signal with three sampling frequencies is output; the current sampling point amplitude of the output signal data_t' of the threshold y and the amplitude adjustment module is equal.
In the third step, the 2 n-stage linear feedback shift register consists of 2n D flip-flops and a plurality of gates, and is controlled by a clock signal clk_r and a reset signal reset, wherein the clock signal clk_r is obtained by dividing the frequency of a main clock signal clk_m, and the frequency f of the clock signal clk_r is obtained by dividing the frequency of the main clock signal clk_m clk_r Greater than the maximum f of three sampling frequencies c1 The output values of the last n D flip-flops of the 2n stage linear feedback shift register constitute an n-bit pseudorandom number rand_num every clock cycle of clk_r.
In the third step, the finite state machine is shapedThe state judgment rule is as follows: if the current state is S 0 K is 0, the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 0 K takes a value of 1, then the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K is 0, the next state is S 2 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K takes a value of 1, then the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K is 0, the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K takes a value of 1, then the next state is S 2 。
In the fourth step, the rule for generating the threshold thr_val by the threshold generator is as follows: at the final state corresponding to the current pseudo random number S 0 At the time, the threshold thr_val is t 1 The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S 1 At the time, the threshold thr_val is t c The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S 2 At the time, the threshold thr_val is t s 。
In the fourth step, the generation rule of the clock signal clk_s is: at the current threshold thr_val is t 1 At the present period, the clock signal clk_s has a frequency f cs The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t c At the present period, the clock signal clk_s has a frequency f c The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t s At the present period, the clock signal clk_s has a frequency f c1 。
In the sixth step, the correction algorithm used in the correction module is: suppose F 1 (x 1 ，in 1 )、F 2 (x 2 ，in 2 ) And F 3 (x 3 ，in 3 ) For sampling points of adjacent three input modulated signals, where F 2 F as the current sampling point 1 For the previous sampling point, F 3 For the latter sampling point, in 1 、in 2 Sum in 3 The amplitudes of the three sampling points are respectively,
Figure SMS_7
x 2 ＝0，
Figure SMS_9
f 1 and f 2 Respectively are sampling points F 1 And F 2 The corresponding sampling frequency; normalizing the amplitude values of the carrier signal and the sampling point to make the minimum value be 0 and the maximum value be 1, and then at the sampling point F 2 And F 3 The saw-tooth wave carrier wave waveform expression between the two is:
Figure SMS_11
Solving the amplitude of the intersection point (pseudo natural sampling point) of the carrier wave and the second-order Newton interpolation curve constructed by the three sampling points to replace the amplitude of the current sampling point to be input into the back edge UPWM generator, so that the generated back edge UPWM signal approximates to the back edge NPWM signal in the time domain, and the harmonic distortion of the signal is reduced; the second-order Newton interpolation curve function expression is: in p (x)＝λ 1 +λ 2 ·(x-x 1 )+λ 3 ·(x-x 1 ) X, where λ 1 ＝in 1 ，
Figure SMS_6
Let F (x) =in p (x) -cw (x) =0, the initial value of x being set to
Figure SMS_8
Approximate solution of F (x) can be obtained by Newton-Laportson iteration method
Figure SMS_10
Wherein->
Figure SMS_12
in′ p (x)＝λ 2 +λ 3 ·x+λ 3 ·(x-x 1 ) The method comprises the steps of carrying out a first treatment on the surface of the Finally, x is b Substituting into the carrier wave waveform expression to obtain the pseudo-natural sampling point amplitude +.>
Figure SMS_5
From in b The trailing edge UPWM signal generated by the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain.
In the eighth step, the amplitude adjustment rule of the amplitude adjustment module is: at presentThe threshold signal thr_val is t 1 When the frequency of the current clock signal clk_s is f cs The current sampling point amplitude adjustment formula is:
Figure SMS_13
at the current threshold signal thr_val is t c When the frequency of the current clock signal clk_s is f c The current sampling point amplitude adjustment formula is:
Figure SMS_14
At the current threshold signal thr_val is t s When the frequency of the current clock signal clk_s is f c1 The current sampling point amplitude adjustment formula is:
Figure SMS_15
wherein val_data' is the original amplitude value of the current sampling point.
The filtering-free pulse width modulator constructed by the three-frequency pseudorandom variable spread spectrum modulation method comprises an interpolation filter, a variable multiple extractor, a negating module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first trailing edge UPWM generator and a second trailing edge UPWM generator; the digital audio input signal is connected with an interpolation filter, the interpolation filter is connected with a variable-power extractor, the variable-power extractor is respectively connected with a first correction module and an inversion module, the inversion module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first back edge UPWM generator, the second Sigma-Delta modulator is connected with a second back edge UPWM generator, and two paths of back edge UPWM signals output by the first back edge UPWM generator and two paths of back edge UPWM signals output by the second back edge UPWM generator are connected with an H bridge power level of a power amplifier.
The interpolation filter is a 32-time interpolation filter, the first Sigma-Delta modulator and the second Sigma-Delta modulator are the same and are all 8-order feedforward interpolation Sigma-Delta modulators, and the first Sigma-Delta modulator and the second Sigma-Delta modulator both convert 24-bit high-precision input signals into 7-bit low-precision signals with 65 quantization levels so that the first trailing edge UPWM generator and the second trailing edge UPWM generator output 64-level trailing edge UPWM signals.
The variable multiple number extractor comprises a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine and a data processing module; the system master clock signal is connected with the variable-multiple number extractor; the clock signal clk_r is respectively connected with the pseudo-random number generator and the finite state machine, and is obtained by dividing the frequency f of the clock signal clk_r by the main clock signal clk_m clk_r Greater than the maximum f of three sampling frequencies cl The pseudo-random number generator is connected with the finite state machine, the finite state machine is connected with the threshold generator, and the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine; the clock signal clk_bas is respectively connected with a pseudo-random number generator, a finite state machine, a first counter and a clock generator, the first counter and the threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal clk_s by utilizing a frequency synthesis technology; the clock generator and the input signal data are both connected with the data processing module, and the data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, so that the digital audio signal data_t with three sampling frequencies is output.
The pseudo-random number generator mainly comprises a 16-stage linear feedback shift register, and an initial state is set for the linear feedback shift register, and the linear feedback shift register generates an 8-bit pseudo-random number and inputs the 8-bit pseudo-random number to a finite state machine after a clk_r period; the finite state machine calculates a final state corresponding to the current pseudo-random number according to the current pseudo-random number and inputs the final state to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state.
The first counter counts the rising edge of the clock signal clk_bas, and when the rising edge of clk_bas is detected, the value of the first counter is increased by 1; when the value of the counter is detected to be equal to the current threshold thr_val, the counter is cleared.
The first and second correction modules are identical, and recalculate the amplitude of each sampling point by using a correction technology according to the threshold signal thr_val, the clock signal clk_s and the digital audio signal data_t with three sampling frequencies output by the variable-multiple decimator, so as to output a new signal data_t'.
The first back edge UPWM generator is the same as the second back edge UPWM generator, and comprises an amplitude adjustment module, a second counter, a comparator and an inversion module; the clock signal clk_s is respectively connected with the second counter and the amplitude adjustment module, the digital audio signal data_t' is connected with the amplitude adjustment module, the clock signal clk_m is respectively connected with the second counter and the comparator, the amplitude adjustment module and the second counter are respectively connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the inverting module and then is output; the amplitude adjustment module calculates and adjusts the amplitude of the current sampling point according to an adjustment rule; the second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared; the comparator compares the counter value with the adjusted signal amplitude, one path of the signal is directly output as a rear edge UPWM signal, and the other path of the signal is inverted by the inverting module and then outputs the rear edge UPWM signal.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is based on a filtering-free modulation architecture, a back edge UPWM technology and a pseudo-random spread spectrum modulation technology, an input audio signal is sampled into an audio signal with three sampling frequencies by constructing a variable multiple extractor, a clock signal synchronous with a digital audio signal is synthesized, and then the amplitude of each sampling point is corrected by utilizing a correction module, so that the baseband distortion introduced in the UPWM process is reduced, and the high-frequency peak amplitude of the output UPWM signal is reduced, and meanwhile, less harmonic distortion is well guaranteed to be introduced, so that the purposes of reducing the EMI and THD of a power amplifier are achieved.
2. The method provided by the invention can be realized by a full digital circuit and can be conveniently applied to the existing filtering-free digital D-type audio power amplifier system.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a conventional digital class D audio power amplifier;
FIG. 2 is a schematic diagram of a filter-free digital class D audio amplifier;
FIG. 3 is a schematic diagram of a filter-free PWM structure according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a variable-magnification extractor according to the present invention;
FIG. 5 is a schematic diagram of a linear feedback shift register according to the present invention;
FIG. 6 is a finite state machine state transition diagram of the present invention;
FIG. 7 is a schematic diagram of a calibration algorithm according to the present invention;
FIG. 8 is a schematic diagram of a trailing edge UPWM generator of the present invention;
FIG. 9 is a schematic diagram of a test system according to the present invention;
FIG. 10 is a baseband spectrum diagram of a trailing edge three-level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator without spread spectrum modulation;
FIG. 11 is a baseband spectrum of a trailing edge three-level UPWM signal output by the filter-free pulse width modulator of the test system of FIG. 9 using the spread spectrum modulation method of the present invention;
FIG. 12 is a high frequency spectrum of a trailing edge three stage UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator without spread spectrum modulation;
fig. 13 is a high frequency spectrum of a trailing edge three-level UPWM signal output by the test system of fig. 9 using a filter-free pwm based on the spread spectrum modulation method of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without any inventive effort, are intended to be within the scope of the invention.
A three-frequency pseudo-random variable spread spectrum modulation method for a filtering-free digital class-D audio power amplifier comprises the following steps.
The first step: the interpolation filter is utilized to amplify the sampling frequency f of the input signal o Lifting N times to sampling frequency f s And according to the sampling frequency f s Determining the intermediate frequency f of the required three sampling frequencies c Wherein f c ＝f s Q, q is an integer less than N;
and a second step of: based on the power amplification system master clock signal clk_m and the determined intermediate frequency f by using frequency synthesis technology c Determining two other sampling frequencies f cs And f c1 Wherein f cs For the smallest sampling frequency among the three,
Figure SMS_16
N s ＝p+v，f c1 for the maximum sampling frequency of the three>
Figure SMS_17
N 1 ＝p-v，v∈[1，p-1]And v is an integer number of times,
Figure SMS_18
f clk_m the frequency of the main clock signal clk_m, m is the number of stages of the UPWM generator;
And a third step of: constructing a variable-magnification extractor, constructing a finite state machine and a finite state machine in the variable-magnification extractorThe finite state machine obtains a final state uniquely corresponding to the n-bit pseudo-random number random_num generated by the pseudo-random number generator by using the pseudo-random number generator consisting of 2 n-level linear feedback shift registers; the 2 n-stage linear feedback shift register consists of 2n D flip-flops and a plurality of gates, and is controlled by a clock signal clk_r and a reset signal reset, wherein the clock signal clk_r is obtained by dividing a main clock signal clk_m, and the frequency f of the clock signal clk_r is clk_r Greater than the maximum f of three sampling frequencies c1 The output values of the last n D flip-flops of the 2 n-level linear feedback shift register form an n-bit pseudo random number rand_num after each clock period of clk_r; the initial state of the finite state machine is S 0 And (3) sequentially taking the value of a one-bit variable K from the highest bit to the lowest bit of the n-bit pseudo-random number, determining the next state by a finite state machine according to the value of K and the current state until the lowest bit of the pseudo-random number is taken by K, and outputting a final state, wherein the finite state machine has three final states respectively: s is S 0 、S 1 、S 2 The method comprises the steps of carrying out a first treatment on the surface of the The state decision rule of the finite state machine is: if the current state is S 0 K is 0, the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 0 K takes a value of 1, then the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K is 0, the next state is S 2 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K takes a value of 1, then the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K is 0, the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K takes a value of 1, then the next state is S 2 ；
Fourth step: constructing a threshold generator, a first counter and a clock generator in the variable multiplier decimator; the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and three values are respectively: t is t s 、t c 、t 1 The method comprises the steps of carrying out a first treatment on the surface of the The method comprises the steps of carrying out a first treatment on the surface of the The determination rule of the threshold thr_val is as follows: at the final state corresponding to the current pseudo random number S 0 At the time, the threshold thr_val is t 1 The method comprises the steps of carrying out a first treatment on the surface of the At the current pseudo-random numberThe corresponding final state is S 1 At the time, the threshold thr_val is t c The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S 2 At the time, the threshold thr_val is t s The method comprises the steps of carrying out a first treatment on the surface of the The first counter is a counter which counts the rising edge of the clock signal clk_bas, when the count value is zero, the clock signal clk_s is set at a high level, and when the value cou_val of the counter is equal to the current threshold value
Figure SMS_19
When the value of the counter cou_val is the same as the current threshold thr_val, the clock signal clk_s is set at the low level, and when the value of the counter cou_val is the same as the current threshold thr_val, the clock signal clk_s is set at the high level again, and the counter is cleared [] Rounding up Rounding off decimal places; the clock generator generates a new clock signal clk_s with three frequencies (the frequencies of which are f respectively) according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas cs 、f c And f c1 ) Wherein the clock signal clk_bas is divided by the master clock signal clk_m, the frequency f clk_bas ＝f s The method comprises the steps of carrying out a first treatment on the surface of the The generation rule of the clock signal clk_s is: at the current threshold thr_val is t 1 At the present period, the clock signal clk_s has a frequency f cs The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t c At the present period, the clock signal clk_s has a frequency f c The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t s At the present period, the clock signal clk_s has a frequency f cl ；/>
Fifth step: a data processing module is built in the variable multiple decimator, and when the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, so that the single sampling frequency signal data output by the interpolation filter is processed into a signal data_t with three sampling frequencies;
sixth step: when the rising edge of the clock signal clk_s is detected, the amplitude of the current sampling point in the input signal data_t is recalculated and assigned by using a correction algorithm, and a new signal data_t' is output, so that a U PWM signal obtained after passing through a UPWM generator is similar to an NPWM signal in the time domain; the correction algorithm used in the correction module is: suppose F 1 (x 1 ，in 1 )、F 2 (x 2 ，in 2 ) And F 3 (x 3 ，in 3 ) For sampling points of adjacent three input modulated signals, where F 2 F as the current sampling point 1 For the previous sampling point, F 3 For the latter sampling point, in 1 、in 2 Sum in 3 The amplitudes of the three sampling points are respectively,
Figure SMS_21
x 2 ＝0，
Figure SMS_23
f 1 and f 2 Respectively are sampling points F 1 And F 2 The corresponding sampling frequency; normalizing the amplitude values of the carrier signal and the sampling point to make the minimum value be 0 and the maximum value be 1, and then at the sampling point F 2 And F 3 The carrier waveform expression between them is:
Figure SMS_25
Solving the amplitude of the intersection point (pseudo natural sampling point) of the carrier wave and the second-order Newton interpolation curve constructed by the three sampling points to replace the amplitude of the current sampling point to be input into the back edge UPWM generator, so that the generated back edge UPWM signal approximates to the back edge NPWM signal in the time domain, and the harmonic distortion of the signal is reduced; the second-order Newton interpolation curve function expression is: in p (x)＝λ 1 +λ 2 ·(x-x 1 )+λ 3 ·(x-x 1 ) X, where λ 1 ＝in 1 ，
Figure SMS_22
Let F (x) =in p (x) -cw (x) =0, the initial value of x is set to +.>
Figure SMS_24
Approximate solution of F (x) can be obtained by Newton-Laportson iteration method
Figure SMS_26
Wherein->
Figure SMS_27
in′ p (x)＝λ 2 +λ 3 ·x+λ 3 ·(x-x 1 ) The method comprises the steps of carrying out a first treatment on the surface of the Finally, x is b Substituting into the carrier wave waveform expression to obtain the pseudo-natural sampling point amplitude +.>
Figure SMS_20
From in b The trailing edge UPWM signal generated by the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain;
Seventh step: constructing an m-level trailing edge UPWM generator, constructing a second counter in the m-level trailing edge UPWM generator, wherein the counter is also an up-counter which counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared;
eighth step: an amplitude adjustment module is constructed in the m-level trailing edge UPWM generator, and because the frequency of a clock signal clk_s input by the trailing edge UPWM generator and the sampling frequency of a digital audio signal data t ' input by the trailing edge UPWM generator are synchronous and variable, the duty ratio of the trailing edge UPWM signal output by the trailing edge UPWM generator is kept unchanged when compared with that of the trailing edge UPWM signal which is not spread, and the module judges the frequency of the current clk_s according to the input clock signal clk_s and a threshold signal thr_val through the current thr_val value, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t ' input by the trailing edge UPWM generator in real time and outputting a new signal data_t '; the amplitude adjustment rule of the amplitude adjustment module is as follows: at the current threshold signal thr_val is t 1 When the frequency of the current clock signal clk_s is f cs The current sampling point amplitude adjustment formula is:
Figure SMS_28
at the current threshold signal thr_val is t c When the frequency of the current clock signal clk_s is f c The current sampling point amplitude adjustment formula is:
Figure SMS_29
At the current threshold signal thr_val is t s When the current clock signalclk_s has a frequency f c1 The current sampling point amplitude adjustment formula is:
Figure SMS_30
wherein val_data' is the original amplitude value of the current sampling point.
Ninth step: constructing a comparator in the m-level trailing edge UPWM generator, and judging whether the output value count of the counter in the step seven is larger than a threshold y at the rising edge of each clock signal clk_m by the comparator; if yes, the comparator outputs 0, otherwise outputs 1, so that a trailing edge two-level UPWM signal with three sampling frequencies is output; the current sampling point amplitude of the output signal data_t' of the threshold y and the amplitude adjustment module is equal. Each UPWM generator in the filtering-free digital D-type audio power amplifier outputs two paths of differential signals, the two UPWM generators output four paths of UPWM signals altogether to drive an H bridge type power level, so that three voltage levels are formed at two ends of a power amplifier load, dependence on an LC analog low-pass filter is reduced in efficiency of the power amplifier, and energy of signals at two ends of the power amplifier load at the PRF and harmonic waves of the PRF is diffused into a peripheral frequency band due to the fact that PRF of each path of UPWM signals is variable, and the aim of reducing power amplifier EMI is achieved.
The three-frequency pseudo-random variable spread spectrum modulation method is utilized to construct a filtering-free pulse width modulator, and the structure diagram of the filtering-free pulse width modulator is shown in figure 3. The filtering-free pulse width modulator comprises an interpolation filter, a variable multiple extractor, an inversion module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first trailing edge UPWM generator and a second trailing edge UPWM generator; the digital audio signal is connected with an interpolation filter, the interpolation filter is connected with a variable-power extractor, the variable-power extractor is respectively connected with a first correction module and an inversion module, the inversion module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first back edge UPWM generator, the second Sigma-Delta modulator is connected with a second back edge UPWM generator, and two paths of back edge UPWM signals output by the first back edge UPWM generator and two paths of back edge UPWM signals output by the second back edge UPWM generator are connected with an H bridge power level of a power amplifier.
F in FIG. 3 o =48 kHz is the sampling frequency of the audio input signal, the filter-free pulse width modulator uses the frequency f of the main clock clk_m clk_m Is 98.304MHz. The interpolation filter designed by the invention is an interpolation filter for realizing 32 times of oversampling, and uniformly improves the sampling frequency of 48kHz of an input signal to f s =1536 kHz, the sampling frequency f s Also the frequency of the clock signal clk_bas.
In order to achieve the purpose of spreading, a schematic diagram of the variable-multiple extractor designed by the invention is shown in fig. 4. The variable multiple decimator includes a first counter, a clock generator, a pseudorandom number generator, a threshold generator, a finite state machine, and a data processing module. The clock signal clk_bas is respectively connected with a pseudo-random number generator, a finite state machine, a first counter and a clock generator, the first counter and the threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal clk_s with three frequencies by utilizing a frequency synthesis technology. In the system, let q=4, v=1, the number of stages m=64 of the trailing edge UPWM generator, then f c ＝f s /q＝384kHz，
Figure SMS_31
N s ＝p+v＝5，N 1 ＝p-v＝3，
Figure SMS_32
Figure SMS_33
The clock signal clk_r is respectively connected with the pseudo-random number generator and the finite state machine, and is obtained by dividing the frequency f of the clock signal clk_r by the main clock signal clk_m clk_r Greater than the maximum f of three sampling frequencies cl In the present system, the frequency f of the clock signal clk_r clk_r 768kHz. An 8-bit pseudo-random number generator formed by 16-stage linear feedback shift registers is connected with a finite state machine. The 16-level lineThe schematic diagram of the structure of the feedback shift register is shown in fig. 5, and the feedback shift register consists of 16D flip-flops, 3 4 input or gates, 1 3 input or gate, 1 4 input nor gate and 4 exclusive or gates. The 16-stage linear feedback shift register is controlled by a clock signal clk_r and a reset signal reset, and the output values of the last 8D flip-flops in the 16-stage linear feedback shift register form an 8-bit pseudo-random number rand_num every time a clock period of clk_r passes. The state transition diagram of the finite state machine is shown in fig. 6, and the initial state of the finite state machine is S 0 And (3) sequentially taking the value of a one-bit variable K from the highest bit to the lowest bit of the 8-bit pseudo-random number, determining the next state by a finite state machine according to the value of K and the current state until the lowest bit of the pseudo-random number is taken by K, and outputting a final state, wherein the finite state machine has three final states respectively: s is S 0 、S 1 、S 2 . As can be seen from fig. 6, the finite state machine state decision rule is: if the current state is S 0 K is 0, the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 0 When K takes a value of 1, the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K is 0, the next state is S 2 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K takes a value of 1, then the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K is 0, the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K takes a value of 1, then the next state is S 2 . The finite state machine is connected with the threshold generator, and the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine. The rule for the threshold generator to generate the threshold thr_val is: at the final state corresponding to the current pseudo random number S 0 At the time, the threshold thr_val is t 1 ＝f s /f cs =5; at the final state corresponding to the current pseudo random number S 1 At the time, the threshold thr_val is t c ＝f s /f c =4; at the final state corresponding to the current pseudo random number S 2 At the time, the threshold thr_val is t s ＝f s /f cl =3. The first counter counts up 1 to the rising edge of the clock signal clk_bas, and generates a clock when the count value is zeroThe output clock signal clk_s of the generator is set high, when the counter value cou_val is equal to the current threshold value
Figure SMS_34
When the value of the counter cou_val is the same as the current threshold thr_val, the clock signal clk_s is set at the low level, and when the value of the counter cou_val is the same as the current threshold thr_val, the clock signal clk_s is set at the high level again, and the counter is cleared [ ] Rounding up Rounding off decimal places. The clock generator generates a new clock signal clk_s with three frequencies (307.2 kHz, 384kHz and 512 kHz) based on the threshold thr_val, the counter value cou_val and the clock signal clk_bas. The clock generator and the input signal data are both connected with a data processing module, and the data processing module performs extraction processing on the input digital audio signal data according to a clock signal clk_s generated by the clock generator, so as to output digital audio signals data_t with three sampling frequencies (307.2 kHz, 384kHz and 512 kHz).
In order to eliminate harmonic distortion of the power amplifier output signal, the correction module corrects the digital audio signal data_t to data_t'. A schematic diagram of the correction algorithm used in the correction module is shown in fig. 7. The algorithm corrects the modulation signal before the UPWM by utilizing the characteristic that the NPWM has no harmonic distortion, so that the UPWM signal finally output by the UPWM generator is similar to the NPWM signal in the time domain to eliminate the harmonic distortion of the output signal. And establishing a second-order Newton interpolation curve function expression according to the current sampling point, the previous sampling point and the next sampling point of the modulation signal, simultaneously establishing a carrier waveform expression, and solving the intersection amplitude of the carrier waveform and the interpolation curve by using a Newton-Lafson iteration method, wherein the rear edge UPWM waveform obtained by the rear edge UPWM generator is similar to the rear edge NPWM waveform in time domain.
The structural schematic diagram of the trailing edge UPWM generator is shown in fig. 8, and the trailing edge UPWM generator comprises an amplitude adjustment module, a second counter, a comparator and an inverting module. The clock signal clk_s is respectively connected with the second counter and the amplitude adjustment module, the digital audio signal data_t' is connected with the amplitude adjustment module, the clock signal clk_m is respectively connected with the second counter and the comparator, the amplitude adjustment module is connected with the comparator, the secondThe counter is connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the inverting module and then output. The amplitude adjustment module has the functions of: the clock signal clk_s has a frequency f cs When the current sampling point amplitude value is adjusted according to the formula:
Figure SMS_35
the clock signal clk_s has a frequency f c When the current sampling point amplitude value is adjusted according to the formula:
Figure SMS_36
the clock signal clk_s has a frequency f cl When the current sampling point amplitude value is adjusted according to the formula:
Figure SMS_37
Wherein val_data' is the original amplitude value of the current sampling point. The second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared; the comparator compares the output count value of the counter with the adjusted signal amplitude at the rising edge of each clock signal clk_m, and if the count value is smaller than the adjusted signal amplitude, the comparator outputs 1; if the count value is greater than or equal to the adjusted signal amplitude, the comparator outputs 0. The inverter inverts one of the output signals of the comparator so that one UPWM generator outputs two differential UPWM signals.
In order to improve the output fidelity of a power amplification system, the first Sigma-Delta modulator and the second Sigma-Delta modulator are 8-order feedforward interpolation Sigma-Delta modulators, and the first Sigma-Delta modulator and the second Sigma-Delta modulator convert a 24-bit high-precision input signal into a 7-bit low-precision signal so that the first UPWM generator and the second UPWM generator output 64-order trailing edge UPWM signals. Because the filter-free pulse width modulator shown in fig. 3 comprises two UPWM generators, four paths of UPWM signals output by the UPWM generators just respectively drive four input ends of an H bridge type power stage, so that three voltage levels are formed at two ends of a power amplifier load, dependence on an LC analog low-pass filter is reduced in efficiency, and because each path of UPWM signals has three sampling frequencies, energy of signals at two ends of the power amplifier load at the sampling frequencies and harmonic waves of the signals is diffused into a peripheral frequency band, and the aim of reducing power amplifier EMI is achieved.
The invention realizes the filtering-free pulse width modulator based on the spread spectrum modulation method by using a Field programmable gate array (Field-Programmable Gate Array, FPGA), and builds a test system shown in figure 9 to verify the beneficial effects of the invention. As can be seen in FIG. 9, the digital audio test signal source generates a digital audio input signal in Sony/Philips digital interface format (Sony/Philips Digital Interface Format, S/PDIF) at a sampling frequency of 48kHz, which is processed by the digital audio receiver as I 2 S-format data, and the filtering-free pulse width modulator based on the spread spectrum modulation method provided by the invention realized by FPGA is used for the I 2 And the USB module transmits the rear edge three-level UPWM signal to a computer for spectrum analysis.
In the case that the test signal is a single-frequency sinusoidal digital signal with the amplitude of 0 dBus, the frequency of 6.6kHz, the precision of 24-bit and the sampling frequency of 48kHz, the baseband frequency spectrum of the three-level UPWM signal output by a filtering-free pulse width modulator without a spread spectrum modulation function (the PRF of the two-level rear edge UPWM signal output by a rear edge UPWM generator is constant at 384 kHz) is shown in the figure 10; the baseband spectrum of the three-level UPWM signal output by the filtering-free pulse width modulator based on the spread spectrum modulation method provided by the invention is shown in figure 11; the high-frequency spectrum of the three-level UPWM signal output by the filtering-free pulse width modulator without the spread spectrum modulation function is shown in figure 12; the high frequency spectrum of the three-stage UPWM signal output by the filtering-free pulse width modulator based on the spread spectrum modulation method provided by the invention is shown in figure 13.
As can be seen from fig. 10 and fig. 11, when the spread spectrum modulation method provided by the present invention is used, the spectrum of the three-level UPWM signal output by the system has a lower amplitude at the third harmonic of the input signal, and the THD of the system is 0.009%, which is smaller than the THD (0.094%) of the three-level UPWM signal output by the system without the spread spectrum modulation function. As can be seen from fig. 12 and fig. 13, when the spread spectrum modulation method provided by the present invention is used, the peak amplitude of the third-level UPWM signal spectrum output by the system in the out-of-band is-28.25 dBFS, and when the system does not use the spread spectrum modulation method, the peak amplitude of the third-level UPWM signal spectrum output by the system in the out-of-band is-10.5 dBFS. Compared with a system without a spread spectrum modulation function, the out-of-band spectrum peak amplitude of the three-level UPWM signal output by the system based on the spread spectrum modulation method provided by the invention is reduced by 17.75dB. Therefore, the spread spectrum modulation method provided by the invention can well perform amplitude reduction treatment on the energy peak on the high-frequency component of the UPWM signal output by the filter-free digital D-type audio power amplifier, and simultaneously reduces the output THD of the power amplifier, and reduces the distortion introduced by the UPWM while reducing the EMI of the power amplifier.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.

Claims (10)

1. The three-frequency pseudo-random variable spread spectrum modulation method is characterized by comprising the following steps:
step one: the interpolation filter is utilized to amplify the sampling frequency f of the input signal o Lifting N times to sampling frequency f s And according to the sampling frequency f s Determining the intermediate frequency f of the required three sampling frequencies c Wherein f c ＝f s Q, q is an integer less than N;
step two: based on the power amplification system master clock signal clk_m and the determined intermediate frequency f by using frequency synthesis technology c Determining two other sampling frequencies f cs And f c1 Wherein f cs For the smallest sampling frequency among the three,
Figure QLYQS_1
N s ＝p+v，f c1 for the maximum sampling frequency of the three>
Figure QLYQS_2
N1＝p-v，v∈[1，p-1]And v is an integer number of times,
Figure QLYQS_3
f clk_m for the frequency of the master clock signal clk_m, m is the number of stages of a uniform sampling pulse width modulation generator, "uniform sampling pulse width modulation" abbreviated as "UPWM";
step three: constructing a variable-magnification number extractor, and constructing a finite state machine and a pseudo-random number generator consisting of a 2 n-level linear feedback shift register in the variable-magnification number extractor, wherein the finite state machine obtains a final state uniquely corresponding to the n-bit pseudo-random number random_num generated by the pseudo-random number generator; the initial state of the finite state machine is S 0 And (3) sequentially taking the value of a one-bit variable K from the highest bit to the lowest bit of the n-bit pseudo-random number, determining the next state by a finite state machine according to the value of K and the current state until the lowest bit of the pseudo-random number is taken by K, and outputting a final state, wherein the finite state machine has three final states respectively: s is S 0 、S 1 、S 2 ；
Step four: constructing a threshold generator, a first counter and a clock generator in the variable multiplier decimator; the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and three values are respectively: t is t s 、t c 、t 1 The method comprises the steps of carrying out a first treatment on the surface of the The first counter is an up-counter which counts the rising edge of the clock signal clk_bas, which is divided by the main clock signal clk_m, at a frequency f clk_bas ＝f s When the counter value is zero, the output clock signal clk_s of the clock generator is set at high level, and when the counter value cou_val is equal to the current threshold value
Figure QLYQS_4
At the same time, the clock signal clk_s is set to low level, whenWhen the value cou_val of the counter is the same as the current threshold thr_val, the clock signal clk_s is again set to high level, and the counter is cleared [ the same ] ] Rounding up Rounding off decimal places; the clock generator generates a new clock signal clk_s with three frequencies according to the threshold thr_val, the counter value cou_val and the clock signal clk_bas;
step five: a data processing module is built in the variable multiple decimator, and when the rising edge of the clock signal clk_s is detected, the value of the current sampling point is output, so that the single sampling frequency signal data output by the interpolation filter is processed into a signal data_t with three sampling frequencies;
step six: when detecting the rising edge of a clock signal clk_s, a correction module is constructed, the amplitude of the current sampling point in an input signal data_t is recalculated and assigned by using a correction algorithm, a new signal data_t' is output, so that a UPWM signal obtained after the new signal passes through a rear edge UPWM generator approximates a natural sampling pulse width modulation signal in a time domain, and the natural sampling pulse width modulation is abbreviated as NPWM;
step seven: constructing an m-level trailing edge UPWM generator, constructing a second counter in the m-level trailing edge UPWM generator, wherein the counter is also an up-counter which counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared;
Step eight: an amplitude adjustment module is constructed in the m-level back edge UPWM generator, and as the frequency of the clock signal clk_s input by the back edge UPWM generator and the sampling frequency of the digital audio signal data_t ' input by the back edge UPWM generator are synchronous and variable, the duty ratio of the back edge UPWM signal output by the back edge UPWM generator is kept unchanged compared with that of the back edge UPWM signal which is not spread, the module judges the frequency of the current clk_s according to the input clock signal clk_s and the threshold signal thr_val through the current thr_val value, thereby adjusting the amplitude of each sampling point of the digital audio signal data_t ' input by the back edge UPWM generator in real time and outputting a new signal data_t ';
step nine: constructing a comparator in the m-level trailing edge UPWM generator, and judging whether the output value count of the second counter in the step seven is larger than a threshold y or not at the rising edge of each clock signal clk_m by the comparator; if yes, the comparator outputs 0, otherwise outputs 1, so that a trailing edge two-level UPWM signal with three sampling frequencies is output; the current sampling point amplitude of the output signal data_t' of the threshold y and the amplitude adjustment module is equal.
2. The method according to claim 1, wherein in the third step, the 2 n-stage linear feedback shift register is composed of 2n D flip-flops and gates, and is controlled by a clock signal clk_r and a reset signal reset, the clock signal clk_r is obtained by dividing a frequency of a master clock signal clk_m, and the frequency f thereof clk_r Greater than the maximum f of three sampling frequencies c1 The output values of the last n D flip-flops of the 2 n-level linear feedback shift register form an n-bit pseudo random number rand_num after each clock period of clk_r;
in the third step, the state decision rule of the finite state machine is: if the current state is S 0 K is 0, the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 0 K takes a value of 1, then the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K is 0, the next state is S 2 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 1 K takes a value of 1, then the next state is S 0 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K is 0, the next state is S 1 The method comprises the steps of carrying out a first treatment on the surface of the If the current state is S 2 K takes a value of 1, then the next state is S 2 。
3. The method of three-frequency pseudo-random variable spread spectrum modulation according to claim 1, wherein in the fourth step, the rule for generating the threshold thr_val by the threshold generator is: at the final state corresponding to the current pseudo random number S 0 At the time, the threshold thr_val is t 1 The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S 1 At the time, the threshold thr_val is t c The method comprises the steps of carrying out a first treatment on the surface of the At the final state corresponding to the current pseudo random number S 2 At the time, the threshold thr_val is t s ；
In the fourth step, the generation rule of the clock signal clk_s is: at the current threshold thr_val is t 1 At the present period, the clock signal clk_s has a frequency f cs The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t c At the present period, the clock signal clk_s has a frequency f c The method comprises the steps of carrying out a first treatment on the surface of the At the current threshold thr_val is t s At the present period, the clock signal clk_s has a frequency f c1 。
4. The method according to claim 1, wherein in the sixth step, the correction algorithm used in the correction module is: suppose F 1 (x 1 ，in 1 )、F 2 (x 2 ，in 2 ) And F 3 (x 3 ，in 3 ) For sampling points of adjacent three input modulated signals, where F 2 F as the current sampling point 1 For the previous sampling point, F 3 For the latter sampling point, in 1 、in 2 Sum in 3 The amplitudes of the three sampling points are respectively,
Figure QLYQS_6
x 2 ＝0，
Figure QLYQS_8
f 1 and f 2 Respectively are sampling points F 1 And F 2 The corresponding sampling frequency; normalizing the amplitude values of the carrier signal and the sampling point to make the minimum value be 0 and the maximum value be 1, and then at the sampling point F 2 And F 3 The saw-tooth wave carrier wave waveform expression between the two is:
Figure QLYQS_10
Solving the intersection point of the carrier wave and a second-order Newton interpolation curve constructed by the three sampling points, namely, the amplitude of a pseudo natural sampling point to replace the amplitude of a current sampling point, and inputting the amplitude of the current sampling point to a rear edge UPWM generator, so that the generated rear edge UPWM signal approximates to a rear edge NPWM signal in a time domain, thereby reducing the harmonic distortion of the signal; the two parts The expression of the function of the order Newton interpolation curve is: in p (x)＝λ 1 +λ 2 ·(x-x 1 )+λ 3 ·(x-x 1 ) X, where λ 1 ＝in 1 ，
Figure QLYQS_7
Let F (x) =in p (x) -cw (x) =0, the initial value of x is set to +.>
Figure QLYQS_9
The approximate solution of F (x) can be determined by Newton-Laportson iteration>
Figure QLYQS_11
Wherein->
Figure QLYQS_12
in′ p (x)＝λ 2 +λ 3 ·x+λ 3 ·(x-x 1 ) The method comprises the steps of carrying out a first treatment on the surface of the Finally, x is b Substituting into the carrier wave waveform expression to obtain the pseudo-natural sampling point amplitude +.>
Figure QLYQS_5
From in b The trailing edge UPWM signal generated by the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain.
5. The method of claim 1, wherein in the eighth step, the amplitude adjustment rule of the amplitude adjustment module is: at the current threshold signal thr_val is t 1 When the frequency of the current clock signal clk_s is f cs The current sampling point amplitude adjustment formula is:
Figure QLYQS_13
at the current threshold signal thr_val is t c When the frequency of the current clock signal clk_s is f c The current sampling point amplitude adjustment formula is:
Figure QLYQS_14
at the current threshold signal thr_val is t s When the frequency of the current clock signal clk_s is f c1 The current sampling point amplitude adjustment formula is:
Figure QLYQS_15
Wherein val_data' is the original amplitude value of the current sampling point.
6. A filter-free pulse width modulator constructed by a three-frequency pseudo-random variable spread spectrum modulation method according to any one of the preceding claims 1-5, said filter-free pulse width modulator comprising an interpolation filter, a variable-multiple decimator, a negating module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first trailing edge UPWM generator and a second trailing edge UPWM generator; the digital audio input signal is connected with an interpolation filter, the interpolation filter is connected with a variable-power extractor, the variable-power extractor is respectively connected with a first correction module and an inversion module, the inversion module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first back edge UPWM generator, the second Sigma-Delta modulator is connected with a second back edge UPWM generator, and two paths of back edge UPWM signals output by the first back edge UPWM generator and two paths of back edge UPWM signals output by the second back edge UPWM generator are connected with an H bridge power level of a power amplifier.
7. The filter-less pulse width modulator of claim 6, wherein the interpolation filter is a 32-fold interpolation filter, the first Sigma-Delta modulator and the second Sigma-Delta modulator are identical and each an 8-order feedforward interpolation Sigma-Delta modulator, the first Sigma-Delta modulator and the second Sigma-Delta modulator each convert a 24-bit high-precision input signal to a low-precision signal of 7 bits 65 quantization levels such that the first trailing edge UPWM generator and the second trailing edge UPWM generator output 64-level trailing edge UPWM signals.
8. The filter-less pulse width modulator of claim 6, wherein the variable multiple decimator comprises a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine, and a data processing module; the system master clock signal is connected with the variable-multiple number extractor; the clock signal clk_r is respectively connected with the pseudo-random number generator and the finite state machine, and is obtained by dividing the frequency f of the clock signal clk_r by the main clock signal clk_m clk_r Greater than the maximum f of three sampling frequencies c1 The pseudo-random number generator is connected with the finite state machine, the finite state machine is connected with the threshold generator, and the threshold generator determines a corresponding threshold thr_val according to the final state output by the finite state machine; the clock signal clk_bas is respectively connected with a pseudo-random number generator, a finite state machine, a first counter and a clock generator, the first counter and the threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal clk_s by utilizing a frequency synthesis technology; the clock generator and the input signal data are both connected with the data processing module, and the data processing module extracts the input digital audio signal data according to the clock signal clk_s generated by the clock generator, so that the digital audio signal data_t with three sampling frequencies is output.
9. The filter-less pwm according to claim 8, wherein the pseudo-random number generator is mainly composed of a 16-stage linear feedback shift register, and the linear feedback shift register generates an 8-bit pseudo-random number and inputs it to the finite state machine every time a clk_r period passes by setting an initial state to the linear feedback shift register; the finite state machine calculates a final state corresponding to the current pseudo-random number according to the current pseudo-random number and inputs the final state to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state;
the first counter counts the rising edge of the clock signal clk_bas, and when the rising edge of clk_bas is detected, the value of the first counter is increased by 1; when detecting that the value of the counter is equal to the current threshold thr_val, resetting the counter;
the first and second correction modules are identical, and recalculate the amplitude of each sampling point by using a correction technology according to the threshold signal thr_val, the clock signal clk_s and the digital audio signal data_t with three sampling frequencies output by the variable-multiple decimator, so as to output a new signal data_t'.
10. The filter-less pulse width modulator of claim 8, wherein the first trailing edge UPWM generator and the second trailing edge UPWM generator are identical comprising an amplitude adjustment module, a second counter, a comparator, and an inverter; the clock signal clk_s is respectively connected with the second counter and the amplitude adjustment module, the digital audio signal data_t' is connected with the amplitude adjustment module, the clock signal clk_m is respectively connected with the second counter and the comparator, the amplitude adjustment module and the second counter are respectively connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the inverter and then is output; the amplitude adjustment module calculates and adjusts the amplitude of the current sampling point according to an adjustment rule; the second counter counts the rising edge of the clock signal clk_m, and when the rising edge of the clock signal clk_s is detected, the counter is cleared; the comparator compares the counter value with the adjusted signal amplitude, one path of the signal is directly output as a rear edge UPWM signal, and the other path of the signal is inverted through the inverter and then outputs the rear edge UPWM signal.
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