CN110957983A - Three-frequency pseudorandom variable spread spectrum modulation method and filtering-free pulse width modulator constructed by same - Google Patents

Three-frequency pseudorandom variable spread spectrum modulation method and filtering-free pulse width modulator constructed by same Download PDF

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CN110957983A
CN110957983A CN201911252480.XA CN201911252480A CN110957983A CN 110957983 A CN110957983 A CN 110957983A CN 201911252480 A CN201911252480 A CN 201911252480A CN 110957983 A CN110957983 A CN 110957983A
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于泽琦
白鸽
张珂
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Zhengzhou University of Light Industry
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    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
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Abstract

The invention has proposed a three frequency pseudo-random variable spread spectrum modulation method and exempts from the pulse width modulator of filtering constructed with this method, this method utilizes the frequency synthesis technology at first, confirm three sampling frequencies; then after oversampling the input audio signal, sampling the audio signal by using a variable multiple decimator to generate a digital signal having the three sampling frequencies, and simultaneously generating a synchronous clock signal clk _ s, then pre-correcting the digital signal by using a correction module to make a UPWM signal generated after the digital signal passes through a back edge UPWM generator approximate to an NPWM signal in a time domain, and finally generating the UPWM signal having three pulse repetition frequencies by the back edge UPWM generator; meanwhile, a corresponding filtering-free pulse width modulator is designed based on the spread spectrum modulation method. The invention can obviously reduce the amplitude of the high-frequency component of the UPWM signal output by the power amplifier, thereby reducing EMI and ensuring that the power amplifier has lower THD.

Description

Three-frequency pseudorandom variable spread spectrum modulation method and filtering-free pulse width modulator constructed by same
Technical Field
The invention relates to the field of filtering-free digital D class audio power amplifiers, in particular to a three-frequency pseudo-random variable spread spectrum modulation method for a filtering-free digital D class audio power amplifier.
Background
Digital class-D audio power amplifiers are generally applied to current consumer electronics products due to the advantages of high power efficiency, convenience in interface with digital audio sources, small size and the like. The structural schematic diagram of a traditional digital class-D audio power amplifier is shown in fig. 1, and comprises a pulse width modulator, a power stage and an LC analog low-pass filter which are connected in sequence. In a traditional digital class-D audio power amplifier, a digital audio signal input by the power amplifier is firstly modulated into a Pulse Width Modulation (PWM) signal through a pulse width modulator, then is amplified by a power-level high-power transistor, and finally is used for filtering a high-frequency component through an inductance-capacitance (LC) analog low-pass filter to drive a loudspeaker to produce sound. Because the LC analog low-pass filter occupies about 75% of the volume of the whole power amplifier system and consumes about 30% of the cost, the volume and the cost of the power amplifier system are greatly increased, and the development trend of miniaturization and portability of current audio-visual products is not met, so that the filtering-free digital D-class audio power amplifier appears and becomes a research hotspot.
The structure schematic diagram of the filtering-free digital class-D audio power amplifier is shown in figure 2, and mainly comprises a filtering-free pulse width modulator and an H bridge type power stage. The filter-free Pulse Width modulator mainly comprises an interpolation filter, a negation module, a Sigma-Delta modulator and a Uniform sampling Pulse Width Modulation (UPWM) generator, and converts a digital audio signal into four paths of UPWM signals by utilizing an oversampling technology, a quantization noise shaping technology and a UPWM technology under the condition of basically keeping the baseband information of an input signal unchanged, wherein the four paths of UPWM signals drive an H bridge type power stage and form a three-level UPWM signal on a loudspeaker load. Because the voltage at two ends of the power amplifier load is equal to zero volt in most of time in each switching period by the three-level UPWM, the current flowing through the load is greatly reduced, and the power amplifier reduces the dependence on the LC analog low-pass filter in the aspect of efficiency. However, the filtering-free digital class D audio amplifier output signal has high energy at the Pulse Repetition Frequency (PRF) and its harmonics, and these high Frequency component energies will cause the power amplifier output signal to generate serious electromagnetic Interference (EMI). Therefore, in order to further improve the practicability of the filtering-free digital class D audio power amplifier, a special method is required to reduce the high-frequency energy peak of the output signal of the power amplifier, so as to reduce the EMI of the power amplifier. The EMI suppression method for class D audio power amplifier is mainly divided into two categories: (1) suppressing from the source, such as adopting a soft switching technology, a spread spectrum modulation technology and the like; (2) and (4) suppressing transmission paths, such as board-level system layout and wiring optimization design, shielding technology and the like. The spread spectrum modulation technology is relatively simple to implement and easy to control, so that the spread spectrum modulation technology becomes a main method for solving the EMI problem of the class D audio power amplifier.
The spread spectrum modulation method for class D audio power amplifier that has been published at present mainly includes: low power frequency modulation (Yeh M L, Liou W R, Hsieh H P, et al. an electronic interference (EMI) reduced high-efficiency switching power amplifiers [ J ]. IEEE Transactions on Power Electronics,2010,25(3): 710-, auer M. digital pulse-width modulator with a spread-spread emission reduction. e & i Elektro technikung information, 2018,135(1): 48-53), and the like. The low-power-consumption frequency modulation method changes the PRF of the power amplifier PWM signal in real time by constructing an ultra-low-power-consumption spread spectrum clock generator, reduces the EMI of the power amplifier and simultaneously well keeps the high efficiency of the power amplifier, but the method needs an analog circuit to realize or needs an analog input signal to participate in modulation, so the method is only suitable for simulating a class D audio power amplifier. The 'PWM Chopping' module method is constructed, and the noise shaping function of a zero-input Sigma-Delta modulator is utilized to carry out frame-by-frame control on output PWM signals, so that common-mode high-frequency peaks at two ends of a power amplifier load are reduced, but a system needs higher main clock frequency. The random winding pulse position modulation method randomizes the position of each pulse of the UPWM signal in the current switching period to realize frequency spreading, and is based on a two-stage PWM technology, so that the power amplifier has low EMI (electro-magnetic interference), but the efficiency is greatly reduced. The multi-frequency pulse modulation method controls the PRF of the output signal of the UPWM generator through two reversible counters, thereby achieving the purpose of frequency spreading.
Disclosure of Invention
Aiming at the defects of the existing spread spectrum modulation method, the invention provides the spread spectrum modulation method for the filtering-free digital D class audio power amplifier, which is easy to realize, and can greatly reduce the amplitude of high-frequency components of UPWM signals output by the power amplifier while reducing the THD of a system, thereby achieving the purpose of reducing EMI. The method comprises the following implementation steps:
the method comprises the following steps: using interpolation filter to sample frequency f of power amplifier input signaloIncrease N times to sampling frequency fsAnd according to the sampling frequency fsDetermining the intermediate frequency f of the required three sampling frequenciescWherein f isc＝fsQ, q is an integer less than N;
step two: by using frequency synthesis technology, according to the main clock signal clk _ m of the power amplifier system and the determined intermediate frequency fcDetermining two further sampling frequencies fcsAnd fclWherein f iscsThe minimum sampling frequency of the three,
Figure BDA0002309413850000031
Ns＝p+v，fclthe maximum sampling frequency of the three is,
Figure BDA0002309413850000032
N1＝p-v，v∈[1，p-1]and v is an integer,
Figure BDA0002309413850000041
fclk_mis the frequency of the main clock signal clk m, m being the number of stages of the UPWM generator;
step three: constructing a variable multiple extractor, constructing a finite state machine and a pseudo-random number generator consisting of 2n stages of linear feedback shift registers in the variable multiple extractor, wherein the finite state machine utilizes an n-bit pseudo-random number rand _ num generated by the pseudo-random number generator to obtain a final state uniquely corresponding to the n-bit pseudo-random number rand _ num; the initial state of the finite state machine is S0And sequentially taking values from the highest bit to the lowest bit of the n-bit pseudo random number by a one-bit variable K, determining the next state by a finite state machine according to the value K and the current state until the value K is the lowest bit of the pseudo random number, and outputting a final state, wherein the finite state machine has three final states: s0、 S1、S2；
Step four: constructing a threshold generator, a first counter and a clock generator in a variable multiple extractor; the threshold generator determines a threshold thr _ val corresponding to the final state output by the finite-state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and has three values: t is ts、tc、t1(ii) a The first counter is an up counter which counts the rising edges of the clock signal clk _ bas divided by the main clock signal clk _ m at a frequency fclk_bas＝fsWhen the count value is zero, the output clock signal clk _ s of the clock generator is set to high level, and when the counter value cou _ val is equal to the current threshold value
Figure BDA0002309413850000042
When the same, the clock signal clk _ s is set to a low level, and when the value cou _ val of the counter is the same as the current threshold thr _ val, the clock signal clk _ s is set to a high level again and the counter is cleared, respectively]Get the wholeRounding off the decimal place; the clock generator generates a new clock signal according to the threshold thr _ val, the counter value cou _ val, and the clock signal clk _ basA clock signal clk _ s having three frequencies;
step five: constructing a data processing module in the variable multiple extractor, and outputting the value of the current sampling point when detecting the rising edge of the clock signal clk _ s, so as to process the single sampling frequency signal data output by the interpolation filter into a signal data _ t with three sampling frequencies;
step six: constructing a correction module, recalculating and assigning the amplitude of the current sampling point in the input signal data _ t by using a correction algorithm when the rising edge of the clock signal clk _ s is detected, and outputting a new signal data _ t' to enable a UPWM (Pulse Width Modulation) signal obtained after the signal passes through a back edge UPWM generator to approximate to a Natural-sampling Pulse Width Modulation (NPWM) signal in a time domain;
step seven: constructing an m-level back edge UPWM generator, constructing a second counter in the m-level back edge UPWM generator, wherein the counter is also an adding counter which counts the rising edge of a clock signal clk _ m, and clearing the counter when the rising edge of a clock signal clk _ s is detected;
step eight: an amplitude adjusting module is constructed in the m-level back edge UPWM generator, because the frequency of a clock signal clk _ s input by the back edge UPWM generator and the sampling frequency of a digital audio signal data _ t ' input by the back edge UPWM generator are synchronously variable, in order to keep the duty ratio of the back edge UPWM signal output by the back edge UPWM generator unchanged compared with the non-spread spectrum, the module judges the frequency of the current clk _ s according to the input clock signal clk _ s and a threshold signal thr _ val and through the current thr _ val value, so that the amplitudes of sampling points of the digital audio signal data _ t ' input by the back edge UPWM generator are adjusted in real time, and a new signal data _ t ' is output;
step nine: constructing a comparator in the m-stage back edge UPWM generator, and judging whether the output value count of the second counter is greater than the threshold y in the seventh step by the comparator at the rising edge of each clock signal clk _ m; if yes, the output of the comparator is 0, otherwise, the output of the comparator is 1, and therefore a back edge two-level UPWM signal with three sampling frequencies is output; the threshold value y is equal to the amplitude of the current sampling point of the output signal data _ t' of the amplitude adjusting module.
In the third step, the 2 n-stage linear feedback shift register consists of 2n D triggers and a plurality of gate circuits, and is controlled by a clock signal clk _ r and a reset signal reset, wherein the clock signal clk _ r is obtained by dividing the frequency of a main clock signal clk _ m, and the frequency f of the clock signal clk _ r is fclk_rGreater than the maximum value f of three sampling frequenciesc1Every time a clock cycle of clk _ r passes, the output values of the last n D flip-flops of the 2 n-stage linear feedback shift register form an n-bit pseudo random number rand _ num.
In the third step, the state decision rule of the finite state machine is as follows: if the current state is S0And K is 0, the next state is S0(ii) a If the current state is S0And K is 1, the next state is S1(ii) a If the current state is S1And K is 0, the next state is S2(ii) a If the current state is S1And K is 1, the next state is S0(ii) a If the current state is S2And K is 0, the next state is S1(ii) a If the current state is S2And K is 1, the next state is S2。
In the fourth step, the rule for the threshold generator to generate the threshold thr _ val is: at the current pseudo random number corresponding to the final state S0When the threshold thr _ val is t1(ii) a At the current pseudo random number corresponding to the final state S1When the threshold thr _ val is tc(ii) a At the current pseudo random number corresponding to the final state S2When the threshold thr _ val is ts。
In the fourth step, the generation rule of the clock signal clk _ s is: at the current threshold thr _ val of t1While the clock signal clk _ s has a frequency f in the current cyclecs(ii) a At the current threshold thr _ val of tcWhile the clock signal clk _ s has a frequency f in the current cyclec(ii) a At the current threshold thr _ val of tsWhile the clock signal clk _ s has a frequency f in the current cyclec1。
In the sixth step, the correction algorithm used in the correction module is as follows: suppose F1(x1，in1)、 F2(x2，in2) And F3(x3，in3) For three adjacent samples of the input modulation signal, where F2For the current sampling point, F1For the previous sampling point, F3For the next sampling point, in1、in2And in3The amplitudes of the three sampling points are respectively,
Figure BDA0002309413850000071
x2＝0，
Figure BDA0002309413850000072
f1and f2Are respectively sampling point F1And F2The corresponding sampling frequency; normalizing the amplitudes of the carrier signal and the sampling point to ensure that the minimum value is 0 and the maximum value is 1, and then, at the sampling point F2And F3The expression of the carrier waveform of the sawtooth wave between the two is as follows:
Figure BDA0002309413850000073
solving the amplitude of the intersection point (pseudo-natural sampling point) of the carrier and a second-order Newton interpolation curve constructed by the three sampling points to replace the amplitude of the current sampling point and inputting the amplitude into the back edge UPWM generator, so that the generated back edge UPWM signal is approximate to the back edge NPWM signal in the time domain, and the harmonic distortion of the signal is reduced; the second-order Newton interpolation curve function expression is as follows: inp(x)＝λ1+λ2·(x-x1)+λ3·(x-x1) X, wherein λ1＝in1，
Figure BDA0002309413850000074
Let F (x) equal to inp(x) -cw (x) 0, setting x to an initial value
Figure BDA0002309413850000075
Approximate solution of F (x) can be obtained by Newton-Raphson iteration method
Figure BDA0002309413850000076
Wherein
Figure BDA0002309413850000077
in′p(x)＝λ2+λ3·x+λ3·(x-x1) (ii) a Finally, x is putbSubstituting into carrier waveform expression to obtain pseudo-natural sampling point amplitude
Figure BDA0002309413850000081
From inbThe trailing edge UPWM signal generated by the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain.
In the step eight, the amplitude adjustment rule of the amplitude adjustment module is as follows: when the current threshold signal thr _ val is t1When the current clock signal clk s has a frequency fcsThe adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000082
when the current threshold signal thr _ val is tcWhen the current clock signal clk s has a frequency fcThe adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000083
when the current threshold signal thr _ val is tsWhen the current clock signal clk s has a frequency fc1The adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000084
wherein, val _ data' is the original amplitude of the current sampling point.
The filtering-free pulse width modulator is constructed by utilizing the three-frequency pseudorandom variable spread spectrum modulation method and comprises an interpolation filter, a variable multiple extractor, a negation module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first back edge UPWM generator and a second back edge UPWM generator; the digital audio input signal is connected with an interpolation filter, the interpolation filter is connected with a variable multiple extractor, the variable multiple extractor is respectively connected with a first correction module and a negation module, the negation module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first rear edge UPWM generator, the second Sigma-Delta modulator is connected with a second rear edge UPWM generator, and two rear edge UPWM signals output by the first rear edge UPWM generator and two rear edge UPWM signals output by the second rear edge UPWM generator are both connected with an H bridge type power stage of a power amplifier.
The interpolation filter is a 32-fold interpolation filter, the first Sigma-Delta modulator and the second Sigma-Delta modulator are the same and are both 8-order feedforward interpolation Sigma-Delta modulators, and both the first Sigma-Delta modulator and the second Sigma-Delta modulator convert the 24-bit high-precision input signal into 7-bit low-precision signals with 65 quantization levels so that the first back edge UPWM generator and the second back edge UPWM generator output 64-level back edge UPWM signals.
The variable multiple extractor comprises a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine and a data processing module; the system main clock signal is connected with the variable multiple extractor; a clock signal clk r is connected to the pseudo-random number generator and the finite state machine, respectively, the clock signal clk r being divided by a main clock signal clk m at a frequency fclk_rGreater than the maximum value f of three sampling frequenciesclThe pseudo-random number generator is connected with the finite-state machine, the finite-state machine is connected with the threshold generator, and the threshold generator determines a threshold thr _ val corresponding to the final state output by the finite-state machine; the clock signal clk _ bas is respectively connected with the pseudo-random number generator, the finite-state machine, the first counter and the clock generator, the first counter and the threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal clk _ s by using a frequency synthesis technology; the clock generator and the input signal data are both connected with the data processing module, and the data processing module generates a clock signal clk _ s pair according to the clock generatorThe input digital audio signal data is decimated, thereby outputting a digital audio signal data _ t having three sampling frequencies.
The pseudo-random number generator mainly comprises a 16-stage linear feedback shift register, an initial state is set for the linear feedback shift register, and the linear feedback shift register generates an 8-bit pseudo-random number and inputs the pseudo-random number to the finite-state machine every clk _ r period; and the finite state machine calculates a final state corresponding to the current pseudo-random number according to the current pseudo-random number and inputs the final state to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state.
The first counter counts rising edges of a clock signal clk _ bas, and when the rising edges of the clk _ bas are detected, the value of the counter is increased by 1; when the counter value is detected to be equal to the current threshold thr _ val, the counter is cleared.
The first and second correction modules are the same, and both calculate the amplitude of each sampling point again by using the correction technique according to the threshold signal thr _ val, the clock signal clk _ s and the digital audio signal data _ t with three sampling frequencies output by the variable multiple decimator, thereby outputting a new signal data _ t'.
The first back edge UPWM generator is the same as the second back edge UPWM generator, and comprises an amplitude adjusting module, a second counter, a comparator and an inverting module; the clock signal clk _ s is respectively connected with the second counter and the amplitude adjusting module, the digital audio signal data _ t' is connected with the amplitude adjusting module, the clock signal clk _ m is respectively connected with the second counter and the comparator, the amplitude adjusting module and the second counter are respectively connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the negating module and then output; the amplitude adjusting module calculates and adjusts the amplitude of the current sampling point according to an adjusting rule; the second counter counts the rising edge of the clock signal clk _ m, and when the rising edge of the clock signal clk _ s is detected, the counter is cleared; and the comparator compares the counter value with the adjusted signal amplitude, one path of signal is directly output as a back edge UPWM signal, and the other path of signal is inverted by the inverting module and then outputs the back edge UPWM signal.
Compared with the prior art, the invention has the beneficial effects that:
1. based on a filtering-free modulation architecture, a back edge UPWM technology and a pseudorandom spread spectrum modulation technology, the invention samples an input audio signal into an audio signal with three sampling frequencies by constructing a variable multiple extractor, synthesizes a clock signal synchronous with a digital audio signal, and then corrects the amplitude of each sampling point by using a correction module to reduce the baseband distortion introduced in the UPWM process, thereby reducing the high-frequency peak amplitude of the output UPWM signal and simultaneously well ensuring to introduce less harmonic distortion so as to achieve the purpose of reducing EMI power amplification and THD.
2. The method provided by the invention can be realized by a full digital circuit and can be conveniently applied to the existing filtering-free digital D class audio power amplifier system.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional digital class D audio power amplifier;
FIG. 2 is a schematic structural diagram of a filtering-free digital class D audio power amplifier;
FIG. 3 is a schematic diagram of a filter-free PWM according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a variable multiplier extractor according to the present invention;
FIG. 5 is a schematic diagram of a linear feedback shift register according to the present invention;
FIG. 6 is a state transition diagram of the finite state machine of the present invention;
FIG. 7 is a schematic diagram of a calibration algorithm of the present invention;
FIG. 8 is a back edge UPWM generator configuration of the present invention;
FIG. 9 is a schematic diagram of a test system of the present invention;
FIG. 10 is a baseband frequency spectrum plot of a trailing edge three level UPWM signal output by the test system of FIG. 9 using an unfiltered pulse width modulator without spread spectrum modulation;
FIG. 11 is a baseband frequency spectrum diagram of a back edge three level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator based on the proposed spread spectrum modulation method of the present invention;
FIG. 12 is a high frequency spectrum plot of a trailing edge three level UPWM signal output by the test system of FIG. 9 using an unfiltered pulse width modulator without amplification modulation;
FIG. 13 is a high frequency spectrum plot of a back edge three level UPWM signal output by the test system of FIG. 9 using a filter-free pulse width modulator based on the proposed spread spectrum modulation method of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
A three-frequency pseudorandom variable spread spectrum modulation method for a filtering-free digital D-class audio power amplifier comprises the following steps.
The first step is as follows: using interpolation filter to sample frequency f of power amplifier input signaloIncrease N times to sampling frequency fsAnd according to the sampling frequency fsDetermining the intermediate frequency f of the required three sampling frequenciescWherein f isc＝fsQ, q is an integer less than N;
the second step is that: by using frequency synthesis technology, according to the main clock signal clk _ m of the power amplifier system and the determined intermediate frequency fcDetermining two further sampling frequencies fcsAnd fc1Wherein, in the step (A),fcsthe minimum sampling frequency of the three,
Figure BDA0002309413850000121
Ns＝p+v，fc1the maximum sampling frequency of the three is,
Figure BDA0002309413850000122
N1＝p-v，v∈[1，p-1]and v is an integer,
Figure BDA0002309413850000123
fclk_mis the frequency of the main clock signal clk _ m, m being the number of stages of the UPWM generator;
the third step: constructing a variable multiple extractor, constructing a finite state machine and a pseudo-random number generator consisting of 2n stages of linear feedback shift registers in the variable multiple extractor, wherein the finite state machine utilizes an n-bit pseudo-random number rand _ num generated by the pseudo-random number generator to obtain a final state uniquely corresponding to the n-bit pseudo-random number rand _ num; the 2 n-stage linear feedback shift register consists of 2n D triggers and a plurality of gate circuits, and is controlled by a clock signal clk _ r and a reset signal reset, wherein the clock signal clk _ r is obtained by dividing the frequency of a main clock signal clk _ m, and the frequency f of the clock signal clk _ r is fclk_rGreater than the maximum value f of three sampling frequenciesc1Every time a clock period of clk _ r passes, the output values of the last n D flip-flops of the 2 n-stage linear feedback shift register form an n-bit pseudo-random number rand _ num; the initial state of the finite state machine is S0And sequentially taking values from the highest bit to the lowest bit of the n-bit pseudo random number by a one-bit variable K, determining the next state by a finite state machine according to the value K and the current state until the value K is taken to the lowest bit of the pseudo random number, and outputting a final state, wherein the finite state machine has three final states: s0、S1、S2(ii) a The state decision rule of the finite state machine is as follows: if the current state is S0And K is 0, the next state is S0(ii) a If the current state is S0And K is 1, the next state is S1(ii) a If the current state is S1And K is 0, the next state is S2(ii) a If the current state isIs S1And K is 1, the next state is S0(ii) a If the current state is S2And K is 0, the next state is S1(ii) a If the current state is S2And K is 1, the next state is S2；
The fourth step: constructing a threshold generator, a first counter and a clock generator in a variable multiple extractor; the threshold generator determines a threshold thr _ val corresponding to the final state output by the finite-state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and has three values: t is ts、tc、t1(ii) a (ii) a The threshold thr _ val is determined by the following rule: at the current pseudo random number corresponding to the final state S0When the threshold thr _ val is t1(ii) a At the current pseudo random number corresponding to the final state S1When the threshold thr _ val is tc(ii) a At the current pseudo random number corresponding to the final state S2When the threshold thr _ val is ts(ii) a The first counter is an adding counter which counts the rising edge of the clock signal clk _ bas, when the count value is zero, the clock signal clk _ s is set to high level, and when the value cou _ val of the counter is equal to the current threshold value
Figure BDA0002309413850000141
When the same, the clock signal clk _ s is set to a low level, and when the value cou _ val of the counter is the same as the current threshold thr _ val, the clock signal clk _ s is set to a high level again and the counter is cleared, respectively]Get the wholeRounding off the decimal place; the clock generator generates a new clock signal clk _ s with three frequencies (f, respectively) according to the threshold thr _ val, the counter value cou _ val, and the clock signal clk _ bascs、fcAnd fc1) Wherein the clock signal clk _ bas is divided by the main clock signal clk _ m, and the frequency fclk_bas＝fs(ii) a The generation rule of the clock signal clk _ s is: at the current threshold thr _ val of t1While the clock signal clk _ s has a frequency f in the current cyclecs(ii) a At the current threshold thr _ val of tcAt the frequency of the current cycle of the clock signal clk _ sIs fc(ii) a At the current threshold thr _ val of tsWhile the clock signal clk _ s has a frequency f in the current cyclecl；
The fifth step: constructing a data processing module in the variable multiple extractor, and outputting the value of the current sampling point when detecting the rising edge of the clock signal clk _ s, so as to process the single sampling frequency signal data output by the interpolation filter into a signal data _ t with three sampling frequencies;
and a sixth step: constructing a correction module, recalculating and assigning the amplitude of the current sampling point in the input signal data _ t by using a correction algorithm when the rising edge of the clock signal clk _ s is detected, and outputting a new signal data _ t' to enable a U PWM signal obtained by a UPWM generator to be similar to an NPWM signal in a time domain; the correction algorithm used in the correction module is as follows: suppose F1(x1，in1)、F2(x2，in2) And F3(x3，in3) For three adjacent samples of the input modulation signal, where F2For the current sampling point, F1For the previous sampling point, F3For the next sampling point, in1、in2And in3The amplitudes of the three sampling points are respectively,
Figure BDA0002309413850000151
x2＝0，
Figure BDA0002309413850000152
f1and f2Are respectively sampling point F1And F2The corresponding sampling frequency; normalizing the amplitudes of the carrier signal and the sampling point to ensure that the minimum value is 0 and the maximum value is 1, and then, at the sampling point F2And F3The carrier waveform expression in between is:
Figure BDA0002309413850000153
solving the amplitude of the intersection point (pseudo-natural sampling point) of the carrier wave and a second-order Newton interpolation curve constructed by the three sampling points to replace the amplitude of the current sampling point and inputting the amplitude of the current sampling point to the back edge UPWMThe generator can enable the generated back edge UPWM signal to approximate a back edge NPWM signal on a time domain, so that harmonic distortion of the signal is reduced; the second-order Newton interpolation curve function expression is as follows: inp(x)＝λ1+λ2·(x-x1)+λ3·(x-x1) X, wherein λ1＝in1，
Figure BDA0002309413850000154
Let F (x) equal to inp(x) -cw (x) 0, setting x to an initial value
Figure BDA0002309413850000155
Approximate solution of F (x) can be obtained by Newton-Raphson iteration method
Figure BDA0002309413850000156
Wherein
Figure BDA0002309413850000157
in′p(x)＝λ2+λ3·x+λ3·(x-x1) (ii) a Finally, x is putbSubstituting into carrier waveform expression to obtain pseudo-natural sampling point amplitude
Figure BDA0002309413850000158
From inbThe back edge UPWM signal generated by the back edge UPWM generator approximates the back edge NPWM signal in time domain;
the seventh step: constructing an m-level back edge UPWM generator, constructing a second counter in the m-level back edge UPWM generator, wherein the counter is also an adding counter which counts the rising edge of a clock signal clk _ m, and clearing the counter when the rising edge of a clock signal clk _ s is detected;
eighth step: an amplitude adjusting module is constructed in the m-stage back edge UPWM generator, and because the frequency of the input clock signal clk _ s of the back edge UPWM generator and the sampling frequency of the input digital audio signal data t' of the back edge UPWM generator are synchronously variable, the duty ratio of the back edge UPWM signal output by the back edge UPWM generator is ensured when being compared with the duty ratio of the back edge UPWM signal output by the back edge UPWM generator without frequency spreadingThe module judges the frequency of the current clk _ s according to the input clock signal clk _ s and the threshold signal thr _ val through the current thr _ val value, so that the amplitude of each sampling point of the digital audio signal data _ t 'input by the UPWM generator at the rear edge is adjusted in real time, and a new signal data _ t' is output; the amplitude adjustment rule of the amplitude adjustment module is as follows: when the current threshold signal thr _ val is t1When the current clock signal clk s has a frequency fcsThe adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000161
when the current threshold signal thr _ val is tcWhen the current clock signal clk s has a frequency fcThe adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000162
when the current threshold signal thr _ val is tsWhen the current clock signal clk s has a frequency fc1The adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000163
wherein, val _ data' is the original amplitude of the current sampling point.
The ninth step: constructing a comparator in the m-stage back edge UPWM generator, and judging whether the output value count of the counter is greater than the threshold y in the seventh step by the comparator at the rising edge of each clock signal clk _ m; if yes, the output of the comparator is 0, otherwise, the output of the comparator is 1, and therefore a back edge two-level UPWM signal with three sampling frequencies is output; the threshold value y is equal to the amplitude of the current sampling point of the output signal data _ t' of the amplitude adjusting module. Each UPWM generator in the filtering-free digital D-type audio power amplifier outputs two paths of differential signals, the two UPWM generators output four paths of UPWM signals together to drive an H-bridge type power stage, so that three voltage levels are formed at two ends of a power amplifier load, the power amplifier reduces the dependence on an LC analog low-pass filter in the aspect of efficiency, and because the PRF of each path of UPWM signal is variable, the energy of the signals at two ends of the power amplifier load at the PRF and harmonic waves thereof is diffused into peripheral frequency bands, and the aim of reducing the EMI of the power amplifier is fulfilled.
The filter-free pulse width modulator is constructed by using the three-frequency pseudorandom variable spread spectrum modulation method, and the structural schematic diagram of the filter-free pulse width modulator is shown in fig. 3. The filter-free pulse width modulator comprises an interpolation filter, a variable multiple decimator, an negation module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first back edge UPWM generator and a second back edge UPWM generator; the digital audio signal is connected with an interpolation filter, the interpolation filter is connected with a variable multiple extractor, the variable multiple extractor is respectively connected with a first correction module and a negation module, the negation module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first rear edge UPWM generator, the second Sigma-Delta modulator is connected with a second rear edge UPWM generator, and two rear edge UPWM signals output by the first rear edge UPWM generator and two rear edge UPWM signals output by the second rear edge UPWM generator are both connected with an H bridge type power stage of a power amplifier.
In FIG. 3 fo48kHz for the sampling frequency of the audio input signal, the frequency f of the main clock clk m used by the filter-less pulse-width modulatorclk_mIs 98.304 MHz. The interpolation filter designed by the invention is an interpolation filter for realizing 32 times of oversampling, and uniformly increases the sampling frequency of an input signal 48kHz to fs1536kHz, the sampling frequency fsAlso the frequency of the clock signal clk bas.
The schematic diagram of the variable multiple decimator designed by the present invention for the purpose of spreading spectrum is shown in fig. 4. The variable multiplier decimator includes a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine, and a data processing module. The clock signal clk _ bas is respectively connected with the pseudo-random number generator, the finite-state machine, the first counter and the clock generator, the first counter and the threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal with three by using a frequency synthesis technologyClock signal clk s of one frequency. In the system, q is 4, v is 1, the number m of the rear edge UPWM generator is 64, and f isc＝fs/q＝384kHz，
Figure BDA0002309413850000181
Ns＝p+v＝5， N1＝p-v＝3，
Figure BDA0002309413850000182
Figure BDA0002309413850000183
A clock signal clk r is connected to the pseudo-random number generator and the finite state machine, respectively, the clock signal clk r being divided by a main clock signal clk m at a frequency fclk_rGreater than the maximum value f of three sampling frequenciesclIn the present system, the frequency f of the clock signal clk _ rclk_rAt 768 kHz. An 8-bit pseudo random number generator formed by 16 stages of linear feedback shift registers is connected with a finite state machine. The structure diagram of the 16-stage linear feedback shift register is shown in fig. 5, and the 16-stage linear feedback shift register consists of 16D flip-flops, 3 4 input or gates, 13 input or gate, 14 input nor gate and 4 exclusive or gates. The 16-stage linear feedback shift register is controlled by a clock signal clk _ r and a reset signal reset, and every time a clock cycle of clk _ r passes, output values of the last 8D flip-flops in the 16-stage linear feedback shift register form 8-bit pseudo-random numbers rand _ num. The state transition diagram of the finite state machine is shown in FIG. 6, and the initial state of the finite state machine is S0And sequentially taking values from the highest bit to the lowest bit of the 8-bit pseudo random number by a one-bit variable K, determining the next state by a finite state machine according to the value K and the current state until the value K is taken to the lowest bit of the pseudo random number, and outputting a final state, wherein the finite state machine has three final states: s0、S1、S2. As can be seen from fig. 6, the finite state machine state decision rule is: if the current state is S0And K is 0, the next state is S0(ii) a If the current state is S0When K is 1, the next state is S1(ii) a If the current state is S1And K is 0, the next state is S2(ii) a If the current state is S1And K is 1, the next state is S0(ii) a If the current state is S2And K is 0, the next state is S1(ii) a If the current state is S2And K is 1, the next state is S2. The finite-state machine is connected with a threshold generator, and the threshold generator determines a threshold thr _ val corresponding to the final state output by the finite-state machine. The rule for the threshold generator to generate the threshold thr _ val is: at the current pseudo random number corresponding to the final state S0When the threshold thr _ val is t1＝fs/fcs(ii) 5; at the current pseudo random number corresponding to the final state S1When the threshold thr _ val is tc＝fs/f c4; at the current pseudo random number corresponding to the final state S2When the threshold thr _ val is ts＝fs/f cl3. The first counter counts the rising edge of the clock signal clk _ bas by 1, when the count value is zero, the output clock signal clk _ s of the clock generator is set to high level, and when the value cou _ val of the counter is equal to the current threshold value
Figure BDA0002309413850000191
When the same, the clock signal clk _ s is set to a low level, and when the value cou _ val of the counter is the same as the current threshold thr _ val, the clock signal clk _ s is set to a high level again and the counter is cleared, respectively]Get the wholeRounding to truncate the decimal place. The clock generator generates a new clock signal clk _ s having three frequencies (307.2kHz, 384kHz and 512kHz) according to the threshold thr _ val, the counter value cou _ val and the clock signal clk _ bas. The clock generator and the input signal data are both connected to the data processing module, and the data processing module performs decimation processing on the input digital audio signal data according to the clock signal clk _ s generated by the clock generator, so as to output the digital audio signal data _ t with three sampling frequencies (307.2kHz, 384kHz and 512 kHz).
In order to eliminate harmonic distortion of the output signal of the power amplifier, the correction module corrects the digital audio signal data _ t into data _ t'. A schematic diagram of the correction algorithm used in the correction module is shown in fig. 7. The method utilizes the characteristic that NPWM has no harmonic distortion to correct the modulation signal before UPWM, so that the UPWM signal finally output by the UPWM generator is similar to the NPWM signal in the time domain to eliminate the harmonic distortion of the output signal. According to the current sampling point, the previous sampling point and the next sampling point of the modulation signal, a second-order Newton interpolation curve function expression is established, meanwhile, a carrier waveform expression is established, the Newton-Raphson iteration method is used for solving the amplitude of the intersection point of the carrier waveform and the interpolation curve, and the amplitude of the point is similar to the waveform of the back edge NPWM in the time domain through the UPWM waveform of the back edge obtained by the UPWM generator.
The schematic diagram of the back edge UPWM generator is shown in fig. 8, and includes an amplitude adjustment module, a second counter, a comparator, and an inversion module. The clock signal clk _ s is respectively connected with the second counter and the amplitude adjusting module, the digital audio signal data _ t' is connected with the amplitude adjusting module, the clock signal clk _ m is respectively connected with the second counter and the comparator, the amplitude adjusting module is connected with the comparator, the second counter is connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the negating module and then output. The amplitude adjusting module has the functions of: when the frequency of the clock signal clk _ s is fcsAnd then, the adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000201
when the frequency of the clock signal clk _ s is fcAnd then, the adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000202
when the frequency of the clock signal clk _ s is fclAnd then, the adjustment formula of the amplitude of the current sampling point is as follows:
Figure BDA0002309413850000203
wherein, val _ data' is the original amplitude of the current sampling point. The second counter counts the rising edge of the clock signal clk _ m, and when the rising edge of the clock signal clk _ s is detected, the counter is cleared; the comparators at eachThe rising edge of the clock signal clk _ m compares the output count value of the counter with the adjusted signal amplitude, and if the count value is smaller than the adjusted signal amplitude, the output of the comparator is 1; if the counting value is larger than or equal to the adjusted signal amplitude, the output of the comparator is 0. The inverter inverts one output signal of the comparator so that one UPWM generator outputs two differential UPWM signals.
In order to improve the output fidelity of a power amplification system, a first Sigma-Delta modulator and a second Sigma-Delta modulator are 8-order feedforward interpolation Sigma-Delta modulators, and convert a 24-bit high-precision input signal into a 7-bit low-precision signal so that a 64-stage back edge UPWM signal is output by the first UPWM generator and the second UPWM generator. The filtering-free pulse width modulator shown in the attached figure 3 comprises two UPWM generators, four paths of UPWM signals output by the filtering-free pulse width modulator just drive four input ends of an H bridge type power stage respectively, so that three voltage levels are formed at two ends of a power amplifier load, the dependence of the power amplifier on an LC analog low-pass filter is reduced in efficiency, and because each path of UPWM signal has three sampling frequencies, the energy of the signals at two ends of the power amplifier load at the sampling frequency and the harmonic wave thereof is diffused into a peripheral frequency band, so that the aim of reducing the EMI of the power amplifier is fulfilled.
The invention realizes the filter-free pulse width modulator based on the spread spectrum modulation method by using a Field Programmable Gate Array (FPGA), and builds a test system as shown in figure 9 to verify the beneficial effect of the invention. As can be seen from FIG. 9, the Digital audio test signal source generates a Digital audio input signal with a sampling frequency of 48kHz in a Sony/Philips Digital Interface Format (S/PDIF) Format, and the Digital audio receiver processes the input signal into I2Data in S format, FPGA realized filter-free pulse width modulator based on spread spectrum modulation method provided by the invention, and I2S-format data are processed and four paths of back edge two-level UPWM signals are output, the four paths of back edge two-level UPWM signals are input to a USB module to be processed into corresponding back edge three-level UPWM signals, and then USThe B module transmits the back edge three-level UPWM signal to a computer for spectral analysis.
In the case of a single-frequency sinusoidal digital signal with an amplitude of 0dBFS, a frequency of 6.6kHz, a precision of 24-bit, and a sampling frequency of 48kHz, the baseband spectrum of a three-level UPWM signal output by a filter-free pulse width modulator without a spreading function (the PRF of a two-level back edge UPWM signal output by a back edge UPWM generator is constantly 384kHz) is as shown in fig. 10; the baseband frequency spectrum of the three-level UPWM signal output by the filter-free pulse width modulator based on the spread spectrum modulation method is shown in figure 11; the high frequency spectrum of a three-level UPWM signal output by a filter-free pulse width modulator without a spread spectrum modulation function is shown in fig. 12; the high frequency spectrum of the three-level UPWM signal outputted by the filter-free pwm based on the spread spectrum modulation method of the present invention is shown in fig. 13.
As can be seen from fig. 10 and 11, when the spread spectrum modulation method of the present invention is used, the spectrum of the output three-level UPWM signal of the system has a lower amplitude at the third harmonic of the input signal, and the THD of the system is 0.009%, which is less than the THD (0.094%) of the output three-level UPWM signal of the system without the spread spectrum modulation function. As can be seen from fig. 12 and 13, the peak amplitude of the three-level UPWM signal spectrum output by the system is-28.25 dBFS out-of-band when the spread spectrum modulation method of the present invention is used, and the peak amplitude of the three-level UPWM signal spectrum output by the system is-10.5 dBFS out-of-band when the spread spectrum modulation method is not used by the system. Compared with a system without a spread spectrum modulation function, the system based on the spread spectrum modulation method disclosed by the invention has the advantage that the out-of-band spectrum peak amplitude of the output three-level UPWM signal is reduced by 17.75 dB. Therefore, the spread spectrum modulation method provided by the invention can well perform amplitude reduction treatment on the energy peak on the high-frequency component of the UPWM signal output by the filtering-free digital D-type audio power amplifier, simultaneously reduce the output THD of the power amplifier, reduce the EMI of the power amplifier and simultaneously reduce the distortion introduced by the UPWM.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. A three-frequency pseudo-random variable spread spectrum modulation method is characterized by comprising the following steps:
the method comprises the following steps: using interpolation filter to sample frequency f of power amplifier input signaloIncrease N times to sampling frequency fsAnd according to the sampling frequency fsDetermining the intermediate frequency f of the required three sampling frequenciescWherein f isc＝fsQ, q is an integer less than N;
step two: by using frequency synthesis technology, according to the main clock signal clk _ m of the power amplifier system and the determined intermediate frequency fcDetermining two further sampling frequencies fcsAnd fc1Wherein f iscsThe minimum sampling frequency of the three,
Figure FDA0002309413840000011
Ns＝p+v，fc1the maximum sampling frequency of the three is,
Figure FDA0002309413840000012
N1＝p-v，v∈[1，p-1]and v is an integer,
Figure FDA0002309413840000013
fclk_mthe frequency of the master clock signal clk _ m, m being the number of stages of the uniformly sampled pulse width modulation generator, "uniformly sampled pulse width modulation" abbreviated "UPWM";
step three: constructing a variable multiple extractor, constructing a finite state machine and a pseudo-random number generator consisting of 2n stages of linear feedback shift registers in the variable multiple extractor, wherein the finite state machine utilizes an n-bit pseudo-random number rand _ num generated by the pseudo-random number generator to obtain a final state uniquely corresponding to the n-bit pseudo-random number rand _ num; the initial state of the finite state machine is S0Allowing a one-bit variable K to sequentially take values from the highest bit to the lowest bit of the n-bit pseudo random number, and obtaining a finite stateThe machine determines the next state according to the K value and the current state until K takes the lowest bit of the pseudo random number, and outputs the final state, and the finite state machine has three final states which are respectively: s0、S1、S2；
Step four: constructing a threshold generator, a first counter and a clock generator in a variable multiple extractor; the threshold generator determines a threshold thr _ val corresponding to the final state output by the finite-state machine, wherein the threshold is the extraction multiple of the current variable multiple extractor, and has three values: t is ts、tc、t1(ii) a The first counter is an up counter which counts the rising edges of the clock signal clk _ bas divided by the main clock signal clk _ m at a frequency fclk_bas＝fsWhen the count value is zero, the output clock signal clk _ s of the clock generator is set to high level, and when the counter value cou _ val is equal to the current threshold value
Figure FDA0002309413840000021
When the same, the clock signal clk _ s is set to a low level, and when the value cou _ val of the counter is the same as the current threshold thr _ val, the clock signal clk _ s is set to a high level again and the counter is cleared, respectively]Get the wholeRounding off the decimal place; the clock generator generates a new clock signal clk _ s with three frequencies according to the threshold thr _ val, the value cou _ val of the counter and the clock signal clk _ bas;
step five: constructing a data processing module in the variable multiple extractor, and outputting the value of the current sampling point when detecting the rising edge of the clock signal clk _ s, so as to process the single sampling frequency signal data output by the interpolation filter into a signal data _ t with three sampling frequencies;
step six: constructing a correction module, recalculating and assigning the amplitude of the current sampling point in the input signal data _ t by using a correction algorithm when the rising edge of the clock signal clk _ s is detected, outputting a new signal data _ t', enabling a UPWM signal obtained after the new signal data _ t passes through a back edge UPWM generator to approximate to a naturally sampled pulse width modulation signal in a time domain, wherein the naturally sampled pulse width modulation signal is abbreviated as NPWM;
step seven: constructing an m-level back edge UPWM generator, constructing a second counter in the m-level back edge UPWM generator, wherein the counter is also an adding counter which counts the rising edge of a clock signal clk _ m, and clearing the counter when the rising edge of a clock signal clk _ s is detected;
step eight: constructing an amplitude adjusting module in an m-level back edge UPWM generator, wherein the frequency of a clock signal clk _ s input by the back edge UPWM generator and the sampling frequency of a digital audio signal data _ t ' input by the back edge UPWM generator are synchronously variable, so that the duty ratio of the back edge UPWM signal output by the back edge UPWM generator is kept unchanged compared with the duty ratio without frequency spreading, and the module judges the frequency of the current clk _ s according to the input clock signal clk _ s and a threshold signal thr _ val and through the current thr _ val value, so that the amplitudes of sampling points of the digital audio signal data _ t ' input by the back edge UPWM generator are adjusted in real time, and a new signal data _ t ' is output;
step nine: constructing a comparator in the m-stage back edge UPWM generator, and judging whether the output value count of the second counter is greater than the threshold y in the seventh step by the comparator at the rising edge of each clock signal clk _ m; if yes, the output of the comparator is 0, otherwise, the output of the comparator is 1, and therefore a back edge two-level UPWM signal with three sampling frequencies is output; the threshold value y is equal to the amplitude of the current sampling point of the output signal data _ t' of the amplitude adjusting module.
2. The method as claimed in claim 1, wherein in the third step, the 2n stages of linear feedback shift registers are composed of 2n D flip-flops and gates, and controlled by a clock signal clk _ r and a reset signal reset, the clock signal clk _ r is divided by a main clock signal clk _ m, and the frequency f is fclk_rGreater than the maximum value f of three sampling frequenciesc1Every time a clock period of clk _ r passes, the output values of the last n D flip-flops of the 2 n-stage linear feedback shift register form an n-bit pseudo-random number rand _ num;
in the third step, the state decision rule of the finite state machine is as follows: if the current state is S0And K is 0, the next state is S0(ii) a If the current state is S0And K is 1, the next state is S1(ii) a If the current state is S1And K is 0, the next state is S2(ii) a If the current state is S1And K is 1, the next state is S0(ii) a If the current state is S2And K is 0, the next state is S1(ii) a If the current state is S2And K is 1, the next state is S2。
3. The spread spectrum modulation method according to claim 1, wherein the rule for the threshold generator to generate the threshold thr _ val in the fourth step is: at the current pseudo random number corresponding to the final state S0When the threshold thr _ val is t1(ii) a At the current pseudo random number corresponding to the final state S1When the threshold thr _ val is tc(ii) a At the current pseudo random number corresponding to the final state S2When the threshold thr _ val is ts；
In the fourth step, the generation rule of the clock signal clk _ s is: at the current threshold thr _ val of t1While the clock signal clk _ s has a frequency f in the current cyclecs(ii) a At the current threshold thr _ val of tcWhile the clock signal clk _ s has a frequency f in the current cyclec(ii) a At the current threshold thr _ val of tsWhile the clock signal clk _ s has a frequency f in the current cyclec1。
4. The method according to claim 1, wherein in the sixth step, the correction algorithm used in the correction module is: suppose F1(x1，in1)、F2(x2，in2) And F3(x3，in3) For three adjacent samples of the input modulation signal, where F2For the current sampling point, F1Is the previous oneSampling point, F3For the next sampling point, in1、in2And in3The amplitudes of the three sampling points are respectively,
Figure FDA0002309413840000041
x2＝0，
Figure FDA0002309413840000042
f1and f2Are respectively sampling point F1And F2The corresponding sampling frequency; normalizing the amplitudes of the carrier signal and the sampling point to ensure that the minimum value is 0 and the maximum value is 1, and then, at the sampling point F2And F3The expression of the carrier waveform of the sawtooth wave between the two is as follows:
Figure FDA0002309413840000043
solving the amplitude of the intersection point (pseudo-natural sampling point) of the carrier and a second-order Newton interpolation curve constructed by the three sampling points to replace the amplitude of the current sampling point and inputting the amplitude into the back edge UPWM generator, so that the generated back edge UPWM signal is approximate to the back edge NPWM signal in the time domain, and the harmonic distortion of the signal is reduced; the second-order Newton interpolation curve function expression is as follows: inp(x)＝λ1+λ2·(x-x1)+λ3·(x-x1) X, wherein λ1＝in1，
Figure FDA0002309413840000051
Let F (x) equal to inp(x) -cw (x) 0, setting x to an initial value
Figure FDA0002309413840000052
Approximate solution of F (x) can be obtained by Newton-Raphson iteration method
Figure FDA0002309413840000053
Wherein
Figure FDA0002309413840000054
in′p(x)＝λ2+λ3·x+λ3·(x-x1) (ii) a Finally, x is putbSubstituting into carrier waveform expression to obtain pseudo-natural sampling point amplitude
Figure FDA0002309413840000055
From inbThe trailing edge UPWM signal generated by the trailing edge UPWM generator approximates the trailing edge NPWM signal in the time domain.
5. The method according to claim 1, wherein in step eight, the amplitude adjustment rule of the amplitude adjustment module is: when the current threshold signal thr _ val is t1When the current clock signal clk s has a frequency fcsThe adjustment formula of the amplitude of the current sampling point is as follows:
Figure FDA0002309413840000056
when the current threshold signal thr _ val is tcWhen the current clock signal clk s has a frequency fcThe adjustment formula of the amplitude of the current sampling point is as follows:
Figure FDA0002309413840000057
when the current threshold signal thr _ val is tsWhen the current clock signal clk s has a frequency fc1The adjustment formula of the amplitude of the current sampling point is as follows:
Figure FDA0002309413840000061
wherein, val _ data' is the original amplitude of the current sampling point.
6. The filter-free pulse width modulator constructed by the pseudorandom variable spread spectrum modulation method of any one of claims 1 to 5, wherein the filter-free pulse width modulator comprises an interpolation filter, a variable multiple extractor, an negation module, a first correction module, a second correction module, a first Sigma-Delta modulator, a second Sigma-Delta modulator, a first back edge UPWM generator and a second back edge UPWM generator; the digital audio input signal is connected with an interpolation filter, the interpolation filter is connected with a variable multiple extractor, the variable multiple extractor is respectively connected with a first correction module and a negation module, the negation module is connected with a second correction module, the first correction module is connected with a first Sigma-Delta modulator, the second correction module is connected with a second Sigma-Delta modulator, the first Sigma-Delta modulator is connected with a first rear edge UPWM generator, the second Sigma-Delta modulator is connected with a second rear edge UPWM generator, and two rear edge UPWM signals output by the first rear edge UPWM generator and two rear edge UPWM signals output by the second rear edge UPWM generator are both connected with an H bridge type power stage of a power amplifier.
7. The filter-free pulse width modulator of claim 6, wherein the interpolation filter is a 32-fold interpolation filter, the first and second Sigma-Delta modulators are identical and are each 8-order feed-forward interpolated Sigma-Delta modulators, and both the first and second Sigma-Delta modulators convert the 24-bit high precision input signal to a 7-bit 65 quantization level low precision signal such that the first and second trailing edge UPWM generators output 64 levels of trailing edge UPWM signals.
8. The filter-free pulse width modulator of claim 6, wherein the variable multiplier decimator comprises a first counter, a clock generator, a pseudo-random number generator, a threshold generator, a finite state machine, and a data processing module; the system main clock signal is connected with the variable multiple extractor; a clock signal clk r is connected to the pseudo-random number generator and the finite state machine, respectively, the clock signal clk r being divided by a main clock signal clk m at a frequency fclk_rGreater than the maximum of three sampling frequencies fc1The pseudo-random number generator is connected with the finite-state machine, the finite-state machine is connected with the threshold generator, and the threshold generator determines a threshold thr _ val corresponding to the final state output by the finite-state machine; clock signal cThe lk _ bas is respectively connected with a pseudo-random number generator, a finite-state machine, a first counter and a clock generator, the first counter and a threshold generator are both connected with the clock generator, and the clock generator generates a new clock signal clk _ s by using a frequency synthesis technology; the clock generator and the input signal data are both connected with the data processing module, and the data processing module performs extraction processing on the input digital audio signal data according to a clock signal clk _ s generated by the clock generator, so that the digital audio signal data _ t with three sampling frequencies is output.
9. The filter-free pulse width modulator of claim 8, wherein the pseudo random number generator is mainly composed of a 16-stage linear feedback shift register, and the linear feedback shift register generates an 8-bit pseudo random number and inputs the pseudo random number to the finite state machine every clk _ r cycle by setting an initial state for the linear feedback shift register; the finite state machine calculates a final state corresponding to the current pseudo-random number according to the current pseudo-random number and inputs the final state to the threshold generator, and the threshold generator determines the extraction multiple of the current variable multiple extractor according to the current final state;
the first counter counts rising edges of a clock signal clk _ bas, and when the rising edges of the clk _ bas are detected, the value of the counter is increased by 1; when the counter value is equal to the current threshold thr _ val, the counter is cleared;
the first and second correction modules are the same, and both calculate the amplitude of each sampling point again by using the correction technique according to the threshold signal thr _ val, the clock signal clk _ s and the digital audio signal data _ t with three sampling frequencies output by the variable multiple decimator, thereby outputting a new signal data _ t'.
10. The filter-free pulse width modulator of claim 8, wherein the first and second back edge UPWM generators are the same and comprise an amplitude adjustment module, a second counter, a comparator, and an inversion module; the clock signal clk _ s is respectively connected with the second counter and the amplitude adjusting module, the digital audio signal data _ t' is connected with the amplitude adjusting module, the clock signal clk _ m is respectively connected with the second counter and the comparator, the amplitude adjusting module and the second counter are respectively connected with the comparator, one path of the comparator is directly output, and the other path of the comparator is connected with the negating module and then output; the amplitude adjusting module calculates and adjusts the amplitude of the current sampling point according to an adjusting rule; the second counter counts the rising edge of the clock signal clk _ m, and when the rising edge of the clock signal clk _ s is detected, the counter is cleared; and the comparator compares the counter value with the adjusted signal amplitude, one path of signal is directly output as a back edge UPWM signal, and the other path of signal is inverted by the inverting module and then outputs the back edge UPWM signal.
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