CN110944125B - Nonlinear column-level ADC (analog to digital converter) and method for improving contrast ratio of CMOS (complementary metal oxide semiconductor) image sensor - Google Patents

Nonlinear column-level ADC (analog to digital converter) and method for improving contrast ratio of CMOS (complementary metal oxide semiconductor) image sensor Download PDF

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CN110944125B
CN110944125B CN201911076762.9A CN201911076762A CN110944125B CN 110944125 B CN110944125 B CN 110944125B CN 201911076762 A CN201911076762 A CN 201911076762A CN 110944125 B CN110944125 B CN 110944125B
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counter
comparator
nonlinear
slope
ramp
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CN110944125A (en
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张鹤玖
余宁梅
刘尕
吕楠
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Xian University of Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H04N25/575—Control of the dynamic range involving a non-linear response with a response composed of multiple slopes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

The invention discloses a nonlinear column ADC for improving the contrast of a CMOS image sensor, which comprises a nonlinear ramp generator and a counter which are connected to be used as the same clock input, wherein the output end of the ramp generator is connected with the positive input end of a comparator, the negative input end of the comparator is connected with pixel voltage sampling, the output end of the comparator is sequentially connected with a latch and a register, the register is also connected with the counter, and the register is used for storing the value of the counter and outputting a result.

Description

Nonlinear column-level ADC (analog to digital converter) and method for improving contrast ratio of CMOS (complementary metal oxide semiconductor) image sensor
Technical Field
The invention belongs to the technical field of high-contrast CMOS image sensors, and particularly relates to a nonlinear column-level ADC (analog-to-digital converter) for improving the contrast of a CMOS image sensor.
The invention also relates to a method for improving the contrast of the CMOS image sensor.
Background
With the development of biomedical diagnostic and testing field, cell detection technology provides important basis for diagnosing the life condition and basic information of organisms. Different physical conditions can correspond to different cell types, cell numbers, cell structures and cell morphologies, and the understanding of various characteristics of the cells has important significance for human health, disease research and drug development. The most basic cell detection methods at present include a chemical detection method and an optical microscopy detection method, but the methods are complex to operate, require professional operation, and cannot be applied to popularization of urban medical treatment. The lens-free imaging system is composed of a light source and a light detector, the light detector is mainly composed of a CMOS image sensor, the size is small, the cost is low, the carrying is convenient, and the requirements of modern medical treatment are met.
In the lens-free cell imaging system, although the performance of the CMOS image sensor is improved with the development of the integrated circuit, most of the CMOS image sensors have linear and uniform output and are suitable for the environment with bright and uniform illumination, but when the cell imaging is performed in the lens-free dark environment, a dark image is obtained due to low sensitivity to illumination intensity. In addition, under a lens-free cell imaging system, the local contrast of the obtained cell image is also low, and because the transmissivity of the subject cell is close to the transmissivity of the surrounding liquid background, the gray distribution range of the image is narrow, the image is slightly blurred, the gray values of local areas are close, and the contrast is reduced, so that the image content cannot be rapidly distinguished. To solve this problem, three solutions are generally adopted at the present stage: firstly, an image signal processing circuit is added in an ADC, and an automatic exposure logic circuit is introduced to expand a dynamic range, but when the method is used in a bright environment, conversion saturation is caused, the dynamic range becomes small, and an ISP circuit also occupies an area of a chip to increase power consumption. Secondly, a multi-frame exposure or multiple correlated sampling mode is adopted, but the multiple sampling can influence the frame rate of system work; and multi-frame exposure increases the exposure time, resulting in an extended shooting time of the sensor. Thirdly, a digital contrast stretching algorithm is adopted outside the chip, the method has two defects although being easy to implement, the first is that the method mainly aims at the whole image, the higher the requirement is, the more complex the mapping function is, and the integration in the CMOS image sensor is difficult to realize; secondly, the quantization error under low illumination can be amplified by adopting a digital method for correction, and at the moment, the image details in the illumination range can be influenced. These methods all increase the design complexity of the circuit to different degrees, increase the circuit consumption, and are difficult to meet the requirements of the future CMOS image sensor.
Disclosure of Invention
The invention aims to provide a nonlinear array ADC (analog to digital converter) for improving the contrast of a CMOS (complementary metal oxide semiconductor) image sensor, which is suitable for application of a lens-free imaging system in a dark light environment, improves the contrast of local cells and obtains a clear cell image.
Another object of the present invention is to provide a method for improving contrast of a CMOS image sensor.
The first technical scheme adopted by the invention is that the nonlinear column-level ADC for improving the contrast of the CMOS image sensor comprises a nonlinear ramp generator and a counter which are connected to be used as the same clock input, the output end of the ramp generator is connected with the positive input end of a comparator, the negative input end of the comparator is connected with pixel voltage sampling, the output end of the comparator is sequentially connected with a latch and a register, the register is also connected with the counter, and the register is used for storing the value of the counter and outputting the result.
The second technical scheme adopted by the invention is a method for improving the contrast ratio of a CMOS image sensor, which adopts the nonlinear column-level ADC for improving the contrast ratio of the CMOS image sensor and is characterized by comprising the following steps:
step 1, a comparator samples input pixel voltage;
step 2, after the sampling in the step 1 is finished, under the control of a clock signal, a slope generator generates a nonlinear slope, and a counter starts to count at the same time;
and 3, the comparator outputs and overturns according to the change of the voltage difference value of the positive input end and the negative input end, and the register outputs the value of the counter at the moment.
The second technical scheme of the invention is also characterized in that:
wherein the step 1 specifically comprises the following steps:
sampling switch SSWhen closed, the pixel voltage VpixelThe sampled pixel voltage is sampled to the negative input end of the comparator, then the sampling switch is switched off, and the negative input end of the comparator is the sampled pixel voltage;
wherein the step 2 specifically comprises the following steps:
step 2.1, under the control of the clock signal, the ramp generator starts to generate a ramp, and the ramp is divided into five regions according to the distribution condition of the cell gray values: the cell nucleus, the nucleus cytoplasm margin, the cytoplasm, the cell membrane and the sheath fluid, wherein the corresponding digital codes of the five regions are respectively: 0-255, 256-345, 346-652, 653-742, 743-1023;
step 2.2, realizing a nonlinear slope, designing 5 current steering DACs by combining the five areas divided in the step 2.1, enabling the output current of each current steering DAC to flow through the same reference resistor, and designing a corresponding reference current at each current steering DAC, namely realizing the nonlinear slope at the output end of a slope generator;
step 2.3, correspondingly designing 5 counters according to the 5 current steering DACs designed in step 2.2, wherein each counter starts counting from 0, each counter only counts the digital code value of the area, and finally outputting a voltage value generating a nonlinear ramp through the counter as follows:
Vout＝(D1×I1+D2×I2+Λ+D5×I5)·R (1)
in the formula, D1，···，D5Is the code value of the counter 1-5;
the working process of the 5 counters in the step 2.3 is specifically as follows:
firstly, a counter 1 starts counting, a current steering DAC corresponding to the counter 1 starts outputting current to generate a slope of a first stage, after the counter 1 finishes counting, a carry signal CO1 is output, CO1 is changed into 1, a latch latches the value of the counter 1, meanwhile, a counter 2 starts counting, a current steering DAC corresponding to the counter 2 starts outputting current of a second stage, a slope of the second stage is generated, and the like until a counter 5 finishes counting;
wherein the step 3 specifically comprises the following steps:
the comparator compares the sampled pixel voltage with the ramp voltage, when the comparison is started, the comparator outputs 0, the ramp voltage is continuously increased, when the ramp voltage is equal to the pixel voltage, the output of the comparator starts to turn over and jump from 0 to 1, after the latch detects the change of the rising edge of the input signal, the rising edge is output to the register, the register stores and then outputs the value of the counter at the moment of the rising edge, and the output code value is the digital quantity quantized by the comparator.
The invention has the beneficial effects that:
the invention is applied to the CMOS image sensor in the lens-free system, designs the column-level nonlinear ADC in the CMOS image sensor, improves the contrast of the CMOS image sensor, utilizes the slope generator to directly generate the nonlinear slope, avoids the operation of the digital part on the output, and only uses 210The CLK can realize the nonlinearity of 10-bit without increasing new power consumption, the nonlinear ramp generator adopts a multilayer current steering structure, each current steering DAC is simple in design idea and convenient to combine, compared with the traditional resistor string type nonlinear DAC, the structure does not need a plurality of reference voltages, and the nonlinear output can be realized only by controlling the on-off of current by a digital circuit.
Drawings
FIG. 1 is a schematic diagram of a non-linear ADC structure in a non-linear column-level ADC for improving the contrast of a CMOS image sensor according to the present invention;
FIG. 2 is a schematic diagram of a system structure of a non-linear column-level ADC for improving the contrast of a CMOS image sensor according to the present invention;
FIG. 3 is a schematic diagram of a non-linear ramp generating circuit based on a current steering structure in a non-linear column-level ADC for improving the contrast of a CMOS image sensor according to the present invention;
FIG. 4 is a schematic diagram of a single current steering DAC circuit in a non-linear column-level ADC for improving the contrast of a CMOS image sensor according to the present invention;
fig. 5 is a non-linear ramp generator output non-linear curve in a non-linear column ADC for improving the contrast of a CMOS image sensor according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention provides a non-linear column-level ADC (analog to digital converter) for improving the contrast of a CMOS (complementary metal oxide semiconductor) image sensor, which is shown in a figure 1 and a figure 2 and comprises a non-linear ramp generator and a counter which are connected to be used as the same clock input, wherein the output end of the ramp generator is connected with the positive input end of a comparator, the negative input end of the comparator is connected with pixel voltage sampling, the output end of the comparator is sequentially connected with a latch and a register, the register is also connected with the counter, and the register is used for storing the value of the counter and outputting a result.
The invention also provides a method for improving the contrast ratio of a CMOS image sensor, which adopts the nonlinear column-level ADC for improving the contrast ratio of the CMOS image sensor, and is implemented by the following steps:
step 1, a comparator samples input pixel voltage: as shown in fig. 2, the sampling switch SSWhen closed, the pixel voltage VpixelIs sampled to the negative input of the comparator, which is the sampled pixel voltage, and then the sampling switch is turned off.
Step 2, after the sampling in step 1 is finished, under the control of a clock signal, a slope generator generates a nonlinear slope, and a counter starts counting, which is implemented according to the following steps:
step 2.1, under the control of the clock signal, the ramp generator starts to generate a ramp, and according to the distribution of the cell gray values, as shown in fig. 3, the ramp is divided into five regions: the cell nucleus, the cell nucleus cytoplasmic edge, the cytoplasm, the cell membrane and the sheath fluid are required to be stretched, in the area required to be stretched, the slope of the slope is half of the standard slope, in the area required to be compressed, the slope is 2 times of the standard slope, other areas are the standard slopes, and the digital codes corresponding to the five areas are respectively as follows: 0-255, 256-345, 346-652, 653-742, 743-1023;
step 2.2, the ramp generator is mainly composed of a current steering DAC, and the ramp of the current steering DAC is changedStep size is ILSBR, reference current I of standard current steering DACLSBAnd the reference resistor R are both constant, and the slope of the reference resistor R is constant; for the current steering DAC, under the condition that the clock frequency is unchanged, the longer the step length is, the larger the slope is, and the step length is closely related to the slope; under the condition that the resistance is unchanged, the slope of the slope can be changed by changing the reference current, in order to realize the nonlinear slope, 5 current steering DACs are designed in combination with the five areas divided in the step 2.1, the output current of each current steering DAC flows through the same reference resistance, the corresponding reference current is designed at each current steering DAC, and the nonlinear slope can be realized at the output end of the slope generator;
step 2.3, correspondingly designing 5 counters according to the 5 current steering DACs designed in step 2.2, wherein each counter starts counting from 0, each counter only counts the digital code value of the area, and finally outputting a voltage value generating a nonlinear ramp through the counter as follows:
Vout＝(D1×I1+D2×I2+Λ+D5×I5)·R (1)
in the formula, D1，···，D5Is the code value of the counter 1-5;
the working process of the 5 counters is as follows:
firstly, the counter 1 starts counting, the current steering DAC corresponding to the counter 1 starts outputting current to generate a first-stage slope, the counter 1 outputs a carry signal CO1 after counting is finished, the CO1 is changed to 1, the latch latches the value of the counter 1, meanwhile, the counter 2 starts counting, the current steering DAC corresponding to the counter 2 starts outputting a second-stage current to generate a second-stage slope, and so on until the counter 5 finishes counting.
And 3, the comparator outputs and overturns according to the change of the voltage difference value of the positive input end and the negative input end, and the register outputs the value of the counter at the moment:
the comparator compares the sampled pixel voltage with the ramp voltage, when the comparison is started, the comparator outputs 0, the ramp voltage is continuously increased, when the ramp voltage is equal to the pixel voltage, the output of the comparator starts to turn over and jump from 0 to 1, after the latch detects the change of the rising edge of the input signal, the rising edge is output to the register, the register stores and then outputs the value of the counter at the moment of the rising edge, and the output code value is the digital quantity quantized by the comparator.
The mechanism of the invention is as follows:
as shown in fig. 2, the CMOS image sensor mainly includes a pixel array, a correlated double sampling, a column conversion circuit, a timing control circuit, a reference circuit, a ramp generation circuit, and a digital processing circuit. The pixel array generates pixel voltage through exposure, the related double sampling circuit performs noise reduction output on the input pixel voltage to improve the signal-to-noise ratio of the pixel voltage, the column conversion circuit is mainly a comparator and compares the pixel voltage with a nonlinear slope and then outputs an output result to the digital processing circuit, the reference circuit provides required bias voltage and current for the circuit, and the slope generator generates the nonlinear slope;
fig. 1 is a non-linear ADC for improving the contrast of a CMOS image sensor, which is designed in the present invention, and the quantization process of the ADC mainly includes three stages: first, switch SSThe method comprises the steps of closing, sampling a pixel voltage signal to a negative input end of a comparator, then opening a switch, completing sampling by an ADC, entering a comparison stage, enabling a nonlinear ramp generator and a counter to change simultaneously, enabling the output of the comparator to be 0, enabling the comparator to be ready to turn when Vramp is equal to Vpixel, and enabling the comparator to be ready to turn when Vramp is equal to Vpixel>When Vpixel is needed, the output of the comparator is turned from 0 to 1, the latch transmits the turning signal to the register, the register saves and outputs the value counted by the counter at the moment according to the input signal, and the nonlinear ADC completes the quantization of the analog pixel voltage;
fig. 3 is a non-linear ramp generator based on a current steering structure according to the present invention, which first determines the segment area and the size of the segment area of the non-linear DAC, where each area is: 0-255, 256-345, 346-652, 653-742, 743-1023; designing corresponding reference current according to the slope of each region slope, wherein the reference current of each region is respectively as follows: 0.5 μ A, 1 μ A, 0.5 μ A, 1 μ A, 2 μ A; and the counting value of the counter is designed according to the code value number of each area, and the counting code value of each area counter is as follows: 255, 90, 307, 90, 281; the working process is as follows: firstly, the counter 1 starts counting, the current steering DAC1 starts outputting current to generate a slope of a first stage, the counter 1 outputs a carry signal CO1 after counting is finished, CO1 becomes 1, the latch latches the value of the counter 1, meanwhile, the counter 2 starts counting, the current steering DAC starts outputting current of a second stage to generate a slope of the second stage, and the like until the counter 5 finishes counting;
FIG. 4 is a schematic diagram of a current steering DAC structure adopted by the present invention, which mainly includes a bias circuit, a current source array, a digital control and switch array, wherein the bias circuit generates a required bias voltage for the current source array to make each path in the current source array generate a corresponding current, the digital control controls the on/off of a switch in the switch array to select the current of the corresponding branch, and finally the current summation output of each branch is If；
FIG. 5 is a non-linear ramp generated by the non-linear ramp generator of the present invention, including a standard linear ramp curve and a generated non-linear ramp curve, the non-linear ramp being divided into five regions from top to bottom, which are cell nucleus, cell nucleus cytoplasm edge, cell membrane, and sheath fluid, respectively; wherein the cell nucleus and the cytoplasm need to be stretched, the slope of the cell nucleus and the cell membrane do not need to be stretched in the area where the cell nucleus and the cytoplasm are located, the slope is a standard slope, the sheath fluid area needs to be compressed, the slope is the maximum, and the digital code at each segmentation point and the corresponding voltage value are respectively as follows: (255, 0.1275V), (345, 0.2175V), (652, 0.371V), (742, 0.461V), (1023, 1.023V).
The nonlinear column-level ADC for improving the contrast of the CMOS image sensor utilizes the principle that a single current steering DAC can generate a linear slope, combines the principle that different currents can be directly summed on a resistor, and uses a plurality of current steering DACs to generate a nonlinear slope.

Claims (3)

1. A method for improving the contrast ratio of a CMOS image sensor adopts a nonlinear column-level ADC for improving the contrast ratio of the CMOS image sensor, and is characterized by comprising a nonlinear ramp generator and a counter which are connected to be used as the same clock input, wherein the output end of the ramp generator is connected with the positive input end of a comparator, the negative input end of the comparator is connected with a pixel voltage sample, the output end of the comparator is sequentially connected with a latch and a register, the register is also connected with the counter, and the register is used for storing the value of the counter and outputting the result;
the method is implemented by the following steps:
step 1, a comparator samples input pixel voltage:
sampling switch SSWhen closed, the pixel voltage VpixelThe sampled pixel voltage is sampled to the negative input end of the comparator, then the sampling switch is switched off, and the negative input end of the comparator is the sampled pixel voltage;
step 2, after the sampling in step 1 is finished, under the control of a clock signal, a slope generator generates a nonlinear slope, and a counter starts to count at the same time:
step 2.1, under the control of the clock signal, the ramp generator starts to generate a ramp, and the ramp is divided into five regions according to the distribution condition of the cell gray values: the cell nucleus, the nucleus cytoplasm margin, the cytoplasm, the cell membrane and the sheath fluid, wherein the corresponding digital codes of the five regions are respectively: 0-255, 256-345, 346-652, 653-742, 743-1023;
step 2.2, realizing a nonlinear slope, designing 5 current steering DACs by combining the five areas divided in the step 2.1, enabling the output current of each current steering DAC to flow through the same reference resistor, and designing a corresponding reference current at each current steering DAC, namely realizing the nonlinear slope at the output end of a slope generator;
step 2.3, correspondingly designing 5 counters according to the 5 current steering DACs designed in step 2.2, wherein each counter starts counting from 0, each counter only counts the digital code value of the area, and finally outputting a voltage value generating a nonlinear ramp through the counter as follows:
Vout＝(D1×I1+D2×I2+Λ+D5×I5)·R (1)
in the formula, D1，···，D5Is the code value of the counter 1-5, and R is the reference resistance;
and 3, the comparator outputs and overturns according to the change of the voltage difference value of the positive input end and the negative input end, and the register outputs the value of the counter at the moment.
2. The method according to claim 1, wherein the working process of the 5 counters in the step 2.3 is specifically as follows:
firstly, the counter 1 starts counting, the current steering DAC corresponding to the counter 1 starts outputting current to generate a first-stage slope, the counter 1 outputs a carry signal CO1 after counting is finished, the CO1 is changed to 1, the latch latches the value of the counter 1, meanwhile, the counter 2 starts counting, the current steering DAC corresponding to the counter 2 starts outputting a second-stage current to generate a second-stage slope, and so on until the counter 5 finishes counting.
3. The method for improving the contrast ratio of the CMOS image sensor according to claim 1, wherein the step 3 specifically comprises:
the comparator compares the sampled pixel voltage with the ramp voltage, when the comparison is started, the comparator outputs 0, the ramp voltage is continuously increased, when the ramp voltage is equal to the pixel voltage, the output of the comparator starts to turn over and jump from 0 to 1, after the latch detects the change of the rising edge of the input signal, the rising edge is output to the register, the register stores and then outputs the value of the counter at the moment of the rising edge, and the output code value is the digital quantity quantized by the comparator.
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