CN110943946A - Channel equalization processing system and method - Google Patents

Channel equalization processing system and method Download PDF

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CN110943946A
CN110943946A CN201911228079.2A CN201911228079A CN110943946A CN 110943946 A CN110943946 A CN 110943946A CN 201911228079 A CN201911228079 A CN 201911228079A CN 110943946 A CN110943946 A CN 110943946A
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CN110943946B (en
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陈致豪
贺江
杨飞
胡明武
杨健
袁勇
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CHENGDU GLOBAL-WAY COMMUNICATION TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure

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Abstract

The invention discloses a channel equalization processing system and a method, wherein the system acquires a training sequence and a pilot training sequence inserted by a sending data frame, a receiving end receives a signal and acquires the channel impact response of the received signal; the system carries out zero filling processing on one path of the received signal to obtain a received data vector, carries out pilot frequency processing and channel estimation on the other path of the received signal, carries out mean value processing on the signal and obtains frequency response and frequency domain response; the system acquires the noise variance, calculates an equalization coefficient, performs equalization processing on the signal and feeds back the result to the signal processing unit; the system calculates and outputs a signal. The invention improves the accuracy and stability of channel estimation, improves the frequency domain equalization performance and enhances the equalization convergence performance.

Description

Channel equalization processing system and method
Technical Field
The present invention belongs to the field of communication technology, and in particular, relates to a channel equalization processing system and method.
Background
In high-speed wireless link transmission, a transmission signal is influenced by absorption, reflection, refraction and diffraction in a propagation process, so that signal components reach a receiver from a multipath direction, different propagation delays are generated, the phase and amplitude are random, signal distortion and waveform broadening are caused, and the accuracy of the signal reaching the receiver is seriously influenced.
In the traditional channel estimation, the randomness of environmental noise and phase noise causes the instability of channel estimation, and meanwhile, the FFT operation is more sensitive to the fluctuation of the impulse response of a channel, so that the poor equalization convergence is caused.
Disclosure of Invention
The present invention provides a channel equalization processing system to solve the above problems, including a signal receiving module, a zero padding processing module, a pilot processing module, a channel estimation module, a data processing unit, a noise variance calculating unit, an equalizer, a feedback unit and an output unit;
the first output end of the channel receiving module is connected with the first input end of the data processing unit through the zero padding processing module; the second output end of the channel receiving module, the pilot frequency processing module, the channel estimation module and the second input end of the data processing unit are connected in sequence;
the output end of the data processing unit is respectively connected with the first input end of the equalizer, the first input end of the feedback unit and the output unit;
the noise variance calculation unit is connected with a second input end of the equalizer; the output end of the equalizer is connected with the second input end of the feedback unit; and the output end of the feedback unit is connected with the third input end of the data processing unit.
A channel equalization processing method comprises the following steps:
s1, the system acquires the training sequence and pilot training sequence inserted by the data frame, the receiving end receives the signal and acquires the channel impact response of the received signal;
s2, the system carries out zero filling processing on one path of the received signal to obtain a received data vector, carries out pilot frequency processing and channel estimation on the other path of the received signal, carries out mean value processing on the signal and obtains frequency response and frequency domain response;
s3, the system acquires the noise variance, calculates the equalizing coefficient, equalizes the signal and feeds back the result to the signal processing unit;
s4, the system calculates and outputs the signal.
The invention has the beneficial effects that: according to the invention, through equalization processing, the traditional channel estimation is improved, the limited length of an FPGA IP core is met through zero padding, the real-time response of the estimated channel is realized by using the mean value of the front pilot frequency and the rear pilot frequency as prior information, the linear value of the channel is closer, and the influence caused by channel noise is further reduced, so that the accuracy of the channel estimation is improved, the number of channel impulse response points is reduced, the effective part is intercepted, the frequency domain equalization performance is greatly improved, and the equalization convergence performance is enhanced.
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FIG. 1 is a system block diagram of the present invention;
fig. 2 is a schematic diagram of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings in which:
as shown in fig. 1, the channel equalization processing system of the present invention includes a signal receiving module, a zero padding processing module, a pilot processing module, a channel estimation module, a data processing unit, a noise variance calculating unit, an equalizer, a feedback unit, and an output unit.
The first output end of the channel receiving module is connected with the first input end of the data processing unit through the zero padding processing module; the second output end of the channel receiving module, the pilot frequency processing module, the channel estimation module and the second input end of the data processing unit are connected in sequence; the output end of the data processing unit is respectively connected with the first input end of the equalizer, the first input end of the feedback unit and the output unit; the noise variance calculation unit is connected with a second input end of the equalizer; the output end of the equalizer is connected with the second input end of the feedback unit; and the output end of the feedback unit is connected with the third input end of the data processing unit.
Further, the data processing unit is an FPGA IP core.
Further, the equalizer is an SC-FDE frequency domain equalizer.
A channel equalization processing method comprises the following steps:
s1, the system acquires the training sequence and pilot training sequence inserted by the data frame, the receiving end receives the signal and acquires the channel impact response of the received signal;
s2, the system carries out zero filling processing on one path of the received signal to obtain a received data vector, carries out pilot frequency processing and channel estimation on the other path of the received signal, carries out mean value processing on the signal and obtains frequency response and frequency domain response;
s3, the system acquires the noise variance, calculates the equalizing coefficient, equalizes the signal and feeds back the result to the signal processing unit;
s4, the system calculates and outputs the signal.
Further, the receiving and processing of the signal by the receiving end specifically includes: let n be the number of signals, n be a positive integer, and transmit signal be x'nThe said transmitted signal includes pre-training word uw1Sending data bit xnWith post-training uw2Pilot training sequence uw3，hnFor the receiver channel impulse response, vnFor additive white Gaussian noise, the received signal is ynLet us order
Figure BDA0002302785630000031
Then the received signal:
Figure BDA0002302785630000032
further, let n + m satisfy the length of the FPGAIP core, yk' is the received data vector after zero padding processing, namely:
yk'＝[yn,zerosm]。
further, the pilot processing specifically includes: receiving signal UW1Transforming response values, UW, for pre-training characters2The response value is transformed for the post-training word, and the mean value of the frequency domain values is UWave
UW1＝fft(uw1')；
UW2＝fft(uw2')；
Figure BDA0002302785630000041
Further, the channel estimation specifically includes: let H be the channel frequency response, H' be the channel estimation impulse response, Hn'is the channel impulse response after zero padding, H' is the frequency response under channel estimation, UWaveIs the mean of the frequency domain values, UW3Is the training sequence on the signal frequency domain, i is the number of pilot training sequence paths, then
Figure BDA0002302785630000042
h'＝ifft(H)；
H'＝fft(hn')。
Further, the equalization coefficient calculation process is as follows: let H 'be the frequency response under channel estimation, H'*Is the conjugate of H', P is the power of the signal, σ2Is an additive white Gaussian noise variance, the coefficient W is equalizedkComprises the following steps:
Figure BDA0002302785630000043
further, the output signal calculation process is as follows: is provided with YkIs the signal frequency domain response, Y'kFor the feedback signal after signal equalization processing, then
Y'k＝Wk*Yk
Then the output signal:
yk＝ifft(Y'k)。
the system firstly processes the frame structure, because the length of the front and back pilot frequency must be larger than the maximum time delay of data transmission, the length of the training word is 128 selected in the item, and the pilot frequency training sequence of 128bit is inserted before and after the data frame is sent, so as to obtain [ uw1,xn,uw2]And in order to save bandwidth in a continuous data stream, pilots are multiplexed in the channel estimation, i.e. always uw of the first frame2Will continue to be used as uw for the second frame1
In the pilot frequency processing module, the pre-training sequence UW and the post-training sequence UW which are inserted in the frequency domain are processed1，UW2Mean value processing to obtain UWave。
In the channel estimation module, the obtained average training sequence UWaveWith a known training sequence UW3And jointly obtaining the estimated channel impact response. Due to the influence of noise in a channel, only the first 10 bits of the effective impulse response are intercepted during fast Fourier operation, and the rest 4086-bit data is subjected to zero padding processing and enters an FPGA IP core for processing.
According to the invention, through equalization processing, the traditional channel estimation is improved, the limited length of an FPGA IP core is met through zero padding, the average value of front and rear pilot frequencies is used as prior information, the real-time response of the estimated channel is realized, the linear value of the channel is closer, and the influence caused by channel noise is further reduced, so that the accuracy and the stability of the channel estimation are improved, the number of channel impulse response points is reduced, the effective part is intercepted, the frequency domain equalization performance is greatly improved, and the equalization convergence performance is enhanced.
The invention adopts the multiplexing operation of the FPGA IP core, controls the input and the output by the state machine, and carries out the time delay input on the data by the register and the counter, thereby avoiding the superposition and the conflict of the input data.
The technical solution of the present invention is not limited to the limitations of the above specific embodiments, and all technical modifications made according to the technical solution of the present invention fall within the protection scope of the present invention.

Claims (10)

1. A channel equalization processing system is characterized by comprising a signal receiving module, a zero padding processing module, a pilot frequency processing module, a channel estimation module, a data processing unit, a noise variance calculating unit, an equalizer, a feedback unit and an output unit;
the first output end of the channel receiving module is connected with the first input end of the data processing unit through the zero padding processing module; the second output end of the channel receiving module, the pilot frequency processing module, the channel estimation module and the second input end of the data processing unit are connected in sequence;
the output end of the data processing unit is respectively connected with the first input end of the equalizer, the first input end of the feedback unit and the output unit;
the noise variance calculation unit is connected with a second input end of the equalizer; the output end of the equalizer is connected with the second input end of the feedback unit; and the output end of the feedback unit is connected with the third input end of the data processing unit.
2. The channel equalization processing system of claim 1, wherein said data processing unit is an FPGAIP core.
3. The channel equalization processing system of claim 1, wherein the equalizer is an SC-FDE frequency domain equalizer.
4. A channel equalization processing method, comprising the steps of:
s1, the system acquires the training sequence and pilot training sequence inserted by the data frame, the receiving end receives the signal and acquires the channel impact response of the received signal;
s2, the system carries out zero filling processing on one path of the received signal to obtain a received data vector, carries out pilot frequency processing and channel estimation on the other path of the received signal, carries out mean value processing on the signal and obtains frequency response and frequency domain response;
s3, the system acquires the noise variance, calculates the equalizing coefficient, equalizes the signal and feeds back the result to the signal processing unit;
s4, the system calculates and outputs the signal.
5. The method according to claim 4, wherein the receiving and processing of the signal by the receiving end specifically comprises:
let n be the number of signals, n be a positive integer, and transmit signal be x'nThe said transmitted signal includes pre-training word uw1Sending data bit xnWith post-training uw2Pilot training sequence uw3，hnFor the receiver channel impulse response, vnFor additive white Gaussian noise, the received signal is ynLet us order
Figure FDA0002302785620000021
Figure FDA0002302785620000022
Then the received signal:
Figure FDA0002302785620000023
6. the channel equalization processing method according to claim 4, wherein the zero padding processing specifically includes: let n + m satisfy the length of FPGA IP core, yk' is the received data vector after zero padding processing, namely:
yk'＝[yn,zerosm]。
7. the method of claim 4, wherein the pilot processing specifically includes:
receiving signal UW1Transforming response values, UW, for pre-training characters2The response value is transformed for the post-training word, and the mean value of the frequency domain values is UWave
UW1＝fft(uw1')；
UW2＝fft(uw2')；
Figure FDA0002302785620000024
8. The channel equalization processing method according to claim 4, wherein the channel estimation specifically includes:
let H be the channel frequency response, H' be the channel estimation impulse response, Hn'is the channel impulse response after zero padding, H' is the frequency response under channel estimation, UWaveIs the mean of the frequency domain values, UW3Is the training sequence on the signal frequency domain, i is the number of pilot training sequence paths, then
Figure FDA0002302785620000031
h'＝ifft(H)；
H'＝fft(hn')。
9. The channel equalization processing method according to claim 4, wherein the equalization coefficient calculation process is: let H 'be the frequency response under channel estimation, H'*Is the conjugate of H', P is the power of the signal, σ2Is an additive white Gaussian noise variance, the coefficient W is equalizedkComprises the following steps:
Figure FDA0002302785620000032
10. the channel equalization processing method as claimed in claim 4, wherein the output signal calculation process is:
is provided with YkIs the signal frequency domain response, Y'kFor the feedback signal after signal equalization processing, then
Y'k＝Wk*Yk
Then the output signal:
yk＝ifft(Y'k)。
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