CN110943822B - Multi-scroll chaotic signal generator based on sinusoidal control - Google Patents
Multi-scroll chaotic signal generator based on sinusoidal control Download PDFInfo
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Abstract
The invention discloses a multi-scroll chaotic signal generator based on sinusoidal control, which comprises: basic chaotic signal generating circuit N1, sine function generating circuit N2, sequence generator N3 for generating switching control function, node f and multiplier MUL 4 (ii) a A node x of the basic chaotic signal generating circuit N1 is connected with the input end of the sine function generating circuit N2; the node z of the basic chaotic signal generating circuit N1 is connected with the input end of a sequence generator N3, and the output end of the sine function generating circuit N2 is connected with a multiplier MUL 4 Is connected to the first input of the sequence generator N3, the output of the sequence generator N3 being connected to the multiplier MUL 4 Is connected to the second input terminal of the multiplier MUL, the multiplier MUL 4 The output terminal of which is connected with the input terminal of the basic chaotic signal generating circuit N1 through a node f. The invention is mainly used in the technical field of chaotic communication.
Description
Technical Field
The invention relates to the technical field of chaotic communication, in particular to a multi-scroll chaotic signal generator based on sinusoidal control.
Background
Since the first chaotic system was discovered by Lorenz in the 60's of the 20 th century, the chaotic system has attracted wide attention in the fields of image encryption, information security and the like because of its characteristics of strong sensitivity, dependence, unpredictability and the like on initial conditions and parameters. The chaos is a deterministic random-like process in a nonlinear power system and has ergodicity, mixing and exponential divergence. The low-dimensional chaotic system has the problems of insufficient key space, low complexity of chaotic sequences, poor anti-deciphering capacity of the system, low safety and the like due to low system dimension.
Disclosure of Invention
The present invention is directed to a multi-scroll chaotic signal generator based on sinusoidal control, so as to solve one or more technical problems of the prior art and provide at least one of the advantages.
The solution of the invention for solving the technical problem is as follows: a multi-scroll chaotic signal generator based on sinusoidal control, comprising: basic chaotic signal generating circuit N1, sine function generating circuit N2, sequence generator N3 for generating switching control function, node f and multiplier MUL 4 (ii) a Of basic chaotic signal-generating circuits N1The node x is connected with the input end of the sine function generating circuit N2; the node z of the basic chaotic signal generating circuit N1 is connected with the input end of a sequence generator N3, and the output end of the sine function generating circuit N2 is connected with a multiplier MUL 4 Is connected to the first input of the sequence generator N3, the output of the sequence generator N3 is connected to the multiplier MUL 4 Is connected to the second input terminal of the multiplier MUL, the multiplier MUL 4 The output terminal of which is connected with the input terminal of the basic chaotic signal generating circuit N1 through a node f.
Further, the sine function generating circuit N2 includes: operational amplifier OP 10 Operational amplifier OP 11 Resistance R 20 And a resistor R 21 Resistance R 22 Resistance R 23 And a sine function generating chip configured to have an amplitude of ten times;
the resistor R 20 Is connected to node x, the resistor R 20 Respectively connected with a resistor R 21 Left end of (3), operational amplifier OP 10 Is connected to the negative input terminal of the resistor R 21 Respectively with an operational amplifier OP 10 Output terminal of (2), resistor R 22 Is connected to the left end of the resistor R 22 Respectively connected with a resistor R 23 Left end, operational amplifier OP 11 Is connected to the negative input terminal of the resistor R 23 Respectively with an operational amplifier OP 11 Is connected with the input end of the sine function generating chip, and the output end of the sine function generating chip is connected with the multiplier MUL 4 Is connected.
Further, the basic chaotic signal generating circuit N1 includes: operational amplifier OP 1 Operational amplifier OP 2 Operational amplifier OP 3 Operational amplifier OP 4 Operational amplifier OP 5 Operational amplifier OP 6 Operational amplifier OP 7 Operational amplifier OP 8 Operational amplifier OP 9 Resistance R 1 And a resistor R 2 And a resistor R 3 And a resistor R 4 And a resistor R 5 Resistance R 6 Resistance R 7 And a resistor R 8 And a resistorR 9 Resistance R 10 Resistance R 11 Resistance R 12 And a resistor R 13 And a resistor R 14 Resistance R 15 And a resistor R 16 Resistance R 17 Resistance R 18 Resistance R 19 Capacitor C 1 Capacitor C 2 Node x, node-x, node y, node-y, node z, node-z and multiplier MUL 1 ；
The operational amplifier OP 1 Respectively connected with the resistor R 1 Right end of (1), resistance R 2 Right end of (3), resistance R 3 Is connected to the left end of the resistor R 3 Respectively with an operational amplifier OP 1 Output terminal of (1), resistor R 4 Is connected to the left end of the resistor R 4 Respectively with an operational amplifier OP 2 Negative input terminal of (1), capacitor C 1 Is connected to the left end of the capacitor C 1 Is respectively connected with the node-x and the resistor R 5 Is connected to the left end of the resistor R 5 Respectively with an operational amplifier OP 3 Negative input terminal of (3), resistor R 6 Is connected to the left end of the resistor R 6 Respectively with an operational amplifier OP 3 Is connected to node x, the resistor R 1 Is connected to node-y, the resistor R 2 Is connected to node-z;
the operational amplifier OP 4 Respectively with the resistor R 7 Right end of (1), resistance R 8 Right end of (3), resistance R 9 The left end of the resistor R is connected with 9 Respectively with an operational amplifier OP 4 Output terminal of (1), resistor R 10 Is connected to the left end of the resistor R 10 Respectively with an operational amplifier OP 5 Negative input terminal of (1), capacitor C 2 Is connected to the left end of the capacitor C 2 With node-y and resistor R, respectively 11 The left end of the resistor R is connected with 11 Respectively with an operational amplifier OP 6 Negative input terminal of (3), resistor R 12 The left end of the resistor R is connected with 12 Respectively with an operational amplifier OP 6 Is connected to node y, the resistor R 7 Is connected to node-z, the resistor R 8 The left end of (a) is connected with a node y;
the operational amplifier OP 7 Respectively connected with the resistor R 13 Right end of (3), resistance R 14 Right end of (1), resistance R 15 Right end of (3), resistance R 16 Is connected to the left end of the resistor R 16 Respectively with an operational amplifier OP 7 Output terminal of (1), resistor R 17 Is connected to the left end of the resistor R 17 Respectively with an operational amplifier OP 8 Negative input terminal of (1), capacitor C 3 Is connected to the left end of the capacitor C 3 Is respectively connected with the node-z and the resistor R 18 The left end of the resistor R is connected with 18 Respectively with an operational amplifier OP 9 Negative input terminal of (3), resistor R 19 Is connected to the left end of the resistor R 19 Respectively with an operational amplifier OP 9 Is connected to node z, the resistor R 13 Is connected with a node y, and the resistor R 14 Left end of and multiplier MUL 1 Is connected to the output of the multiplier MUL, the multiplier MUL 1 Is connected to node-y, said multiplier MUL 1 Is connected to node z, the resistor R 15 The left end of (a) is connected with a node f;
the operational amplifier OP 1 Positive input terminal of, operational amplifier OP 2 Positive input terminal of, operational amplifier OP 3 Positive input terminal of, operational amplifier OP 4 Positive input terminal of, operational amplifier OP 5 Positive input terminal of (1), operational amplifier OP 6 Positive input terminal of, operational amplifier OP 7 Positive input terminal of, operational amplifier OP 8 And the operational amplifier OP 9 The positive input ends of which are respectively connected to the ground.
Further, the sequencer N3 includes: operational amplifier OP 16 Operational amplifier OP 17 Operational amplifier OP 18 Operational amplifier OP 19 Operational amplifier OP 20 Resistance R 36 Resistance R 37 Resistance R 38 Resistance R 39 And a resistor R 40 Resistance R 41 And a resistor R 42 And a resistor R 43 Node U 1 And node U 2 ；
The operational amplifier OP 16 Is connected to node z, said operational amplifier OP 16 Positive input end and node U of 1 Connected, said operational amplifier OP 16 Output terminal and resistor R 36 The left end of the resistor R is connected with 36 Respectively connected with a resistor R 37 Left end, operational amplifier OP 17 Is connected to the negative input terminal of the resistor R 37 Respectively with an operational amplifier OP 17 Output terminal of (2), resistor R 38 The left end of the resistor R is connected with 38 Respectively connected with a resistor R 39 Left end, operational amplifier OP 20 Is connected to the negative input terminal of the resistor R 39 Respectively with an operational amplifier OP 20 Output terminal of (2), multiplier MUL 4 Is connected to the second input terminal of the first,
the operational amplifier OP 18 Is connected to node z, said operational amplifier OP 18 Positive input end and node U of 2 Connected, said operational amplifier OP 18 Output terminal and resistor R 40 Is connected to the left end of the resistor R 40 Respectively connected with a resistor R 41 Left end, operational amplifier OP 19 Is connected to the negative input terminal of the resistor R 41 Respectively with an operational amplifier OP 19 Output terminal of (1), resistor R 42 Is connected to the left end of the resistor R 42 Respectively with a resistor R 43 Upper end, operational amplifier OP 20 Are connected with the positive input end of the main body;
the operational amplifier OP 17 Positive input terminal of (1), operational amplifier OP 19 Positive input terminal of (2) and resistor R 43 Are respectively connected to the ground.
Further, the resistors adopted by the basic chaotic signal generating circuit N1, the sine function generating circuit N2 and the sequencer N3 are all precision adjustable resistors or precision adjustable potentiometers.
Further, the model of the sine function generating chip is AD639.
The invention has the beneficial effects that: the invention can generate more scrolls, has higher complexity of the chaotic sequence, larger key space and stronger system anti-deciphering capacity and has better potential application value in the fields of secret communication, chaotic control and the like.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings described are only some embodiments of the invention, not all embodiments, and that a person skilled in the art, without inventive effort, can also derive other designs and drawings from these drawings.
Fig. 1 is a schematic circuit connection diagram between a sine function generating circuit N2 and a sequencer N3;
fig. 2 is a circuit connection schematic diagram of the basic chaotic signal generating circuit N1.
Detailed Description
Reference will now be made in detail to the present embodiments of the present invention, preferred embodiments of which are illustrated in the accompanying drawings, wherein the drawings are provided for the purpose of visually supplementing the description in the specification and so forth, and which are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as up, down, front, rear, left, right, etc., is the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of the description of the present invention, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the invention, if words such as "a number" or the like are used, the meaning is one or more, the meaning of a plurality is two or more, more than, less than, more than, etc. are understood as not including the number, and more than, less than, more than, etc. are understood as including the number.
In the description of the present invention, unless otherwise explicitly defined, terms such as setup, installation, connection, and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the terms in the present invention in combination with the detailed contents of the technical solutions.
Embodiment 1, referring to fig. 1 and 2, a sinusoidal control based multi-scroll chaotic signal generator includes: basic chaotic signal generating circuit N1, sine function generating circuit N2, sequence generator N3 for generating switching control function, node f and multiplier MUL 4 。
Wherein the basic chaotic signal generating circuit N1 includes: operational amplifier OP 1 Operational amplifier OP 2 Operational amplifier OP 3 Operational amplifier OP 4 Operational amplifier OP 5 Operational amplifier OP 6 Operational amplifier OP 7 Operational amplifier OP 8 Operational amplifier OP 9 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 5 Resistance R 6 And a resistor R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 And a resistor R 12 Resistance R 13 And a resistor R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Resistance R 19 Capacitor C 1 Capacitor C 2 Node x, node-x, node y, node-y, node z, node-z and multiplier MUL 1 (ii) a The operational amplifier OP 1 Respectively with the resistor R 1 Right end of (1), resistance R 2 Right end of (1), resistance R 3 Is connected to the left end of the resistor R 3 Respectively with an operational amplifier OP 1 Output terminal of (2), resistor R 4 Is connected to the left end of the resistor R 4 Respectively with an operational amplifier OP 2 Negative input terminal of (1), capacitor C 1 Is connected to the left end of the capacitor C 1 Is respectively connected with the node-x and the resistor R 5 Is connected to the left end of the resistor R 5 Respectively with an operational amplifier OP 3 Negative input terminal of (3), resistor R 6 Is connected to the left end of the resistor R 6 Respectively with an operational amplifier OP 3 Is connected to node x, the resistor R 1 Is connected to node-y, the resistor R 2 Is connected to node-z; the operational amplifier OP 4 Respectively with the resistor R 7 Right end of (1), resistance R 8 Right end of (1), resistance R 9 Is connected to the left end of the resistor R 9 Respectively with an operational amplifier OP 4 Output terminal of (1), resistor R 10 Is connected to the left end of the resistor R 10 Respectively with an operational amplifier OP 5 Negative input terminal of (1), capacitor C 2 Is connected to the left end of the capacitor C 2 With node-y and resistor R, respectively 11 Is connected to the left end of the resistor R 11 Respectively with an operational amplifier OP 6 Negative input terminal of (2), resistor R 12 Is connected to the left end of the resistor R 12 Respectively with an operational amplifier OP 6 Is connected to node y, the resistor R 7 Is connected to node-z, the resistor R 8 The left end of (a) is connected with a node y; the operational amplifier OP 7 Respectively with the resistor R 13 Right end of (3), resistance R 14 Right end of (1), resistance R 15 Right end of (3), resistance R 16 Is connected to the left end of the resistor R 16 Respectively with an operational amplifier OP 7 Output terminal of (1), resistor R 17 The left end of the resistor R is connected with 17 Respectively with an operational amplifier OP 8 Negative input terminal of (1), capacitor C 3 Is connected to the left end of the capacitor C 3 Is respectively connected with the node-z and the resistor R 18 Is connected to the left end of the resistor R 18 Respectively with an operational amplifier OP 9 Negative input terminal of (3), resistor R 19 The left end of the resistor R is connected with 19 Respectively with an operational amplifier OP 9 Is connected to node z, the resistor R 13 To the left ofTerminal is connected to node y, and resistor R 14 Left end of (D) and multiplier MUL 1 Is connected to the output of the multiplier MUL, the multiplier MUL 1 Is connected to node-y, said multiplier MUL 1 Is connected to node z, the resistor R 15 The left end of (a) is connected with a node f; the operational amplifier OP 1 Positive input terminal of (1), operational amplifier OP 2 Positive input terminal of, operational amplifier OP 3 Positive input terminal of, operational amplifier OP 4 Positive input terminal of, operational amplifier OP 5 Positive input terminal of, operational amplifier OP 6 Positive input terminal of (1), operational amplifier OP 7 Positive input terminal of, operational amplifier OP 8 And the operational amplifier OP 9 Respectively, are connected to ground.
The sine function generating circuit N2 includes: operational amplifier OP 10 Operational amplifier OP 11 Resistance R 20 And a resistor R 21 Resistance R 22 Resistance R 23 And a sine function generating chip configured to have an amplitude ten times larger; the resistance R 20 Is connected to node x, the resistor R 20 Respectively connected with a resistor R 21 Left end, operational amplifier OP 10 Is connected to the negative input terminal of the resistor R 21 Respectively with an operational amplifier OP 10 Output terminal of (1), resistor R 22 Is connected to the left end of the resistor R 22 Respectively with a resistor R 23 Left end, operational amplifier OP 11 Is connected to the negative input terminal of the resistor R 23 Respectively with an operational amplifier OP 11 Is connected with the input end of the sine function generating chip, and the output end of the sine function generating chip is connected with the multiplier MUL 4 Is connected to the first input terminal.
The sequencer N3 includes: operational amplifier OP 16 Operational amplifier OP 17 Operational amplifier OP 18 Operational amplifier OP 19 Operational amplifier OP 20 And a resistor R 36 Resistance R 37 Resistance R 38 And a resistor R 39 Resistance R 40 Resistance R 41 Resistance R 42 And a resistor R 43 Node U 1 And node U 2 (ii) a The operational amplifier OP 16 Is connected to node z, said operational amplifier OP 16 Positive input end and node U of 1 Connected, said operational amplifier OP 16 Output terminal and resistor R 36 Is connected to the left end of the resistor R 36 Respectively connected with a resistor R 37 Left end of (3), operational amplifier OP 17 Is connected to the negative input terminal of the resistor R 37 Respectively with an operational amplifier OP 17 Output terminal of (1), resistor R 38 Is connected to the left end of the resistor R 38 Respectively with a resistor R 39 Left end of (3), operational amplifier OP 20 Is connected to the negative input terminal of the resistor R 39 Respectively with an operational amplifier OP 20 Output terminal of (2), multiplier MUL 4 Is connected with the second input end; the operational amplifier OP 18 Is connected to node z, said operational amplifier OP 18 Positive input end of and node U 2 Connected, said operational amplifier OP 18 Output terminal and resistor R 40 Is connected to the left end of the resistor R 40 Respectively with a resistor R 41 Left end, operational amplifier OP 19 Is connected to the negative input terminal of the resistor R 41 Respectively with an operational amplifier OP 19 Output terminal of (2), resistor R 42 Is connected to the left end of the resistor R 42 Respectively connected with a resistor R 43 Upper end of (OP), operational amplifier 20 Is connected with the positive input end of the switch; the operational amplifier OP 17 Positive input terminal of, operational amplifier OP 19 Positive input terminal of (2) and resistor R 43 Are respectively connected to the ground.
The state equation of the multi-scroll chaotic signal generator based on cosine control is as follows:
gate＝0.5[sgn(z-U 2 )-sgn(z-U 1 )]
f＝[cos(4wx)gate]
in the above formula, f is represented as a signal at node f, a 11 ＝3，b 11 ＝0.8，b 12 ＝8，c 11 ＝3，c 12 ＝0.2，c 13 ＝0.32，
In the expression of d, the symbol [ ] ]]Expressed as an integer, R 2 Expressed as resistance R 2 In k Ω, U 1 Represents node U 1 Level value of (U) 2 Represents a node U 2 Level value of (d).
U 1 And U 2 The expression of (a) is:
T＝2π/(wk)
U 1 ＝(N+0.25)*T，
U 2 ＝-(M+0.75)*T
in the above formula, w =4, k =5, m and N are variables, and the adjustment resistance R is 2 To change the value of d to produce different wrap numbers.
Selection of circuit elements and supply voltage of the invention: all operational amplifiers in fig. 1 and 2 are model TL082. All multipliers in fig. 1 and 2 have the model number of AD633. In order to facilitate circuit experiments and ensure the accuracy of the resistance value, all the resistors in fig. 1 and 2 adopt a precision resistor or a precision adjustable potentiometer. Table 1 shows resistance parameters of the basic chaotic signal generating circuit N1, the sine function generating circuit N2, and the sequencer N3, specifically:
| R 1 | 33.3 | R 2 | variable resistance value | R 3 | 100 |
| R 4 | 50 | R 5 | 10 | R 6 | 10 |
| R 7 | 14.3 | R 8 | 125 | R 9 | 100 |
| R 10 | 50 | R 11 | 10 | R 12 | 10 |
| R 13 | 50 | R 14 | 50 | R 15 | 312.5 |
| R 16 | 100 | R 17 | 50 | R 18 | 10 |
| R 19 | 10 | R 20 | 2 | R 21 | 10 |
| R 22 | 10 | R 23 | 10 | R 24 | 9 |
| R 25 | 9 | R 26 | 9 | R 27 | 9 |
| R 28 | 9 | R 29 | 9 | R 30 | 9 |
| R 31 | 9 | R 32 | 10 | R 33 | 8 |
| R 34 | 10 | R 35 | 100 | R 36 | 13.5 |
| R 37 | 0.5 | R 38 | 9 | R 39 | 9 |
| R 40 | 13.5 | R 41 | 0.5 | R 42 | 9 |
| R 43 | 9 |
Table 1;
in table 1, the unit of resistance is k Ω.
Table 2 shows node V 1 And node V 2 The parameter values of (1) are specifically:
| V 1 | 5 | V 2 | 1.25 |
table 2;
in table 2, the unit of the parameter value is V.
Table 3 shows the values of the parameters for the capacitance in nF.
| C 1 | 33 | C 2 | 33 | C 3 | 33 |
Table 3;
table 4 shows the relationship between the number of scrolls and the parameter d obtained by the multi-scroll chaotic signal generator, which is specifically:
table 4;
as can be seen from table 4, the multi-scroll chaotic signal generator of the present invention can generate a variable and considerable amount of multi-scroll signals by changing the resistor R2 (i.e., changing the parameter d). The encryption capability is improved.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the invention is not limited to the details of the embodiments shown, but is capable of various modifications and substitutions without departing from the spirit of the invention.
Claims (3)
1. A multi-scroll chaotic signal generator based on sinusoidal control is characterized by comprising: basic chaotic signal generating circuit N1, sine function generating circuit N2, for generating a sliceSequence generator N3, node f and multiplier MUL for changing control function 4 (ii) a A node x of the basic chaotic signal generating circuit N1 is connected with the input end of the sine function generating circuit N2; the node z of the basic chaotic signal generating circuit N1 is connected with the input end of a sequence generator N3, and the output end of the sine function generating circuit N2 is connected with a multiplier MUL 4 Is connected to the first input of the sequence generator N3, the output of the sequence generator N3 being connected to the multiplier MUL 4 Is connected to the second input terminal of the multiplier MUL, the multiplier MUL 4 The output end of the basic chaotic signal generating circuit is connected with the input end of a basic chaotic signal generating circuit N1 through a node f;
the sine function generating circuit N2 includes: operational amplifier OP 10 Operational amplifier OP 11 Resistance R 20 Resistance R 21 Resistance R 22 Resistance R 23 And a sine function generating chip configured to have an amplitude ten times larger;
the resistor R 20 Is connected to node x, the resistor R 20 Respectively with a resistor R 21 Left end, operational amplifier OP 10 Is connected to the negative input terminal of the resistor R 21 Respectively with an operational amplifier OP 10 Output terminal of (1), resistor R 22 The left end of the resistor R is connected with 22 Respectively with a resistor R 23 Left end, operational amplifier OP 11 Is connected to the negative input terminal of the resistor R 23 Respectively with an operational amplifier OP 11 Is connected with the input end of the sine function generating chip, and the output end of the sine function generating chip is connected with the multiplier MUL 4 Is connected with the first input end of the first switch;
the basic chaotic signal generating circuit N1 includes: operational amplifier OP 1 Operational amplifier OP 2 Operational amplifier OP 3 Operational amplifier OP 4 Operational amplifier OP 5 Operational amplifier OP 6 Operational amplifier OP 7 Operational amplifier OP 8 Operational amplifier OP 9 Resistance R 1 Resistance R 2 Resistance R 3 Resistance R 4 Resistance R 5 Resistance R 6 Resistance R 7 Resistance R 8 Resistance R 9 Resistance R 10 Resistance R 11 Resistance R 12 Resistance R 13 And a resistor R 14 Resistance R 15 Resistance R 16 Resistance R 17 Resistance R 18 Resistance R 19 Capacitor C 1 Capacitor C 2 Node x, node-x, node y, node-y, node z, node-z and multiplier MUL 1 ；
The operational amplifier OP 1 Respectively with the resistor R 1 Right end of (1), resistance R 2 Right end of (1), resistance R 3 Is connected to the left end of the resistor R 3 Respectively with an operational amplifier OP 1 Output terminal of (1), resistor R 4 Is connected to the left end of the resistor R 4 Respectively with an operational amplifier OP 2 Negative input terminal of (1), capacitor C 1 Is connected to the left end of the capacitor C 1 Is respectively connected with the node-x and the resistor R 5 Is connected to the left end of the resistor R 5 Respectively with an operational amplifier OP 3 Negative input terminal of (3), resistor R 6 Is connected to the left end of the resistor R 6 Respectively with an operational amplifier OP 3 Is connected to node x, the resistor R 1 Is connected to node-y, the resistor R 2 Is connected to node-z;
the operational amplifier OP 4 Respectively with the resistor R 7 Right end of (1), resistance R 8 Right end of (3), resistance R 9 The left end of the resistor R is connected with 9 Respectively with an operational amplifier OP 4 Output terminal of (2), resistor R 10 Is connected to the left end of the resistor R 10 Respectively with an operational amplifier OP 5 Negative input terminal of (1), capacitor C 2 Is connected to the left end of the capacitor C 2 Respectively connected with node-y and resistor R 11 The left end of the resistor R is connected with 11 Respectively with an operational amplifier OP 6 Negative input terminal of (3), resistor R 12 Is connected to the left end of the resistor R 12 Respectively and operation of right ends ofAmplifier OP 6 Is connected to node y, the resistor R 7 Is connected to node-z, the resistor R 8 The left end of (a) is connected with a node y;
the operational amplifier OP 7 Respectively connected with the resistor R 13 Right end of (3), resistance R 14 Right end of (3), resistance R 15 Right end of (1), resistance R 16 The left end of the resistor R is connected with 16 Respectively with an operational amplifier OP 7 Output terminal of (2), resistor R 17 Is connected to the left end of the resistor R 17 Respectively with an operational amplifier OP 8 Negative input terminal of (1), capacitor C 3 Is connected to the left end of the capacitor C 3 Is respectively connected with the node-z and the resistor R 18 The left end of the resistor R is connected with 18 Respectively with an operational amplifier OP 9 Negative input terminal of (3), resistor R 19 The left end of the resistor R is connected with 19 Respectively with an operational amplifier OP 9 Is connected to node z, the resistor R 13 Is connected with a node y, and the resistor R 14 Left end of and multiplier MUL 1 Is connected to the output of the multiplier MUL, the multiplier MUL 1 Is connected to node-y, said multiplier MUL 1 Is connected to node z, said resistor R 15 The left end of (a) is connected with a node f;
the operational amplifier OP 1 Positive input terminal of, operational amplifier OP 2 Positive input terminal of (1), operational amplifier OP 3 Positive input terminal of, operational amplifier OP 4 Positive input terminal of, operational amplifier OP 5 Positive input terminal of, operational amplifier OP 6 Positive input terminal of, operational amplifier OP 7 Positive input terminal of, operational amplifier OP 8 And the operational amplifier OP 9 The positive input ends of the two are respectively connected to the ground;
the sequencer N3 includes: operational amplifier OP 16 Operational amplifier OP 17 Operational amplifier OP 18 Operational amplifier OP 19 Operational amplifier OP 20 Resistance R 36 Resistance R 37 Resistance R 38 Resistance R 39 Resistance R 40 And a resistor R 41 Resistance R 42 Resistance R 43 Node U 1 And node U 2 ；
The operational amplifier OP 16 Is connected to node z, said operational amplifier OP 16 Positive input end and node U of 1 Connected, said operational amplifier OP 16 Output terminal and resistor R 36 Is connected to the left end of the resistor R 36 Respectively with a resistor R 37 Left end, operational amplifier OP 17 Is connected to the negative input terminal of the resistor R 37 Respectively with an operational amplifier OP 17 Output terminal of (1), resistor R 38 Is connected to the left end of the resistor R 38 Respectively with a resistor R 39 Left end, operational amplifier OP 20 Is connected to the negative input terminal of the resistor R 39 Respectively with an operational amplifier OP 20 Output terminal of (2), multiplier MUL 4 Is connected to the second input terminal of the first,
the operational amplifier OP 18 Is connected to node z, said operational amplifier OP 18 Positive input end and node U of 2 Connected, said operational amplifier OP 18 Output terminal and resistor R 40 The left end of the resistor R is connected with 40 Respectively with a resistor R 41 Left end, operational amplifier OP 19 Is connected to the negative input terminal of the resistor R 41 Respectively with an operational amplifier OP 19 Output terminal of (1), resistor R 42 Is connected to the left end of the resistor R 42 Respectively with a resistor R 43 Upper end, operational amplifier OP 20 Are connected with the positive input end of the main body;
the operational amplifier OP 17 Positive input terminal of, operational amplifier OP 19 Positive input terminal and resistor R 43 Are respectively connected to the ground.
2. The sinusoidal-control-based multi-scroll chaotic signal generator according to claim 1, wherein: the resistors adopted by the basic chaotic signal generating circuit N1, the sine function generating circuit N2 and the sequence generator N3 are all precision adjustable resistors or precision adjustable potentiometers.
3. The sinusoidal-control-based multi-scroll chaotic signal generator according to claim 1, wherein: the model of the sine function generating chip is AD639.
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