CN110943737B - Charge pump system and nonvolatile memory - Google Patents
Charge pump system and nonvolatile memory Download PDFInfo
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- CN110943737B CN110943737B CN201811109494.1A CN201811109494A CN110943737B CN 110943737 B CN110943737 B CN 110943737B CN 201811109494 A CN201811109494 A CN 201811109494A CN 110943737 B CN110943737 B CN 110943737B
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- charge pump
- delay
- latch
- latch circuit
- inverter
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- 230000003111 delayed effect Effects 0.000 claims description 9
- 230000004044 response Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Embodiments of the present invention provide a charge pump system and a nonvolatile memory, the system comprising: an oscillator unit, a first charge pump unit, a second charge pump unit; the output end of the first delay inverting latch circuit is connected with the input end of the second delay inverting latch circuit and the input end of the first charge pump unit; the output end of the second delay inverting latch circuit is connected with the input end of the inverter and the input end of the second charge pump unit; the first delay inverting latch circuit comprises a first latch enabling end, and the second delay inverting latch circuit comprises a second latch enabling end; the first latch enabling end is connected with the first latch enabling end; the output end of the first charge pump unit is connected with the output end of the second charge pump unit. In the embodiment of the invention, two paths of clock signals without burrs of the oscillator unit are respectively input to the first charge pump unit and the second charge pump unit, so that the response speed of the system is very high, and the overshoot phenomenon can be avoided because the clock signals are free of burrs.
Description
Technical Field
The present invention relates to the field of charge pumps, and more particularly, to a charge pump system and a nonvolatile memory.
Background
In a charge pump system, a charge pump unit typically charges a load on either a rising or falling edge of a clock output current.
In the prior art, as shown in fig. 1, EN is an enable signal, and when EN is generally 1, the oscillator circuit is operated, and when CK0 is output and EN is 0, the oscillator circuit is turned off.
However, the inventors have found in the course of studying the above-described technical solutions that the above-described technical solutions have the following drawbacks: when the oscillator circuit of the prior art is turned off, burrs often occur on the falling edge of EN, so that the charge pump unit performs one more charging operation, and overshoot occurs.
Disclosure of Invention
In view of the above, a charge pump system according to an embodiment of the present invention is provided to avoid overshoot of the charge pump unit.
According to a first aspect of the present invention there is provided a charge pump system comprising:
an oscillator unit, a first charge pump unit, a second charge pump unit;
the oscillator unit includes: the first delay inverting latch circuit, the second delay inverting latch circuit and the inverter;
the first delay inverting latch circuit is used for generating and outputting a first clock signal without burrs; the second delay inverting latch circuit is used for generating and outputting a second clock signal without burrs; the inverter is used for outputting the second clock signal in an inverted mode;
the output end of the first delay inverting latch circuit is connected with the input end of the second delay inverting latch circuit and the input end of the first charge pump unit;
the output end of the second delay inverting latch circuit is connected with the input end of the inverter and the input end of the second charge pump unit;
the first delay inverting latch circuit comprises a first latch enabling end, and the second delay inverting latch circuit comprises a second latch enabling end;
the first latch enabling end is connected with the first latch enabling end and used as an input end of the oscillator unit and used for receiving an enabling signal;
the output end of the first charge pump unit is connected with the output end of the second charge pump unit and is used as a charge pump voltage output end. According to a second aspect of the present invention there is provided a non-volatile memory comprising any of the charge pump systems described above.
The charge pump system in the embodiment of the invention comprises an oscillator unit, a first charge pump unit and a second charge pump unit; the oscillator unit includes: the first delay inverting latch circuit, the second delay inverting latch circuit and the inverter; the output end of the first delay inverting latch circuit is connected with the input end of the second delay inverting latch circuit and the input end of the first charge pump unit; the output end of the second delay inverting latch circuit is connected with the input end of the inverter and the input end of the second charge pump unit; the first delay inverting latch circuit comprises a first latch enabling end, and the second delay inverting latch circuit comprises a second latch enabling end; the first latch enabling end is connected with the first latch enabling end and used as an input end of the oscillator unit and used for receiving an enabling signal; the output end of the first charge pump unit is connected with the output end of the second charge pump unit and is used as a charge pump voltage output end. In the embodiment of the invention, two paths of clock signals without burrs of the oscillator unit are respectively input into the first charge pump unit and the second charge pump unit, the first charge pump unit and the second charge pump unit can work under different clock phases of the same oscillator unit, when any path of clock signals of the oscillator unit are inverted, the charging operation can be quickly responded and carried out through the first charge pump unit and the second charge pump unit, the response speed is very high, and the overshoot phenomenon can be avoided because the clock signals are free of burrs.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a prior art charge pump system;
FIG. 2 is a schematic diagram of a charge pump system according to an embodiment of the present invention;
fig. 3 is a timing diagram of a charge pump system according to an embodiment of the present invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
Referring to fig. 2, there is shown a charge pump system, comprising in particular: an oscillator unit 10, a first charge pump unit 20, a second charge pump unit 30.
Wherein the oscillator unit 10 includes: a first delayed inversion latch circuit 101, a second delayed inversion latch circuit 102, and an inverter 103; wherein, the output end of the first delay inverting latch circuit 101 is connected with the input end of the second delay inverting latch circuit 102 and the input end of the first charge pump unit 20; the output end of the second delay inverting latch circuit 102 is connected with the input end of the inverter 103 and the input end of the second charge pump unit 30; the first delayed inverting latch circuit 101 includes a first latch enable terminal, and the second delayed inverting latch circuit 102 includes a second latch enable terminal; the first latch enabling end is connected with the first latch enabling end and used as an input end of the oscillator unit and used for receiving an enabling signal; the output terminal of the first charge pump unit 20 is connected to the output terminal of the second charge pump unit 30 as a charge pump voltage output terminal.
In the embodiment of the present invention, the first delayed inverting latch circuit 101 is used for generating and outputting a first clock signal Q1 without glitch; the second delay inverting latch circuit 102 is configured to generate and output a second clock signal Q2 without glitches; the inverter 103 is configured to invert and output the second clock signal.
In the embodiment of the present invention, when the charge pump system works, the enable signal EN is 1, the first delay inverting latch circuit 101 and the second delay inverting latch circuit 102 are in a normal conduction state, the first charge pump unit 20 charges on the rising edge and the falling edge of Q1, and the second charge pump unit 30 charges on the rising edge and the falling edge of Q2; when the voltage at the voltage output end of the charge pump reaches the target voltage value, EN is pulled down to 0, the first delay inverting latch circuit 101 can lock the state of Q1 in the state before EN is pulled down, the second delay inverting latch circuit 102 can lock the state of Q2 in the state before EN is pulled down, and the first charge pump unit 20 and the second charge pump unit 30 can not be charged again after EN is pulled down, so that overshoot is avoided.
As a specific application example, as shown in fig. 2, the charge pump unit of the present invention further includes: a comparison unit 40, a first resistor 50, a second resistor 40; the comparing unit 40 comprises a first input interface 401, a second input interface 402, a first output interface 403; the first input interface 401 is used for accessing a reference voltage; the first output interface 401 is connected to an input of the oscillator unit 10; one end of the first resistor 50 is connected with the voltage output end of the charge pump; the other end of the first resistor 50 is connected to one end of the second resistor 60 and the second input interface 402; the other end of the second resistor 60 is grounded.
The first delayed inversion latch circuit 101 includes: a first delay inverter 1011, a second delay inverter 1012, and a first latch 1013; wherein the first latch 1013 includes the first latch enable terminal; the input end of the first delay inverter 1011 is the input end of the first delay inverter circuit 101; an output end of the first delay inverter 1011 is connected with an input end of the second delay inverter 1012; an output of the second delay inverter 1012 is connected to an input of the first latch 1013; the output of the first latch 1013 is the output of the first delay inverter circuit 101. The second delayed inverting latch circuit 102 includes: a third delay inverter 1021, a fourth delay inverter 1022, and a second latch 1023; wherein the second latch 1023 includes the second latch enable terminal; the input end of the third delay inverter 1021 is the input end of the second delay inverter circuit 102; the output end of the third delay inverter 1021 is connected with the input end of the fourth delay inverter 1022; the output end of the fourth delay inverter 1022 is connected to the input end of the second latch 1023; the output of the second latch 1023 is the output of the second delay inverter circuit 102.
In the embodiment of the present invention, through the above connection relationship between the first delay inverter 1011 and the second delay inverter 1012, the oscillation signals D1, D1 may be generated, and the first clock signal Q1 may be obtained after the oscillation signals D1 are processed by the first latch 1013; by the above connection relationship between the third delay inverter 1021 and the third delay inverter 1022, the oscillation signals D2 and D2 can be generated, and the second clock signal Q2 can be obtained after being processed by the second latch 1023.
In the embodiment of the present invention, the first resistor 50 and the second resistor 60 form a voltage sampling circuit, VFB is a feedback voltage, VREF is a reference voltage, specific reference of the reference voltage can be set according to an actual application scenario, cmp is the comparator 40, when VFB is smaller than VREF, cmp output signal EN is 1, the first latch 1013 is in a normal conduction state, D1 can be directly transferred to Q1, the second latch 1023 is in a normal conduction state, and D2 can be directly transferred to Q2; with rising edges and falling edges of Q1 and Q2, the first charge pump unit 20 and the second charge pump unit 30 charge the charge pump voltage output terminal, and the output voltage VP of the charge pump voltage output terminal is continuously flushable by the first charge pump unit 20 and the second charge pump unit 30, and accordingly, VFB increases with increasing VP, and when VFB is greater than VREF, the cmp output signal EN is 0. After EN falling edge arrives, EN is 0, the first latch 1013 is in a latch state, which can latch Q1 in the state of Q1 before EN falling edge arrives, and the second latch 1023 is in a latch state, which can latch Q2 in the state of Q2 before EN falling edge arrives, so that Q1 and Q2 are clock signals without glitches.
In a specific application, when EN falls, Q1 and Q2 may be locked in four positions (case 1, case2, case3, case 4) as shown in fig. 3. Four positions: case1 represents q1=1 and q2=1; case2 represents q1=0 and q2=1; case3 represents q1=0 and q2=0; case4 represents q1=1 and q2=0.
Under four conditions (case 1, case2, case3, case 4), Q1 and Q2 after locking correspond to the unique D1 and D2 combination values, and the values of D1 and D2 corresponding to the four cases are given in reference to Table 1:
| case1 | case2 | case3 | case4 | |
| Q1 | 1 | 0 | 0 | 1 |
| Q2 | 1 | 1 | 0 | 0 |
| D1 | 0 | 0 | 1 | 1 |
| D2 | 1 | 0 | 0 | 1 |
TABLE 1
When the oscillator unit 10 is operated again, i.e., EN changes from 0 to 1, D1 is transmitted to Q1 and D2 is transmitted to Q2, it can be seen from table 1 that in any one of cases 1, case2, case3, case4, only one of D1 and D2 corresponding to Q1 and Q2 is inverted, so that only one of Q1 and Q2 is inverted at the first time and then the two phases are alternately operated, so that the first charge pump unit 20 and the second charge pump unit 30 can respond excessively in time and respond only to one phase, not to respond, and thus the performance of the burr, overshoot, and response speed of the charge pump system can be optimized.
In a specific application, the delay inverter may be a circuit or an integrated chip with a delay inverting function built by using a field effect transistor, a transistor, etc., and the comparing unit may be a comparator.
Embodiments of the present invention may also provide a nonvolatile memory including any of the above charge pump systems.
It should be noted that, for simplicity of description, each embodiment is described as a series of circuit combinations, but those skilled in the art should appreciate that embodiments of the present invention are not limited by the description. Further, it should be understood by those skilled in the art that the embodiments described in the specification are all preferred embodiments, and the circuit connections referred to are not necessarily required in the embodiments of the present invention.
The invention has been illustrated and described in detail in the drawings and in the preferred embodiments, but the invention is not limited to these disclosed embodiments and other solutions derived therefrom by a person skilled in the art are also within the scope of the invention.
It should be noted that modifications and adaptations to the invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has outlined a charge pump system and a nonvolatile memory in accordance with the present invention in detail, and the detailed description of the principles and embodiments of the invention have been provided herein with the application of the specific examples, the above examples being provided to facilitate the understanding of the invention and its core concepts; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (6)
1. A charge pump system, the system comprising:
an oscillator unit, a first charge pump unit, a second charge pump unit;
the oscillator unit includes: the first delay inverting latch circuit, the second delay inverting latch circuit and the inverter; the first delayed inverting latch circuit includes: a first delay inverter, a second delay inverter, and a first latch; the second delayed inverting latch circuit includes: a third delay inverter, a fourth delay inverter, and a second latch;
the first delay inverting latch circuit is used for generating and outputting a first clock signal without burrs; the second delay inverting latch circuit is used for generating and outputting a second clock signal without burrs; the inverter is used for outputting the second clock signal in an inverted mode;
the output end of the first delay inverting latch circuit is connected with the input end of the second delay inverting latch circuit and the input end of the first charge pump unit;
the output end of the second delay inverting latch circuit is connected with the input end of the inverter and the input end of the second charge pump unit;
the first delay inverting latch circuit comprises a first latch enabling end, and the second delay inverting latch circuit comprises a second latch enabling end;
the first latch enabling end is connected with the first latch enabling end and used as an input end of the oscillator unit and used for receiving an enabling signal;
the output end of the first charge pump unit is connected with the output end of the second charge pump unit and is used as a charge pump voltage output end.
2. The system of claim 1, further comprising:
the comparison unit, the first resistor and the second resistor;
the comparison unit comprises a first input interface, a second input interface and a first output interface; the first input interface is used for accessing reference voltage;
the first output interface is connected with the input end of the oscillator unit;
one end of the first resistor is connected with the voltage output end of the charge pump;
the other end of the first resistor is connected with one end of the second resistor and the second input interface;
the other end of the second resistor is grounded.
3. The system of claim 1, wherein the first latch comprises the first latch enable terminal;
the input end of the first delay inverter is the input end of the first delay inverting latch circuit;
the output end of the first delay inverter is connected with the input end of the second delay inverter;
the output end of the second delay inverter is connected with the input end of the first latch;
the output end of the first latch is the output end of the first delay inverting latch circuit.
4. The system of claim 3, wherein the second latch comprises the second latch enable terminal;
the input end of the third delay inverter is the input end of the second delay inverting latch circuit;
the output end of the third delay inverter is connected with the input end of the fourth delay inverter;
the output end of the fourth delay inverter is connected with the input end of the second latch;
the output end of the second latch is the output end of the second delay inverting latch circuit.
5. The system of claim 2, wherein the comparison unit is a comparator.
6. A nonvolatile memory comprising the charge pump system of any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811109494.1A CN110943737B (en) | 2018-09-21 | 2018-09-21 | Charge pump system and nonvolatile memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811109494.1A CN110943737B (en) | 2018-09-21 | 2018-09-21 | Charge pump system and nonvolatile memory |
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| CN110943737A CN110943737A (en) | 2020-03-31 |
| CN110943737B true CN110943737B (en) | 2024-04-05 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11298302A (en) * | 1998-04-13 | 1999-10-29 | Hitachi Ltd | Frequency variable oscillation circuit, phase synchronous circuit using the same and clock synchronous circuit |
| US7279959B1 (en) * | 2006-05-26 | 2007-10-09 | Freescale Semiconductor, Inc. | Charge pump system with reduced ripple and method therefor |
| CN104854698A (en) * | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | Dram-type device with low variation transistor peripheral circuits, and related methods |
| CN107370474A (en) * | 2017-06-12 | 2017-11-21 | 合肥格易集成电路有限公司 | A kind of pierce circuit and nonvolatile memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI329991B (en) * | 2006-09-21 | 2010-09-01 | Etron Technology Inc | A charge pump control system and a ring oscillator |
-
2018
- 2018-09-21 CN CN201811109494.1A patent/CN110943737B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11298302A (en) * | 1998-04-13 | 1999-10-29 | Hitachi Ltd | Frequency variable oscillation circuit, phase synchronous circuit using the same and clock synchronous circuit |
| US7279959B1 (en) * | 2006-05-26 | 2007-10-09 | Freescale Semiconductor, Inc. | Charge pump system with reduced ripple and method therefor |
| CN104854698A (en) * | 2012-10-31 | 2015-08-19 | 三重富士通半导体有限责任公司 | Dram-type device with low variation transistor peripheral circuits, and related methods |
| CN107370474A (en) * | 2017-06-12 | 2017-11-21 | 合肥格易集成电路有限公司 | A kind of pierce circuit and nonvolatile memory |
Non-Patent Citations (1)
| Title |
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| 谢明璞 ; 武杰 ; 张杰 ; .利用FPGA延时链实现鉴相器时钟数据恢复.核技术.2009,(06),全文. * |
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