CN110943610A - Charge pump system and nonvolatile memory - Google Patents
Charge pump system and nonvolatile memory Download PDFInfo
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- CN110943610A CN110943610A CN201811109664.6A CN201811109664A CN110943610A CN 110943610 A CN110943610 A CN 110943610A CN 201811109664 A CN201811109664 A CN 201811109664A CN 110943610 A CN110943610 A CN 110943610A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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Abstract
The embodiment of the invention provides a charge pump system and a nonvolatile memory, wherein the system comprises: the circuit comprises a comparison unit, an oscillator unit, a latch unit, a charge pump unit, a first resistor and a second resistor; the comparison unit comprises a first input interface, a second input interface and a first output interface; the first input interface is used for accessing a reference voltage; the first output interface is connected with the input end of the oscillator unit and the enabling end of the latch unit; the output end of the oscillator unit is connected with the input end of the latch unit; the output end of the latch unit is connected with the input end of the charge pump unit. In the embodiment of the invention, the output end of the oscillator unit is provided with the latch unit, and when the output end of the comparison unit is pulled down, the latch unit can latch the clock signal in a state before the falling edge of the output end of the comparison unit appears, so that the burr in the charge pump system can be effectively avoided, and the error of the internal node of the charge pump unit is avoided.
Description
Technical Field
The present invention relates to the field of charge pumps, and more particularly, to a charge pump system and a nonvolatile memory.
Background
In a charge pump system, a charge pump unit typically outputs a current to charge a load on a rising or falling edge of a clock.
In the conventional charge pump system, as shown in fig. 1, EN is an enable signal, and when EN is 1 in general, the charge pump system is operated, and when an output clock signal CK0 and EN is 0, the charge pump system is turned off.
However, the inventor finds that the above technical solution has the following defects in the process of researching the above technical solution: when the prior art charge pump system is turned off, glitches often occur at the falling edge of EN, causing the charge pump cell internal nodes to fail.
Disclosure of Invention
In view of the above problems, a charge pump system according to an embodiment of the present invention is provided to eliminate glitches in the charge pump system.
According to a first aspect of the present invention, there is provided a charge pump system comprising:
the circuit comprises a comparison unit, an oscillator unit, a latch unit, a charge pump unit, a first resistor and a second resistor;
the comparison unit comprises a first input interface, a second input interface and a first output interface; the first input interface is used for accessing a reference voltage;
the first output interface is connected with the input end of the oscillator unit and the enabling end of the latch unit;
the output end of the oscillator unit is connected with the input end of the latch unit;
the output end of the latch unit is connected with the input end of the charge pump unit;
one end of the first resistor is connected with the output end of the charge pump unit, and the other end of the first resistor is connected with the output end of the charge pump unit and then serves as a clock signal output end;
the other end of the first resistor is connected with one end of the second resistor and the second input interface;
the other end of the second resistor is grounded.
According to a second aspect of the invention, there is provided a non-volatile memory comprising a charge pump system as any of the above.
The charge pump system in the embodiment of the invention comprises a comparison unit, an oscillator unit, a latch unit, a charge pump unit, a first resistor and a second resistor; the comparison unit comprises a first input interface, a second input interface and a first output interface; the first input interface is used for accessing a reference voltage; the first output interface is connected with the input end of the oscillator unit and the enabling end of the latch unit; the output end of the oscillator unit is connected with the input end of the latch unit; the output end of the latch unit is connected with the input end of the charge pump unit; one end of the first resistor is connected with the output end of the charge pump unit, and the one end of the first resistor is connected with the output end of the charge pump unit and then used as a clock signal output end; the other end of the first resistor is connected with one end of the second resistor and the second input interface; the other end of the second resistor is grounded. In the embodiment of the invention, the output end of the oscillator unit is provided with the latch unit, and when the output end of the comparison unit is pulled down, the latch unit can latch the clock signal in a state before the falling edge of the output end of the comparison unit appears, so that the burr in the charge pump system can be effectively avoided, and the error of the internal node of the charge pump unit is avoided.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a prior art charge pump system;
FIG. 2 illustrates a charge pump system according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating the output signals of a clock unit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of the output signals of a clock unit of the charge pump system according to the present invention;
FIG. 5 is a timing diagram of an output signal of another clock unit of the charge pump system according to the embodiment of the present invention;
FIG. 6 is another charge pump system provided by an embodiment of the present invention;
fig. 7 is a delay inverting circuit of a charge pump system according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 2, there is shown a charge pump system, comprising in particular:
the circuit comprises a comparison unit 10, an oscillator unit 20, a latch unit 30, a charge pump unit 40, a first resistor 50 and a second resistor 60; the comparison unit 10 comprises a first input interface 101, a second input interface 102 and a first output interface 103; the first input interface 101 is used for accessing a reference voltage; the first output interface 103 is connected to the input terminal of the oscillator unit 20 and the enable terminal 301 of the latch unit 30; the output end of the oscillator unit 20 is connected with the input end of the latch unit 30; the output end of the latch unit 30 is connected with the input end of the charge pump unit 40; one end of the first resistor 50 is connected to the output end of the charge pump unit 40, and one end of the first resistor 50 is connected to the output end of the charge pump unit 40 and then serves as a clock signal output end; the other end of the first resistor 50 is connected to one end of the second resistor 60 and the second input interface 102; the other end of the second resistor 60 is grounded.
In the embodiment of the present invention, as shown in fig. 2, the first resistor 50 and the second resistor 60 form a voltage sampling circuit, VFB is a feedback voltage, VREF is a reference voltage, cmp is the comparator 10, when VFB is smaller than VREF, a cmp output signal EN is 1, the oscillator unit 20(osc) operates to output a clock signal CK, a signal at an input terminal of the latch unit 20(latch) can be transmitted to an output terminal of the latch unit (latch), CK can be transmitted to an input terminal of the charge pump unit 40(pump), an output voltage VP of the pump is continuously boosted by the pump as rising and falling edges of the output clock signal CK of the osc arrive, and accordingly, VFB also rises as VP rises, and when VFB is larger than VREF, the cmp output signal EN is 0. After the EN falling edge arrives, EN is 0, and the latch is in a latch state, so that the signal CK1 at the output end of the latch is latched in a state before the clock signal CK occurs at the EN falling edge, and the CK1 is prevented from generating glitch.
It can be understood that if the latch unit 30 is not provided in the charge pump system, there is a high possibility that a timing diagram of CK shown in fig. 3 may appear when an EN falling edge arrives, when CK is high, the voltage CK at the pump output end has already hit a target value, and since CK is pulled low when the EN falling edge arrives, a clock glitch occurs, the clock glitch has one more falling edge, and for some pump structures, the glitch may cause an error in the internal node of the pump, resulting in slow or failed next start-up.
In the charge pump system provided with the latch unit 30 according to the embodiment of the present invention, the clock signal of CK may be specifically shown in fig. 4 and 5. Specifically, fig. 4 shows the timing sequence when CK is 0 at the time of EN falling edge, and it can be seen that CK does not generate glitch; fig. 5 shows the timing sequence when CK is 1 when EN falls, and it can be seen that no glitch occurs in CK due to the arrangement of the latch unit 30, so that no overshoot or node fault occurs in the charge pump system.
In a specific application, the comparison unit 10 may be an integrated comparator, so that the circuit is simple to build and has stable performance.
In summary, in the charge pump system according to the embodiment of the invention, the latch unit 30 is disposed, so that glitches in the charge pump system can be effectively avoided, and errors in internal nodes of the charge pump unit can be avoided.
As a preferable solution of the embodiment of the present invention, as shown in fig. 6, the charge pump system further includes: a timing delay unit 70; the first output interface 103 is connected to the input end of the oscillator unit through the timing delay unit 70.
In the embodiment of the invention, the time sequence Delay unit (Delay unit) can be used for ensuring that the time sequence of the latch is enough, and further enhancing the reliability of the burr reducing function.
As a preferable aspect of the embodiment of the present invention, as shown in fig. 7, the oscillator unit 20 includes: a delay inverting circuit 11, a NAND gate circuit 12 and a NOT gate circuit 13; the delay inverting circuit 11 comprises a first input end 111 and a first output end 112; the nand gate circuit 12 comprises a second input terminal 121, a third input terminal 122 and a second output terminal 123; the first output terminal 112 is connected to the second input terminal 121; the second output terminal 123 is connected to an input terminal of the not-gate circuit 13; the output end of the not gate circuit 13 is used as the output end of the oscillator unit 20; the first input end 111 and the third input end 122 are connected to the first output interface 103.
In the embodiment of the present invention, when EN is 1 in the oscillation unit 20, the delay inverting circuit 11 may generate an oscillation signal, and output the clock signal CK through the nand gate circuit 12 and the not gate circuit 13.
In a specific application, as shown in fig. 7, the delay inverting circuit 11 includes:
p type field effect transistor: p0, P1, P2, P3, P4, P5, P6, P7, P8;
n-type field effect transistor: n0, N1, N2, N3, N4, N5, N6, N7, N8, N11, N12;
the source end of the P0, the source end of the P1, the source end of the P3, the source end of the P5 and the source end of the P7 are connected with a power supply VDD; the gate terminal of the P0, the gate terminal of the P1, the gate terminal of the P3, the gate terminal of the P5 and the gate terminal of the P7 are connected; the gate end of the P0 is connected with the drain end of the P0; the drain terminal of the P1 is connected with the source terminal of the P2; the drain terminal of the P3 is connected with the source terminal of the P4; the drain terminal of the P5 is connected with the source terminal of the P6; the drain terminal of the P7 is connected with the source terminal of the P8; the gate terminal of the P2 is connected with the gate terminal of the N1, and the second output terminal is connected; the drain terminal of P2, the drain terminal of N1, the gate terminal of P4 and the gate terminal of N3 are connected; the drain terminal of the P4, the drain terminal of the N3, the gate terminal of the P6 and the gate terminal of the N5 are connected; the drain terminal of the P6, the drain terminal of the N5, the gate terminal of the P8 and the gate terminal of the N7 are connected; the drain terminal of the P8 and the drain terminal of the N7 are connected with the first output terminal; the drain terminal of the N2 is connected with the source terminal of the N1; the drain terminal of the N4 is connected with the source terminal of the N3; the drain terminal of the N6 is connected with the source terminal of the N5; the drain terminal of the N8 is connected with the source terminal of the N7; the source end of the N2, the source end of the N4, the source end of the N6, the source end of the N8, the source end of the N11, and the source end of the N12 are connected to a ground end GND; the gate terminal of the N2, the gate terminal of the N4, the gate terminal of the N6, the gate terminal of the N8, the gate terminal of the N11 and the gate terminal of the N12 are connected; the gate end of the N11 is connected with the drain end of the N11; the drain terminal of the N12 is connected with the drain terminal of the P0; the drain terminal of the N11 is connected with the source terminal of the N0; the drain terminal of the N0 is used as a bias current access terminal and is used for receiving bias current; and the grid end of the N0 is connected with the first output interface.
In specific application, the field effect transistor units (including the P-type field effect transistor unit and the N-type field effect transistor unit) can be single MOS transistors, so that the circuit is simple to build and low in cost; the field effect transistor unit of the embodiment of the invention can also be built by a plurality of MOS transistors, and has a source end, a gate end and a drain end, for example, a structure that a plurality of MOS transistors are connected in parallel is used, and under the condition that a plurality of MOS transistors are connected in parallel, the source end, the gate end and the drain end of each MOS transistor are respectively connected, so that a larger current is provided for a circuit in a parallel connection mode. The embodiment of the present invention is not particularly limited to this.
The connection of the delay inverting circuit 11 generates an oscillation signal, and outputs a clock signal CK via the nand gate circuit 12 and the not gate circuit 13.
Embodiments of the present invention can also provide a nonvolatile memory, including any of the charge pump systems described above.
It should be noted that, for simplicity of description, the embodiments are described as a series of circuit combinations, but those skilled in the art should understand that the embodiments of the present invention are not limited by the description. Furthermore, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the circuit connections involved are not necessarily required for embodiments of the invention.
While the invention has been illustrated and described in detail in the drawings and foregoing description with reference to preferred embodiments, the invention is not limited to the embodiments disclosed, and other arrangements derived therefrom by those skilled in the art are within the scope of the invention.
It should be noted that modifications and adaptations may occur to those skilled in the art without departing from the principles of the present invention and should be considered within the scope of the present invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The present invention provides a charge pump system and a non-volatile memory, which are described in detail above, and the principle and the implementation of the present invention are explained herein by using specific examples, and the description of the above examples is only used to help understanding the present invention and its core idea; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (6)
1. A charge pump system, the system comprising:
the circuit comprises a comparison unit, an oscillator unit, a latch unit, a charge pump unit, a first resistor and a second resistor;
the comparison unit comprises a first input interface, a second input interface and a first output interface; the first input interface is used for accessing a reference voltage;
the first output interface is connected with the input end of the oscillator unit and the enabling end of the latch unit;
the output end of the oscillator unit is connected with the input end of the latch unit;
the output end of the latch unit is connected with the input end of the charge pump unit;
one end of the first resistor is connected with the output end of the charge pump unit, and the other end of the first resistor is connected with the output end of the charge pump unit and then serves as a clock signal output end;
the other end of the first resistor is connected with one end of the second resistor and the second input interface;
the other end of the second resistor is grounded.
2. The system of claim 1, further comprising: a time delay unit;
the first output interface is connected with the input end of the oscillator unit through the time sequence delay unit.
3. The system according to claim 1 or 2, wherein the oscillator unit comprises: a time-delay inverting circuit, a NAND gate circuit and a NOT gate circuit;
the delay inverting circuit comprises a first input end and a first output end;
the NAND gate circuit comprises a second input end, a third input end and a second output end;
the first output end is connected with the second input end;
the second output end is connected with the input end of the NOT gate circuit;
the output end of the NOT gate circuit is used as the output end of the oscillator unit;
the first input end and the third input end are connected with the first output interface.
4. The system of claim 3, wherein the time-delayed inverting circuit comprises:
p type field effect transistor: p0, P1, P2, P3, P4, P5, P6, P7, P8;
n-type field effect transistor: n0, N1, N2, N3, N4, N5, N6, N7, N8, N11, N12;
the source end of the P0, the source end of the P1, the source end of the P3, the source end of the P5 and the source end of the P7 are connected with a power supply VDD;
the gate terminal of the P0, the gate terminal of the P1, the gate terminal of the P3, the gate terminal of the P5 and the gate terminal of the P7 are connected; the gate end of the P0 is connected with the drain end of the P0;
the drain terminal of the P1 is connected with the source terminal of the P2;
the drain terminal of the P3 is connected with the source terminal of the P4;
the drain terminal of the P5 is connected with the source terminal of the P6;
the drain terminal of the P7 is connected with the source terminal of the P8;
the gate terminal of the P2 is connected with the gate terminal of the N1, and the second output terminal is connected;
the drain terminal of the P2, the drain terminal of the N1, the gate terminal of the P4 and the gate terminal of the N3 are connected;
the drain terminal of the P4, the drain terminal of the N3, the gate terminal of the P6 and the gate terminal of the N5 are connected;
the drain terminal of the P6, the drain terminal of the N5, the gate terminal of the P8 and the gate terminal of the N7 are connected;
the drain terminal of the P8 and the drain terminal of the N7 are connected with the first output terminal;
the drain terminal of the N2 is connected with the source terminal of the N1;
the drain terminal of the N4 is connected with the source terminal of the N3;
the drain terminal of the N6 is connected with the source terminal of the N5;
the drain terminal of the N8 is connected with the source terminal of the N7;
the source end of the N2, the source end of the N4, the source end of the N6, the source end of the N8, the source end of the N11, and the source end of the N12 are connected to a ground end GND;
the gate terminal of the N2, the gate terminal of the N4, the gate terminal of the N6, the gate terminal of the N8, the gate terminal of the N11 and the gate terminal of the N12 are connected; the gate end of the N11 is connected with the drain end of the N11;
the drain terminal of the N12 is connected with the drain terminal of the P0;
the drain terminal of the N11 is connected with the source terminal of the N0;
the drain terminal of the N0 is used as a bias current access terminal and is used for receiving bias current;
and the grid end of the N0 is connected with the first output interface.
5. The system of claim 1, wherein the comparison unit is a comparator.
6. A non-volatile memory comprising the charge pump system of any of claims 1-5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811109664.6A CN110943610B (en) | 2018-09-21 | 2018-09-21 | Charge pump system and nonvolatile memory |
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| CN201811109664.6A CN110943610B (en) | 2018-09-21 | 2018-09-21 | Charge pump system and nonvolatile memory |
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| CN114257084A (en) * | 2021-12-24 | 2022-03-29 | 恒烁半导体(合肥)股份有限公司 | Charge pump circuit with quick start function and application thereof |
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| CN110943610B (en) | 2021-04-02 |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |
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