CN110941938B - Circuit area and power consumption optimization method based on NAND/NOR-AND exclusive OR non-graph - Google Patents
Circuit area and power consumption optimization method based on NAND/NOR-AND exclusive OR non-graph Download PDFInfo
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Abstract
The invention discloses a circuit area and power consumption optimization method based on NAND/NOR/XNOR graph, which comprises the steps of firstly converting an integrated circuit to be processed into an AIG, defining an exclusive-OR structure in the AIG as a basic exclusive-OR structure, a single-node shared exclusive-OR structure and a double-sub-node shared exclusive-OR structure, replacing the basic exclusive-OR structure and the single-sub-node shared exclusive-OR structure by exclusive-OR nodes, so as to convert the AIG into an AXIG, obtaining the AXIG of the integrated circuit to be processed, finally converting the AXIG of the integrated circuit to be processed to obtain NAXIG, mapping the NAXIG into a circuit, and outputting the circuit after the NAXIG is the optimized circuit; the integrated circuit has the advantages of being capable of optimizing the area and the power consumption simultaneously, and good in optimizing effect, and enabling the integrated circuit to have higher comprehensive performance.
Description
Technical Field
The invention relates to a circuit area and power consumption optimization method, in particular to a circuit area and power consumption optimization method based on NAND/NOR-AND exclusive OR non-graph.
Background
As the scale of integrated circuits increases and the operating frequency increases, the area and power consumption of integrated circuits also increases rapidly. Optimization of integrated circuit area and power consumption is a critical issue to be addressed in integrated circuit design.
In recent years, integrated circuit area optimization problems have been widely studied, such as two-stage AND multi-stage circuit area optimization for AND/OR structures based on conventional boolean logic (Traditional Boolean, TBL), area optimization for simplest AND disjoint product term reduction logic function implementation based on Reed-Muller logic, processing of exclusive OR intensive functions based on binary decision diagrams to optimize circuit area, reduction of diagram nodes based on nand diagram (And Inverter Graph, AIG) rewrite algorithms to reduce circuit gate structures to achieve circuit area optimization, AND so forth. Most of these area optimization methods described above have been integrated into EDA tools (e.g., espresso, MIS, ABC, etc.). However, as the scale of integrated circuit designs continues to expand, EDA tools also face various challenges, such as dealing with ever-increasing functional complexity issues, and many of these existing area optimization approaches remain inadequate. Thus, the functional representation of an integrated circuit directly affects the degree of optimization of the integrated circuit area when the EDA tool performs integrated circuit logic synthesis and optimization.
When the performance of an integrated circuit is optimized, the logic function of the integrated circuit mainly has two expression structures: graphical structures and non-graphical structures. Compared with a non-graph structure, the graph structure adopts nodes to represent logic gates, adopts solid line edges to represent input or output, adopts dotted line edges to represent inverters, adopts nodes which represent the original input of the integrated circuit as original input nodes, and adopts other nodes as internal nodes. The graph structure indicates that the logic function can effectively reduce the memory, has simple structure and has good mapping relation with the circuit process. Therefore, integrated circuit optimization techniques based on graphic structures are receiving extensive attention from researchers. The conventional graph structure is a directed acyclic graph (Directed Acyclic Graph, DAG) structure. AIG is one of the most widely used directed acyclic graph structures. The logic gates represented by the nodes in the AIG are AND gates, each AND gate node is provided with an input side and an output side, the number of the input sides is two, and the number of the output sides is one or more. Which represents a more compact form of integrated circuit and can greatly reduce memory space. Some optimization algorithms that represent integrated circuits using AIG have been integrated into a well-known logic synthesis tool ABC in the academy. However, the limitations of the AIG architecture itself, i.e., the inclusion of only and gate nodes and inverters, make it necessary to have a large number of and gate nodes to construct other logic gate structures when representing more complex integrated circuits containing multiple logic, such that circuit area optimization is limited.
Currently, to further optimize integrated circuits, the improved architecture of AIG is endless, with exclusive OR and NAND (XOR-And Inverter Graph, XAIG) stand out. Exclusive or nand graph is formulated
For the sake of the description, an exclusive or gate structure in the AIG is represented by an exclusive or node, so that the graph structure is simplified, where a and b represent two inputs of an and gate node in the AIG, and f is an output of the and gate node. As shown in fig. 1, the exclusive or gate structure replaced by exclusive or nodes is composed of three and gate nodes, which are formedAmong three AND gate nodes of the exclusive OR gate structure, one AND gate node is taken as a root node, the output edge of the root node outputs f, the other two AND gate nodes are taken as left and right child nodes, two input edges of the two child nodes are input a and b, one input edge of each child node is a solid line edge, the other input edge is a broken line edge, the two child nodes respectively have only one output edge, namely, the two child nodes are not shared by other nodes, and the output edges of the two child nodes are taken as the two input edges of the root node. Although the XAIG is simpler in form than the AIG, it can replace only one type of the xor gate structure in the AIG structure, and the possible xor gate structure is not complete, and the area optimization effect needs to be improved. Furthermore, the current methods of optimizing power consumption for integrated circuits are not very much. And the area optimization and the power consumption optimization are independently carried out, so that the integrated circuit is not high in comprehensive performance.
Disclosure of Invention
The invention aims to solve the technical problem of providing a circuit area and power consumption optimization method based on NAND/NOR/XNOR graphs, which can simultaneously realize the optimization of area and power consumption, has good optimization effect and can lead an integrated circuit to have higher comprehensive performance when applied to the integrated circuit.
The technical scheme adopted for solving the technical problems is as follows: a circuit area and power consumption optimization method based on NAND/NOR-AND/XOR-NOT-AND comprises the following steps:
step 1: the integrated circuit to be processed is represented by a graphic structure: converting the integrated circuit to be processed into AIG;
step 2: defining an exclusive or structure in AIG, specifically: defining an exclusive-or structure in which two child nodes are not shared by other nodes as a basic exclusive-or structure, defining an exclusive-or structure in which only one child node of the two child nodes is shared by other nodes as a single-node shared exclusive-or structure, and defining an exclusive-or structure in which both child nodes are shared by other nodes as a double-child node shared exclusive-or structure;
step 3: converting AIG into AXIG to obtain AXIG of the integrated circuit to be processed, wherein the specific conversion process is as follows:
3-1, determining a basic exclusive-or structure, a single-node shared exclusive-or structure and a double-child node shared exclusive-or structure existing in the AIG;
3-2, replacing three AND gate nodes of each basic exclusive-or structure existing in the AIG by an exclusive-or node, converting an input edge of any child node in the exclusive-or structure, which is a broken line edge, into a solid line edge to be used as an input edge of the replaced exclusive-or node, wherein the input edge of the solid line edge is kept unchanged to be used as another input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are both solid line edges, then taking an output edge of a root node in the basic exclusive-or structure as an output edge of the exclusive-or node, and deleting two input edges of the root node and two input edges of another child node in the basic exclusive-or structure; the child nodes shared by other nodes in each single-node shared exclusive-or structure existing in the AIG and input edges and output edges of the child nodes are kept unchanged, the root node and the child nodes which are not shared by other nodes are replaced by one exclusive-or node, the input edge of the child node shared by other nodes in each single-node shared exclusive-or structure, which is a broken line edge, is converted into one input edge of the replaced exclusive-or node, the input edge of the child node which is not shared by other nodes, which is a solid line edge, is kept unchanged and is used as the other input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are solid line edges, two input edges of the root node in the basic exclusive-or structure are deleted, and the output edge of the root node in the single-node shared exclusive-or structure is used as the output edge of the exclusive-or node; the double sub-node exclusive or structure remains unchanged.
Step 4: obtaining the type of each node in the AXIG of the integrated circuit to be processed, the input edge and the output edge virtually and practically of each node, and converting the AXIG of the integrated circuit to be processed according to the following rules:
when the node is an AND gate node and the output edge is a solid line edge: if the two input edges are solid line edges, converting the node into a NAND gate node, and converting the two input edges and the output edge into broken line edges; if one input edge is a broken line edge and the other input edge is a solid line edge, converting the node into a NOR gate node at the moment, and keeping the two input edges and the output edge unchanged; if the two input edges are all broken line edges, converting the node into a NOR gate node at the moment, and keeping the two input edges and the output edge unchanged;
when the node is an AND gate node and the output edge is a dashed line edge: if the two input edges are both broken line edges, converting the node into a NOR gate node, converting the output edge into a solid line edge, and keeping the two input edges unchanged; if the two input edges are solid lines, converting the node into a NAND gate node, converting the output edge into a solid line, and keeping the two input edges unchanged; if one input edge is a solid line edge and the other input edge is a broken line edge, converting the node into a NAND gate node, converting the output edge into the solid line edge, and keeping the two input edges unchanged;
the graph obtained by converting AXIG of the integrated circuit to be processed according to the rule is called NAXIG;
step 5: and mapping NAXIG into a circuit and outputting the circuit, wherein the output circuit is the optimized circuit.
Compared with the prior art, the invention has the advantages that the integrated circuit to be processed is converted into the AIG, then the exclusive-or structure in the AIG is defined, the exclusive-or structure in which two child nodes are not shared by other nodes is defined as a basic exclusive-or structure, the exclusive-or structure in which only one child node is shared by other nodes is defined as a single-node shared exclusive-or structure, the exclusive-or structure in which two child nodes are shared by other nodes is defined as a double-child node shared exclusive-or structure, three AND gate nodes of each basic exclusive-or structure existing in the AIG are replaced by one exclusive-or node, the input edge of any child node in the exclusive-or structure which is a broken line edge is converted into one input edge of the replaced exclusive-or node after being a solid line edge, the input edge of the solid line edge is kept unchanged as the other input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are solid edges, the output edge of the root node in the basic exclusive-or structure is taken as the output edge of the exclusive-or node, the two input edges of the root node and the two input edges of the other child nodes in the basic exclusive-or structure are deleted, the child node shared by other nodes in the shared exclusive-or structure of each child node existing in the AIG, the input edges and the output edges thereof are kept unchanged, the child node shared by other nodes in the shared exclusive-or structure of the root node and the child node not shared by other nodes are replaced by one exclusive-or node, the input edge shared by other nodes in the shared exclusive-or structure of each child node is converted into the solid edge serving as one input edge of the replaced exclusive-or node, the input edge shared by other nodes not serving as the solid edge of the other child node is kept unchanged as the other input edge of the replaced exclusive-or node, the method comprises the steps of deleting two input edges of a root node in a basic exclusive-or structure, taking an output edge of the root node in the basic exclusive-or structure as an output edge of the exclusive-or node, keeping the double-sub-node exclusive-or structure unchanged, converting AIG into AXIG, enabling the AXIG obtained after conversion to be equivalent to AIG logic functions, enabling the AXIG structure obtained at the moment to be simpler for AXIG obtained by converting by the existing method, finally further converting AXIG based on node type, input edge and output variable virtual reality, obtaining a final graph NAXIG, and enabling a circuit corresponding to the NAXIG to be an optimized circuit.
Drawings
FIG. 1 is a schematic diagram of an exclusive OR gate structure of an exclusive OR node in an AIG according to the prior art;
FIG. 2 is a schematic diagram of a conversion process of converting a basic exclusive-or structure into exclusive-or nodes in the method of the present invention;
fig. 3 is a schematic diagram of a conversion process of converting a single-node shared xor structure into an xor node in the method of the present invention.
Detailed Description
The invention is described in further detail below with reference to the embodiments of the drawings.
Examples: a circuit area and power consumption optimization method based on NAND/NOR-AND/XOR-NOT-AND comprises the following steps:
step 1: the integrated circuit to be processed is represented by a graphic structure: converting the integrated circuit to be processed into AIG;
step 2: defining an exclusive or structure in AIG, specifically: defining an exclusive-or structure in which two child nodes are not shared by other nodes as a basic exclusive-or structure, defining an exclusive-or structure in which only one child node of the two child nodes is shared by other nodes as a single-node shared exclusive-or structure, and defining an exclusive-or structure in which both child nodes are shared by other nodes as a double-child node shared exclusive-or structure;
step 3: converting AIG into AXIG to obtain AXIG of the integrated circuit to be processed, wherein the specific conversion process is as follows:
3-1, determining a basic exclusive-or structure, a single-node shared exclusive-or structure and a double-child node shared exclusive-or structure existing in the AIG;
3-2, replacing three AND gate nodes of each basic exclusive-or structure existing in the AIG by an exclusive-or node, converting an input edge of any child node in the exclusive-or structure, which is a broken line edge, into a solid line edge to be used as an input edge of the replaced exclusive-or node, wherein the input edge of the solid line edge is kept unchanged to be used as another input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are both solid line edges, then taking an output edge of a root node in the basic exclusive-or structure as an output edge of the exclusive-or node, and deleting two input edges of the root node and two input edges of another child node in the basic exclusive-or structure;a schematic diagram of the conversion process of the basic exclusive-or structure into exclusive-or nodes is shown in fig. 2,
representing AND gate node->
Representing an exclusive or gate node; the child nodes shared by other nodes in each single-node shared exclusive-or structure existing in the AIG and input edges and output edges of the child nodes are kept unchanged, the root node and the child nodes which are not shared by other nodes are replaced by one exclusive-or node, the input edge of the child node shared by other nodes in each single-node shared exclusive-or structure, which is a broken line edge, is converted into one input edge of the replaced exclusive-or node, the input edge of the child node which is not shared by other nodes, which is a solid line edge, is kept unchanged and is used as the other input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are solid line edges, two input edges of the root node in the basic exclusive-or structure are deleted, and the output edge of the root node in the single-node shared exclusive-or structure is used as the output edge of the exclusive-or node; a schematic diagram of a conversion process of converting the single-node shared exclusive OR structure into the exclusive OR node is shown in FIG. 3, wherein +_in FIG. 3>
Representing AND gate node->
Representing an exclusive or gate node; the double sub-node exclusive or structure remains unchanged.
Step 4: obtaining the type of each node in the AXIG of the integrated circuit to be processed, the input edge and the output edge virtually and practically of each node, and converting the AXIG of the integrated circuit to be processed according to the following rules:
when the node is an AND gate node and the output edge is a solid line edge: if the two input edges are solid line edges, converting the node into a NAND gate node, and converting the two input edges and the output edge into broken line edges; if one input edge is a broken line edge and the other input edge is a solid line edge, converting the node into a NOR gate node at the moment, and keeping the two input edges and the output edge unchanged; if the two input edges are all broken line edges, converting the node into a NOR gate node at the moment, and keeping the two input edges and the output edge unchanged;
when the node is an AND gate node and the output edge is a dashed line edge: if the two input edges are both broken line edges, converting the node into a NOR gate node, converting the output edge into a solid line edge, and keeping the two input edges unchanged; if the two input edges are solid lines, converting the node into a NAND gate node, converting the output edge into a solid line, and keeping the two input edges unchanged; if one input edge is a solid line edge and the other input edge is a broken line edge, converting the node into a NAND gate node, converting the output edge into the solid line edge, and keeping the two input edges unchanged;
the graph obtained by converting the AXIG of the integrated circuit to be processed according to the rule is called NAXIG (namely NAND/NOR-AND/XOR not graph);
step 5: and mapping NAXIG into a circuit and outputting the circuit, wherein the output circuit is the optimized circuit.
The NAXIG structure, AIG and AXIG structure obtained by the method are realized by adopting C language under Ubuntu16.04 system, and LGSynth91 standard circuit is selected for testing. Randomly generating the probability of the input signal, wherein the value interval is (0, 1). And according to the different numbers of circuit inputs, the signal probabilities are sequentially selected from left to right. In order to ensure consistency of experimental parameters, before the other two structures are realized, an input circuit is converted into an AIG network in ABC, and an integrated command resyn2 in an ABC tool is called to optimize the AIG network. The signal probabilities are randomly generated and are respectively given to the circuits of the three structural representations, so that the input signal probabilities are kept consistent. Table 1 lists the circuit names and corresponding input/output numbers, the area, switching activity of the AIG, AXIG and NAXIG structures, and finally the improved average of the performance of NAXIG compared to the other two structures.
Statistics show that NAXIG is reduced in area by 45.86% and 36.19% compared with AIG and AXIG, respectively, and switching activity is reduced by 51.51% and 15.88% respectively. NAXIG is significantly better than AIG structure in area and switching activity improvement, with average improvement of more than 40%. NAXIG has an area improvement average of greater than 30% and a switching activity improvement average of greater than 15% as compared to AXIG. The algorithmic temporal complexity of the three structures in Table 1 can be represented by O (|T|log|T|), where T is the total number of gate nodes of any structure. The algorithm run time is not listed because it is not the primary optimization objective herein, and the average time experimentally measured for each algorithm is less than 100 ms.
Table 1 area and switch activity comparison of three structures
From analysis of the data in table 1, most of the circuit area is obviously reduced, and the switching activities of alu2 and apex6 are obviously reduced, so that the method has advantages in circuit area and power consumption optimization, and can effectively optimize the circuit area and the power consumption.
Claims (1)
1. The circuit area and power consumption optimization method based on the NAND/NOR-AND/XOR-NOT graph is characterized by comprising the following steps of:
step 1: the integrated circuit to be processed is represented by a graphic structure: converting the integrated circuit to be processed into AIG;
step 2: defining an exclusive or structure in AIG, specifically: defining an exclusive-or structure in which two child nodes are not shared by other nodes as a basic exclusive-or structure, defining an exclusive-or structure in which only one child node of the two child nodes is shared by other nodes as a single-node shared exclusive-or structure, and defining an exclusive-or structure in which both child nodes are shared by other nodes as a double-child node shared exclusive-or structure;
step 3: converting AIG into AXIG to obtain AXIG of the integrated circuit to be processed, wherein the specific conversion process is as follows:
3-1, determining a basic exclusive-or structure, a single-node shared exclusive-or structure and a double-child node shared exclusive-or structure existing in the AIG;
3-2, replacing three AND gate nodes of each basic exclusive-or structure existing in the AIG by an exclusive-or node, converting an input edge of any child node in the exclusive-or structure, which is a broken line edge, into a solid line edge to be used as an input edge of the replaced exclusive-or node, wherein the input edge of the solid line edge is kept unchanged to be used as another input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are both solid line edges, then taking an output edge of a root node in the basic exclusive-or structure as an output edge of the exclusive-or node, and deleting two input edges of the root node and two input edges of another child node in the basic exclusive-or structure; the child nodes shared by other nodes in each single-node shared exclusive-or structure existing in the AIG and input edges and output edges of the child nodes are kept unchanged, the root node and the child nodes which are not shared by other nodes are replaced by one exclusive-or node, the input edge of the child node shared by other nodes in each single-node shared exclusive-or structure, which is a broken line edge, is converted into one input edge of the replaced exclusive-or node, the input edge of the child node which is not shared by other nodes, which is a solid line edge, is kept unchanged and is used as the other input edge of the replaced exclusive-or node, namely, two input edges of the replaced exclusive-or node are solid line edges, two input edges of the root node in the basic exclusive-or structure are deleted, and the output edge of the root node in the single-node shared exclusive-or structure is used as the output edge of the exclusive-or node; the double-child node type exclusive or structure is kept unchanged;
step 4: obtaining the type of each node in the AXIG of the integrated circuit to be processed, the input edge and the output edge virtually and practically of each node, and converting the AXIG of the integrated circuit to be processed according to the following rules:
when the node is an AND gate node and the output edge is a solid line edge: if the two input edges are solid line edges, converting the node into a NAND gate node, and converting the two input edges and the output edge into broken line edges; if one input edge is a broken line edge and the other input edge is a solid line edge, converting the node into a NOR gate node at the moment, and keeping the two input edges and the output edge unchanged; if the two input edges are all broken line edges, converting the node into a NOR gate node at the moment, and keeping the two input edges and the output edge unchanged;
when the node is an AND gate node and the output edge is a dashed line edge: if the two input edges are both broken line edges, converting the node into a NOR gate node, converting the output edge into a solid line edge, and keeping the two input edges unchanged; if the two input edges are solid lines, converting the node into a NAND gate node, converting the output edge into a solid line, and keeping the two input edges unchanged; if one input edge is a solid line edge and the other input edge is a broken line edge, converting the node into a NAND gate node, converting the output edge into the solid line edge, and keeping the two input edges unchanged;
the graph obtained by converting AXIG of the integrated circuit to be processed according to the rule is called NAXIG;
step 5: and mapping NAXIG into a circuit and outputting the circuit, wherein the output circuit is the optimized circuit.
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Application publication date: 20200331 Assignee: Ningbo Xungao Intelligent Technology Co.,Ltd. Assignor: Wenzhou University Contract record no.: X2024330000002 Denomination of invention: Optimization method for circuit area and power consumption based on AND NOT/OR - AND XOR non graph Granted publication date: 20230502 License type: Common License Record date: 20240103 |