CN110932556B - Phase-shifted full-bridge circuit topology low-voltage output mechanism and low-voltage output method - Google Patents

Phase-shifted full-bridge circuit topology low-voltage output mechanism and low-voltage output method Download PDF

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CN110932556B
CN110932556B CN201911138247.9A CN201911138247A CN110932556B CN 110932556 B CN110932556 B CN 110932556B CN 201911138247 A CN201911138247 A CN 201911138247A CN 110932556 B CN110932556 B CN 110932556B
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electrically connected
diode
phase
mos transistor
capacitor
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CN110932556A (en
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钟钢炜
赵涛
蔡振鸿
唐德平
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Cowell Technology Co.,Ltd.
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Hefei Kewei Power System Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a phase-shifted full-bridge circuit topology low-voltage output mechanism which comprises a transformer T, a phase-shifted full-bridge circuit, a rectifying circuit and an LC (inductance-capacitance) filter circuit, wherein the primary side of the transformer T is connected with the phase-shifted full-bridge circuit, the phase-shifted full-bridge circuit is connected with an external power supply, the secondary side of the transformer T is connected with the rectifying circuit, and the rectifying circuit is connected with the LC filter circuit. The invention also discloses a method for outputting low voltage, wherein an external power supply is connected with the phase-shifted full-bridge circuit for supplying power, and the external power supply is a direct current power supply, and then outputs voltage through the phase-shifted full-bridge circuit, the transformer T, the rectifying circuit and the filter circuit in sequence, so that when energy is transmitted to the secondary side of the transformer T through the transformer T, low voltage can be output even if the output end has insufficient load under the condition of no load or light load.

Description

Phase-shifted full-bridge circuit topology low-voltage output mechanism and low-voltage output method
Technical Field
The invention relates to the field of electronic equipment measurement and test, in particular to a phase-shifted full-bridge circuit topology low-voltage output mechanism and a low-voltage output method.
Background
In the field of electronic technology, a direct current test power supply is one of indispensable test instruments of power electronic enterprises, and because tested devices are various in types and different in functions, the direct current test power supply is required to be capable of providing wide-range output so as to meet various test environments, and a phase-shifted full bridge is a topological structure commonly used by high-frequency direct current test power supplies at present.
The invention patent with the publication number of CN104467434B discloses a transient phase-shifting control method for a double-active full-bridge direct-current converter, belonging to the technical field of power electronics; the method comprises the steps that during a steady state, the alternating current output side of a first full bridge in the double-active full-bridge direct current converter is adjusted to be square wave vh1 with the duty ratio of 50%, and the phase is fixed; the alternating current output side of the second full bridge in the double-active full-bridge direct current converter is also adjusted to be square wave vh2 with the duty ratio of 50%, and an equal phase shift angle is arranged between the rising edge and the falling edge of each of the square waves vh2 and vh 1; during transient, the phase shift angle changes from the phase shift angle D1 of the first switching period T1 to the phase shift angle D2 of the second switching period T2, in the second switching period T2, the phase shift angle between the rising edge (or falling edge) of the square wave vh2 and the rising edge (or falling edge) of the square wave vh1 is D20, and the falling edge (or rising edge) of the square wave vh2 and the falling edge (or rising edge) of the square wave vh1 have the phase shift angle D2. However, in the patent, the full-bridge topology is limited by the development level of the existing semiconductor device, so that when the phase shift angle is shifted to "0", energy of the primary side is still transferred to the secondary side; this characteristic directly results in that the dc test power supply using the phase-shifted full-bridge topology cannot output low voltage when no load or light load.
In the existing direct current test power supply of the phase-shifted full-bridge topology, because of the limitation of the development level of the existing semiconductor device, the direct current test power supply using the phase-shifted full-bridge topology cannot output low voltage when no load or light load; the common solution is to load the load, which greatly reduces the efficiency of the power supply itself, and increases the size and cost of the power supply.
Disclosure of Invention
The invention aims to solve the technical problem that how to solve the problem that the low voltage cannot be output when the phase-shifted full-bridge topology direct-current test power supply is in no-load or light-load.
The invention solves the technical problems through the following technical means:
a phase-shifted full-bridge circuit topology low-voltage output mechanism comprises a transformer T, a phase-shifted full-bridge circuit, a rectifying circuit, an LC (inductance-capacitance) filter circuit and a control module, wherein the primary side of the transformer T is connected with the phase-shifted full-bridge circuit, the phase-shifted full-bridge circuit is connected with an external power supply, the secondary side of the transformer T is connected with the rectifying circuit, and the rectifying circuit is connected with the LC filter circuit;
the phase-shifted full-bridge circuit is also electrically connected with the control module.
The external power supply is connected with the phase-shifted full-bridge circuit for supplying power, the external power supply is a direct-current power supply, the direct-current power supply sequentially passes through the phase-shifted full-bridge circuit, the transformer T, the rectifying circuit and the filtering circuit for outputting, the control driving signal is sent to the phase-shifted full-bridge circuit through the control module, and under the action of the phase-shifted full-bridge circuit, when energy is transmitted to the secondary side of the transformer T through the transformer T, low voltage can be output under the condition of no load or light load.
As a further scheme of the invention: the phase-shift full-bridge circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a MOS tube Q1, a MOS tube Q2, a MOS tube Q3, a MOS tube Q4, a diode D1, a diode D2, a diode D3, a diode D4, an inductor L1, an inductor L2 and a capacitor C2, wherein,
one end of the capacitor C1 is electrically connected with the anode of an external direct-current power supply through a bus Vbus +, the other end of the capacitor C1 is electrically connected with the cathode of the external direct-current power supply through a bus Vbus-, one end of the capacitor C1 connected with the anode of the direct-current power supply is also electrically connected with the source of the MOS transistor Q1 and the source of the MOS transistor Q3 respectively, and one end of the capacitor C1 connected with the cathode of the direct-current power supply is also electrically connected with the drain of the MOS transistor Q2 and the drain of the MOS transistor Q4 respectively;
the source of the MOS transistor Q1 is connected to one electrical end of a capacitor C2, the other end of the capacitor C2 is electrically connected to the drain of the MOS transistor Q1, the capacitor C2 is connected in parallel with a diode D1 and then connected between the source and the drain of the MOS transistor Q1, wherein the cathode of the diode D1 is electrically connected to the source of the MOS transistor Q1, and the anode of the diode D2 is electrically connected to the drain of the MOS transistor Q1;
the drain of the MOS transistor Q1 is further electrically connected to the source of the MOS transistor Q2, the source of the MOS transistor Q2 is further electrically connected to one end of a capacitor C3, the other end of the capacitor C3 is electrically connected to the drain of the MOS transistor Q2, the capacitor C3 is connected in parallel with a diode D2 and then connected between the source and the drain of the MOS transistor Q2, wherein the cathode of the diode D2 is electrically connected to the source of the MOS transistor Q2, and the anode of the diode D2 is electrically connected to the drain of the MOS transistor Q2;
the source of the MOS transistor Q3 is further electrically connected with one end of a capacitor C4, the other end of the capacitor C4 is electrically connected with the drain of the MOS transistor Q3, the capacitor C4 is connected in parallel with a diode D3 and then connected between the source and the drain of the MOS transistor Q3, wherein the anode of the diode D3 is electrically connected with the source of the MOS transistor Q3, and the cathode of the diode D3 is connected with the drain of the MOS transistor Q3;
the drain of the MOS transistor Q3 is also electrically connected to the gate of the MOS transistor Q4, the source of the MOS transistor Q4 is electrically connected to one end of a capacitor C5, the other end of the capacitor C5 is electrically connected to the drain of the MOS transistor Q4, the capacitor C5 is connected in parallel to a diode D4 and then connected between the source and the drain of the MOS transistor Q4, wherein the cathode of the diode D4 is electrically connected to the source of the MOS transistor Q4, and the anode of the diode D4 is electrically connected to the drain of the MOS transistor Q4.
The drain of the MOS transistor Q1 is electrically connected to one end of an inductor L1 connected to the source of the MOS transistor Q2, the other end of the inductor L1 is electrically connected to one end of a capacitor C6, the other end of the capacitor C6 is electrically connected to one end of an inductor L2, the other end of the inductor L2 is electrically connected to one end of the primary side of a transformer T3, and the other end of the primary side of the transformer T3 is electrically connected to the source of the MOS transistor Q4.
When the direct current power supply works, the voltage of the direct current power supply is added between the bus Vbus plus and the bus Vbus minus, the pulse driving signal sent by the digital control chip DSP controls the conduction and the cut-off of the MOS tube Q1, the MOS tube Q2, the MOS tube Q3 and the MOS tube Q4, and under the phase shifting mode, all the MOS tubes are always conducted at 50% duty ratio (the dead zone is ignored at this moment, and the dead zone time is reasonably set according to the driving circuit and the switching frequency during practical application), and the DSP adjusts the phase shifting angle between the MOS tube Q1 and the MOS tube Q2 and the phase shifting angle between the MOS tube Q3 and the MOS tube Q4, thereby realizing the change of the output voltage and the power.
As a further scheme of the invention: the control module comprises an FPGA and a controller, the grid of the MOS tube Q1 is electrically connected with the A output end of the FPGA, the grid of the MOS tube Q2 is electrically connected with the B output end of the FPGA, the grid of the MOS tube Q3 is electrically connected with the C output end of the FPGA, the grid of the MOS tube Q4 is electrically connected with the D output end of the FPGA, and the output end of the controller is electrically connected with the input end of the FPGA.
As a further scheme of the invention: the rectifying circuit comprises a diode D5, a diode D6, a diode D7 and a diode D8, wherein,
one end of the secondary side of the transformer T3 is electrically connected with the anode of the diode D5, the other end of the secondary side of the transformer T3 is connected with the cathode of the diode D8, the cathode of the diode D5 is electrically connected with the cathode of the diode D6, the anode of the diode D6 is electrically connected with the cathode of the diode D8, the anode of the diode D8 is electrically connected with the anode of the diode D7, and the cathode of the diode D7 is electrically connected with the anode of the diode D5.
As a further scheme of the invention: the LC filter circuit comprises an inductor L3, a capacitor C7 and a resistor R, wherein,
the negative electrode of the diode D5 and the negative electrode of the diode D6 are electrically connected with one end of an inductor L3, the other end of the inductor L3 is electrically connected with one end of a capacitor C7, the other end of the capacitor C7 is electrically connected with the positive electrodes of the diode D7 and the diode D8, and the capacitor C7 is connected with a resistor R in parallel; the resistor R is used to output a voltage.
Through the LC filter circuit, most of the interference signals are prevented from being absorbed by the inductor L3 and become magnetic induction and heat energy, most of the rest is bypassed to the ground by the capacitor C3, so that the effect of the interference signals can be inhibited, and relatively pure direct current can be obtained at the output end.
A low-voltage output method based on the phase-shifted full-bridge circuit topology low-voltage output mechanism comprises the following steps:
s1, testing the lowest output voltage value in an open loop mode; testing the lowest current value in a closed loop mode, drawing a U-I coordinate axis, and determining a phase-shifting mode area and a PWM mode area according to the lowest output voltage value and the current voltage value;
and S2, switching the phase-shifting mode and the PWM mode, and outputting low voltage.
Switching is carried out according to the divided phase-shifting mode region and the divided PWM mode region, when the output voltage is lower than the lowest output voltage value and the output current is smaller than the lowest current value, the PWM mode is switched, and under the mode, the duty ratio of the pulse driving signal actually sent to the MOS tube by the FPGA is the phase shifting angle
Figure BDA0002280147010000051
So when phase shifting angle
Figure BDA0002280147010000061
When the duty ratio of the four MOS tubes is 0, the duty ratios of the four MOS tubes are all 0, so that the situation of repeated charging and discharging of the junction capacitor does not exist, the output can completely reach 0V, and low-voltage output during no-load or light-load is realized.
As a further scheme of the invention: the step S1 includes:
s11, under the phase-shifting mode, using open loop test to output no-load, setting the phase-shifting angle to 0, then outputting voltage, measuring the output voltage value at the moment, and recording the value as Umin;
and S12, in the phase-shifting mode, setting the output voltage to be 1V by using a closed-loop test, then gradually increasing the load, and recording the current value at the moment as Imin when the output voltage can be stabilized at 1V.
And S13, drawing an I-U coordinate axis, and determining a phase shift mode area and a PWM mode area.
As a further scheme of the invention: in step S13, the phase shift mode region and the PWM mode region are determined as follows: u is used as a horizontal coordinate, I is used as a vertical coordinate, wherein the intersection point is (0, 0), the U axis is drawn with (Umax, 0) and (Umin, 0), the I axis is drawn with (0, Imax) and (0, Imin), the area occupied by the phase-shifting mode is the area of Umax Imax, wherein Umax is the maximum value of the output voltage in the phase-shifting mode, and the maximum value of the output current in the Imax phase-shifting mode; and the range of the PWM pattern is in the region of Umin Imin.
As a further scheme of the invention: in step S2, when the output voltage is lower than Umin and the output current is smaller than Imin, the PWM mode is switched to.
The invention has the advantages that:
1. according to the invention, an external power supply is connected with the phase-shifted full-bridge circuit for supplying power, the external power supply is a direct-current power supply, and then the voltage is output through the phase-shifted full-bridge circuit, the transformer T, the rectifying circuit and the filter circuit in sequence, and the phase-shifted full-bridge circuit can control the driving signal, so that when energy is transmitted to the secondary side of the transformer T through the transformer T, low voltage can be output under the condition of no load or light load, and 0V voltage output can be realized.
2. The invention also has the advantages of high efficiency and low cost, and the method for solving the problem of low-voltage output in the prior art usually deadens load, which can greatly reduce the working efficiency of the power supply and increase the volume and the cost of the power supply.
3. In the invention, the on and off of the MOS tube Q1, the MOS tube Q2, the MOS tube Q3 and the MOS tube Q4 are controlled by a pulse driving signal sent by a digital control chip DSP, and the DSP realizes the change of output voltage and power by adjusting the phase shift angle between the MOS tube Q1 and the MOS tube Q2 and the phase shift angle between the MOS tube Q3 and the MOS tube Q4.
4. In the invention, the PWM mode and the phase-shifting mode can be switched to realize low-voltage output, when the output voltage is lower than Umin and the output current is less than Imin, the PWM mode is switched to, and under the mode, the duty ratio of the pulse driving signal actually sent to the MOS tube by the FPGA is the phase shifting angle
Figure BDA0002280147010000071
Therefore, when the phase shift angle is 0, the duty ratios of all the MOS tubes are all 0, and the situation that junction capacitance is repeatedly charged and discharged does not exist, so that the output can completely reach 0V, and low-voltage output during no-load or light-load is realized.
Drawings
Fig. 1 is a circuit diagram of a phase-shifted full-bridge circuit topology low-voltage output mechanism provided in embodiment 1 of the present invention.
Fig. 2 is a signal diagram of a phase shift mode and a PMW mode in the low-voltage output method provided in embodiment 2 of the present invention.
FIG. 3 is a U-I coordinate axis view.
In the figure: 1-a control module; 2-phase-shifted full bridge circuit; 3-transformer T; 4-a rectifying circuit; 5-LC filter circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Fig. 1 is a circuit diagram of a phase-shifted full-bridge circuit topology low-voltage output mechanism provided in embodiment 1 of the present invention, and as shown in fig. 1, the phase-shifted full-bridge circuit topology low-voltage output mechanism includes a control module 1, a phase-shifted full-bridge circuit 2, a transformer T3, a rectification circuit 4, and an LC filter circuit 5, wherein a primary side of the transformer T3 is connected to the phase-shifted full-bridge circuit 2, the phase-shifted full-bridge circuit 2 is connected to an external power supply, a secondary side of the transformer T3 is connected to the rectification circuit 4, and the rectification circuit 4 is connected to the LC filter circuit 5;
the phase-shifted full-bridge circuit 2 is also electrically connected with the control module 1.
Carry out the power supply with shifting phase full-bridge circuit 2 through external power source and linking to each other, and external power source is DC power supply, again in proper order through shifting phase full-bridge circuit 2, transformer T3, rectifier circuit 4 and filter circuit export, through control module 1, control drive signal sends to shifting phase full-bridge circuit 2 department, under the effect of shifting phase full-bridge circuit 2, when making the energy pass through transformer T3 and transmit transformer T3 secondary side, under no-load or the underload condition, also can export the low pressure.
The phase-shift full bridge circuit 2 comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a MOS transistor Q1, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a diode D1, a diode D2, a diode D3, a diode D4, an inductor L1 and an inductor L2.
The control module 1 includes an FPGA (Field-Programmable Gate Array) and a controller.
Wherein,
one end of the capacitor C1 is electrically connected with the anode of an external direct-current power supply through a bus Vbus +, the other end of the capacitor C1 is electrically connected with the cathode of the external direct-current power supply through a bus Vbus-, one end of the capacitor C1 connected with the anode of the direct-current power supply is also electrically connected with the source of the MOS transistor Q1 and the source of the MOS transistor Q3 respectively, and one end of the capacitor C1 connected with the cathode of the direct-current power supply is also electrically connected with the drain of the MOS transistor Q2 and the drain of the MOS transistor Q4 respectively;
further, the gate of the MOS transistor Q1 is connected to a of the FPGA*The output end is electrically connected, the source of the MOS transistor Q1 is connected with one end of the capacitor C2, the other end of the capacitor C2 is electrically connected with the drain of the MOS transistor Q1, the capacitor C2 is connected between the source and the drain of the MOS transistor Q1 after being connected in parallel with the diode D1, the cathode of the diode D1 is electrically connected with the source of the MOS transistor Q1, and the anode of the diode D2 is electrically connected with the drain of the MOS transistor Q1.
Further, the drain of the MOS transistor Q1 is electrically connected to the source of the MOS transistor Q2; the grid of the MOS tube Q2 and the B of the FPGA*The output end of the MOS tube Q2 is electrically connected, the source of the MOS tube Q2 is also electrically connected with one end of a capacitor C3, the other end of the capacitor C3 is electrically connected with the drain of the MOS tube Q2, the capacitor C3 is connected between the source and the drain of the MOS tube Q2 after being connected in parallel with a diode D2, wherein the cathode of the diode D2 is electrically connected with the source of the MOS tube Q2, and the anode of the diode D2 is electrically connected with the drain of the MOS tube Q2;
further, the gate of the MOS transistor Q3 is connected to the gate of the FPGA*The output end is electrically connected, the source of the MOS transistor Q3 is also electrically connected with one end of a capacitor C4, the other end of the capacitor C4 is electrically connected with the drain of the MOS transistor Q3, the capacitor C4 is connected between the source and the drain of the MOS transistor Q3 after being connected in parallel with a diode D3, the anode of the diode D3 is electrically connected with the source of the MOS transistor Q3, and the cathode of the diode D3 is connected with the drain of the MOS transistor Q3.
Further, the drain of the MOS transistor Q3 is electrically connected to the gate of the MOS transistor Q4; the grid of the MOS tube Q4 and the D of the FPGA*The output end is electrically connected, the source of the MOS transistor Q4 is electrically connected with one end of a capacitor C5, the other end of the capacitor C5 is electrically connected with the drain of the MOS transistor Q4, the capacitor C5 is connected between the source and the drain of the MOS transistor Q4 after being connected in parallel with a diode D4, the cathode of the diode D4 is electrically connected with the source of the MOS transistor Q4, and the anode of the diode D4 is electrically connected with the drain of the MOS transistor Q4.
In this embodiment, in order to better control the on and off of the MOS transistor Q1, the MOS transistor Q2, the MOS transistor Q3, and the MOS transistor Q4, the controller is preferably a Digital Signal Processing (DSP) processor, and four output terminals A, B, C, D of the DSP are electrically connected to four input terminals of the FPGA, respectively.
Further, the drain of the MOS transistor Q1 is electrically connected to one end of an inductor L1 connected to the source of the MOS transistor Q2, the other end of the inductor L1 is electrically connected to one end of a capacitor C6, the other end of the capacitor C6 is electrically connected to one end of an inductor L2, the other end of the inductor L2 is electrically connected to one end of the primary side of a transformer T3, and the other end of the primary side of the transformer T3 is electrically connected to the source of the MOS transistor Q4.
When the direct current power supply works, the voltage of the direct current power supply is added between bus Vbus + and bus Vbus-, the conduction and the cut-off of MOS tube Q1, MOS tube Q2, MOS tube Q3 and MOS tube Q4 are controlled by a pulse driving signal sent by a digital control chip DSP, and under the phase-shifting mode, MOS tube Q1, MOS tube Q2, MOS tube Q3 and MOS tube Q4 are always conducted at a 50% duty ratio (the dead zone is ignored at this time, the dead zone time is reasonably set according to a driving circuit and the switching frequency in practical application), and the DSP adjusts the phase shifting angle between MOS tube Q1 and MOS tube Q2 and the phase shifting angle between MOS tube Q3 and MOS tube Q4, so that the output voltage and power are realized.
The embodiment also has the advantages of high efficiency and low cost, and the method for solving the low-voltage output in the prior art mostly realizes the low-voltage output by adding dead load, but the method can greatly reduce the working efficiency of the power supply and increase the volume and the cost of the power supply.
The rectifying circuit 4 comprises a diode D5, a diode D6, a diode D7 and a diode D8, wherein,
one end of the secondary side of the transformer T3 is electrically connected with the anode of the diode D5, the other end of the secondary side of the transformer T3 is connected with the cathode of the diode D8, the cathode of the diode D5 is electrically connected with the cathode of the diode D6, the anode of the diode D6 is electrically connected with the cathode of the diode D8, the anode of the diode D8 is electrically connected with the anode of the diode D7, the cathode of the diode D7 is electrically connected with the anode of the diode D5, and the diode D5, the diode D6, the diode D7 and the diode D8 form a rectifying circuit 4 to convert alternating current into direct current.
The LC filter circuit 5 comprises an inductor L3, a capacitor C7 and a resistor R, wherein,
the negative electrode of the diode D5 and the negative electrode of the diode D6 are electrically connected with one end of an inductor L3, the other end of the inductor L3 is electrically connected with one end of a capacitor C7, the other end of the capacitor C7 is electrically connected with the positive electrodes of the diode D7 and the diode D8, and the capacitor C7 is connected with a resistor R in parallel; the resistor R is used for outputting voltage, most of interference signals are prevented by the inductor L3 from being absorbed to become magnetic induction and heat energy through the LC filter circuit 5, most of the rest interference signals are bypassed to the ground by the capacitor C7, the effect of the interference signals can be inhibited, and relatively pure direct current is obtained at the output end.
Example 2
A low-voltage output method based on the phase-shifted full-bridge circuit topology low-voltage output mechanism of the embodiment 1 comprises the following steps:
s1, testing the lowest output voltage value in an open loop mode; and testing the lowest current value in a closed loop manner, drawing a U-I coordinate axis according to the lowest output voltage value and the lowest current value, and determining a phase-shifting mode area and a PWM (Pulse Width Modulation, which is a very effective mode for controlling an analog circuit by utilizing the digital output of a microprocessor) mode area;
s11, in actual use, because of different hardware model selection parameters, the lowest output voltage value when the phase shift angle of the phase shift mode is 0 needs to be tested firstly; in a phase-shifting mode, outputting no load by using an open loop test, setting a phase shifting angle to be 0, then outputting voltage, measuring the output voltage value at the moment, and recording the value as Umin;
and S12, in the phase-shifting mode, setting the output voltage to be 1V by using a closed-loop test, then gradually increasing the load, and recording the current value at the moment as Imin when the output voltage can be stabilized at 1V.
S13, finally drawing an I-U coordinate axis, determining a phase shift mode region and a PWM mode region, dividing the working regions of the phase shift mode and the PWM mode, where fig. 3 is a U-I coordinate axis diagram, U is an abscissa, and as shown in fig. 3, I is an ordinate, where the intersection is (0, 0), the U axis is drawn with (Umax, 0), (Umin, 0), the I axis is drawn with (0, Imax), (0, Imin), the occupied region of the phase shift mode is the region of Umax Imax, where Umax is the maximum value that the output voltage can take in the phase shift mode, and the maximum value that the output current can take in the Imax phase shift mode; both Umax and Imax can be obtained by measurement; and the range of the PWM pattern is in the region of Umin Imin.
Fig. 2 is a signal diagram of a phase shift mode and a PMW mode in the low-voltage output method according to embodiment 2 of the present invention, for example, in the phase shift mode of fig. 2, driving waveforms of the MOS transistor Q1, the MOS transistor Q2, the MOS transistor Q3, and the MOS transistor Q4 correspond to waveforms a, B, C, and D in fig. 2, and all the MOSs are always turned on at a 50% duty ratio (dead zones are omitted here), and the digital control chip DSP implements magnitudes of output voltage and power by adjusting magnitudes of a phase shift angle between the MOS transistor Q1 and the MOS transistor Q2, and magnitudes of a phase shift angle between the transistor Q3 and the transistor Q4, and at this time, the FPGA in fig. 2 directly forwards the driving signal a, the driving signal B, the driving signal C, and the driving signal D sent by the DSP without any processing to the corresponding MOS transistors;
PWM mode: under the same topological structure, a pulse driving signal A, a pulse driving signal B, a pulse driving signal C and a pulse driving signal D sent by a DSP are processed by an FPGA, the FPGA firstly carries out AND logical operation on the pulse driving signal A and the pulse driving signal D, and then the signals subjected to AND logical operation are used as the driving of an MOS tube Q1 and an MOSD and are respectively marked as a driving signal A and a driving signal D; similarly, the driving signal B and the driving signal C are subjected to and logical operation, and then the driving signal B and the driving signal C subjected to and logical operation are used for driving the MOS transistor Q2 and the MOS transistor Q3.
S2, switching between a phase-shifting mode and a PWM mode;
when the output voltage is lower than Umin and the output current is less than Imin, switching to a PWM mode in which FThe duty ratio of the pulse driving signal actually sent to the MOS tube by the PGA is the phase shifting angle
Figure BDA0002280147010000131
Therefore, when the phase shift angle is 0, the duty ratios of all four MOS tubes are 0, and the situation that junction capacitors are repeatedly charged and discharged does not exist, so that the output voltage can completely reach 0V, and low-voltage output during no-load or light-load is realized.
The working principle is as follows: according to the magnitude of the output voltage, switching a phase-shifting mode and a PWM mode, wherein in the PWM mode, the FPGA firstly performs AND logic operation on a pulse driving signal A and a pulse driving signal D, and then the signals subjected to the AND logic operation are used as the driving of an MOS tube Q1 and an MOSD and are respectively marked as a driving signal A and a driving signal D; similarly, the drive signal B and the drive signal C are subjected to and logical operation, and then the drive signal B and the drive signal C subjected to and logical operation are used for driving the MOS transistor Q2 and the MOS transistor Q3; at the moment, the duty ratio of the pulse driving signal of the MOS tube is the phase shifting angle
Figure BDA0002280147010000141
When the phase shift angle is 0, the output voltage can completely reach 0V, and the phase shift circuit has the advantages of small volume and low cost while outputting 0V.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (6)

1. The utility model provides a phase-shifting full-bridge circuit topology low pressure output method, its characterized in that, this method is realized including phase-shifting full-bridge circuit topology low pressure output structure, phase-shifting full-bridge circuit topology low pressure output structure includes transformer T (3), phase-shifting full-bridge circuit (2), rectifier circuit (4), LC filter circuit, control module (1), the former limit of transformer T (3) links to each other with phase-shifting full-bridge circuit (2), phase-shifting full-bridge circuit (2) link to each other with external power supply, transformer T (3) secondary is continuous with rectifier circuit (4), rectifier circuit (4) link to each other with LC filter circuit (5), phase-shifting full-bridge circuit (2) still link to each other with control module (1) electrical property, this method includes following step:
s1, testing the lowest output voltage value in an open loop mode; testing the lowest current value in a closed loop mode, drawing a U-I coordinate axis, and determining a phase-shifting mode area and a PWM mode area;
the step S1 includes:
s11, in a phase-shifting mode, an open loop test is used, power supply is carried out by connecting an external power supply with a phase-shifting full-bridge circuit (2), the external power supply is a direct-current power supply, and then the external power supply is output through the phase-shifting full-bridge circuit (2), a transformer T (3), a rectifying circuit (4) and a filter circuit in sequence, a control module (1) is used for controlling a driving signal to be sent to the phase-shifting full-bridge circuit (2), under the action of the phase-shifting full-bridge circuit (2), when energy is transmitted to a secondary side of the transformer T (3) through the transformer T (3), no load is output, a phase shifting angle is set to be 0, then voltage is output, the output voltage value at the moment is measured, and the Umin is recorded;
s12, under the phase-shifting mode, a closed-loop test is used, the output voltage is set to be 1V, then the load is gradually increased, and when the output voltage can be stabilized at 1V, the current value at the moment is recorded and is Imin;
s13, drawing an I-U coordinate axis, and determining a phase-shifting mode area and a PWM mode area;
in step S13, the phase shift mode region and the PWM mode region are determined as follows: u is used as an abscissa, I is used as an ordinate, wherein the intersection point is (0, 0), the U axis is drawn with (Umax, 0) and (Umin, 0), the I axis is drawn with (0, Imax) and (0, Imin), and the region occupied by the phase-shifting mode is the region of Umax and Imax; and the range of the PWM pattern is in the area of Umin Imin;
s2, switching a phase-shifting mode and a PWM mode, and outputting low voltage;
and when the output voltage is lower than Umin and the output current is smaller than Imin, switching to the PWM mode.
2. The phase-shifted full-bridge circuit topology low-voltage output method according to claim 1, wherein the phase-shifted full-bridge circuit (2) comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a MOS transistor Q1, a MOS transistor Q2, a MOS transistor Q3, a MOS transistor Q4, a diode D1, a diode D2, a diode D3, a diode D4, an inductor L1 and an inductor L2, wherein,
one end of the capacitor C1 is electrically connected with the anode of an external direct-current power supply through a bus Vbus +, the other end of the capacitor C1 is electrically connected with the cathode of the external direct-current power supply through a bus Vbus-, one end of the capacitor C1 connected with the anode of the direct-current power supply is also electrically connected with the source of the MOS transistor Q1 and the source of the MOS transistor Q3 respectively, and one end of the capacitor C1 connected with the cathode of the direct-current power supply is also electrically connected with the drain of the MOS transistor Q2 and the drain of the MOS transistor Q4 respectively;
the source of the MOS transistor Q1 is connected to one electrical end of a capacitor C2, the other end of the capacitor C2 is electrically connected to the drain of the MOS transistor Q1, the capacitor C2 is connected in parallel with a diode D1 and then connected between the source and the drain of the MOS transistor Q1, wherein the cathode of the diode D1 is electrically connected to the source of the MOS transistor Q1, and the anode of the diode D2 is electrically connected to the drain of the MOS transistor Q1;
the drain electrode of the MOS transistor Q1 is also electrically connected with the source electrode of the MOS transistor Q2; the source of the MOS transistor Q2 is further electrically connected with one end of a capacitor C3, the other end of the capacitor C3 is electrically connected with the drain of the MOS transistor Q2, the capacitor C3 is connected in parallel with a diode D2 and then connected between the source and the drain of the MOS transistor Q2, wherein the cathode of the diode D2 is electrically connected with the source of the MOS transistor Q2, and the anode of the diode D2 is electrically connected with the drain of the MOS transistor Q2;
the source of the MOS transistor Q3 is further electrically connected with one end of a capacitor C4, the other end of the capacitor C4 is electrically connected with the drain of the MOS transistor Q3, the capacitor C4 is connected in parallel with a diode D3 and then connected between the source and the drain of the MOS transistor Q3, wherein the anode of the diode D3 is electrically connected with the source of the MOS transistor Q3, and the cathode of the diode D3 is connected with the drain of the MOS transistor Q3;
of the MOS transistor Q3The drain electrode is also electrically connected with the grid electrode of the MOS tube Q4; the grid of the MOS tube Q4 and the D of the FPGA*The output end of the MOS tube Q4 is electrically connected, the source of the MOS tube Q4 is electrically connected with one end of a capacitor C5, the other end of the capacitor C5 is electrically connected with the drain of the MOS tube Q4, the capacitor C5 is connected between the source and the drain of the MOS tube Q4 after being connected in parallel with a diode D4, the cathode of the diode D4 is electrically connected with the source of the MOS tube Q4, and the anode of the diode D4 is electrically connected with the drain of the MOS tube Q4;
the drain of the MOS transistor Q1 is electrically connected to one end of an inductor L1 connected to the source of the MOS transistor Q2, the other end of the inductor L1 is electrically connected to one end of a capacitor C6, the other end of the capacitor C6 is electrically connected to one end of an inductor L2, the other end of the inductor L2 is electrically connected to one end of the primary side of the transformer T (3), and the other end of the primary side of the transformer T (3) is electrically connected to the source of the MOS transistor Q4.
3. The phase-shifted full-bridge topology low-voltage output method according to claim 2, wherein the control module (1) comprises an FPGA and a controller, the gate of the MOS transistor Q1 is electrically connected to the a output terminal of the FPGA, the gate of the MOS transistor Q2 is electrically connected to the B output terminal of the FPGA, the gate of the MOS transistor Q3 is electrically connected to the C output terminal of the FPGA, the gate of the MOS transistor Q4 is electrically connected to the D output terminal of the FPGA, and the output terminal of the controller is electrically connected to the input terminal of the FPGA.
4. The phase-shifted full-bridge topology low-voltage output method according to claim 2, wherein the rectifying circuit (4) comprises a diode D5, a diode D6, a diode D7 and a diode D8,
one end of the secondary side of the transformer T (3) is electrically connected with the anode of the diode D5, the other end of the secondary side of the transformer T (3) is connected with the cathode of the diode D8, the cathode of the diode D5 is electrically connected with the cathode of the diode D6, the anode of the diode D6 is electrically connected with the cathode of the diode D8, the anode of the diode D8 is electrically connected with the anode of the diode D7, and the cathode of the diode D7 is electrically connected with the anode of the diode D5.
5. The phase-shifted full-bridge topology low-voltage output method according to claim 4, wherein the LC filter circuit (5) comprises an inductor L3, a capacitor C3, a resistor R, wherein,
the negative electrode of the diode D5 and the negative electrode of the diode D6 are electrically connected with one end of an inductor L3, the other end of the inductor L3 is electrically connected with one end of a capacitor C7, the other end of the capacitor C7 is electrically connected with the positive electrodes of the diode D7 and the diode D8, and the capacitor C7 is connected with a resistor R in parallel.
6. The phase-shifted full-bridge topology low-voltage output method according to claim 5, wherein Umax is the maximum value that the output voltage can take in the phase-shifted mode, and the maximum value that the output current can take in the Imax phase-shifted mode.
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