CN110931564A - 半导体结构、晶体管、可变电容及元器件 - Google Patents

半导体结构、晶体管、可变电容及元器件 Download PDF

Info

Publication number
CN110931564A
CN110931564A CN201911252048.0A CN201911252048A CN110931564A CN 110931564 A CN110931564 A CN 110931564A CN 201911252048 A CN201911252048 A CN 201911252048A CN 110931564 A CN110931564 A CN 110931564A
Authority
CN
China
Prior art keywords
channel
transistor
semiconductor structure
type
variable capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911252048.0A
Other languages
English (en)
Other versions
CN110931564B (zh
Inventor
田志
李娟娟
邵华
陈昊瑜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN201911252048.0A priority Critical patent/CN110931564B/zh
Publication of CN110931564A publication Critical patent/CN110931564A/zh
Application granted granted Critical
Publication of CN110931564B publication Critical patent/CN110931564B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供了一种半导体结构，包括：衬底以及位于衬底上的栅极结构，所述衬底包括势阱，势阱中形成有第一通道、第二通道、第三通道和第四通道，所述第一通道和所述第二通道连通，第一通道和第二通道注入相同的离子，第三通道和第四通道注入相同的离子。本发明还提供了一种晶体管和一种可变电容，均包括如上述所述的半导体结构。本发明还提供了一种元器件，包括晶体管以及位于所述晶体管旁边的可变电容，晶体管和可变电容的势阱相同。在本发明提供的半导体结构、晶体管、可变电容及元器件中，晶体管和可变电容的势阱为同一类型的势阱，由于是同一类型的势阱，无需考量类似N型势阱和P型势阱之间的最小隔离需求，可以有效缩减版图面积。

Description

半导体结构、晶体管、可变电容及元器件
技术领域
本发明涉及半导体技术领域，尤其是涉及一种半导体结构、晶体管、可变电容及元器件。
背景技术
随着物联网和可穿戴技术的发展，要求更小的电路来实现更多功能，面积的缩减可以从两方面，一种是集成电路技术节点的前进，从90nm，55nm，40nm，28nm，14nm，甚至到7nm，技术节点的进步可以使单位面积容纳更多的晶体管，从而实现芯片的面积缩减，另一种是设计的优化，包含功能设计的优化，例如对于高电压的运用，将原有的多级的增压，利用电容实现级数缩减)，还有就是版图的优化，通过优化版图的摆放和设计规则的优化来实现小面积芯片设计。
对于常用的器件，如晶体管，电容，电阻，二极管，三极管，其都有对应的规则来规定画法和相对的距离要求。对于可变电容结构，目前55nm低功耗逻辑使用的利用衬底掺杂类型，源漏极与多晶硅掺杂相同的类似晶体管的薄氧化硅结构来形成的可变电容器(薄氧化硅，单位面积可以提供更多的电容)，这种结构与原有的二极管的可变电容器相比的优点是与互补型晶体管(CMOS)制造工艺完全兼容，而且与晶体管搭配使用，可以消除原有单纯二极管与多晶硅之间多晶硅密度差异导致的刻蚀负载效应。虽然这种电容结构可以降低对应的面积，但是其中用到N型沟道晶体管(NMOS)与N型变容二极管(N varactor)时。由于NMOS在P型势阱中，而N型可变电容器在N型势阱中，二者的势阱需要一定的距离间隔，以及N型势阱与N型有源区也有距离的要求，导致二者连接使用时面积增加，不利于芯片面积的缩减。
发明内容
本发明的目的在于提供一种半导体结构、晶体管、可变电容及元器件，可以消除晶体管和可变电容因为势阱不同而对晶体管和可变电容的距离的要求，最终可以缩减版图面积。
为了达到上述目的，本发明提供了一种半导体结构，包括：衬底以及位于所述衬底上的栅极结构，所述衬底包括势阱，所述势阱中形成有第一通道、第二通道、第三通道和第四通道，所述第一通道和所述第二通道连通，第一通道和第二通道注入相同的离子，第三通道和第四通道注入相同的离子。
可选的，在所述的半导体结构中，所述势阱为P型势阱或N型势阱。
可选的，在所述的半导体结构中，当势阱为P型势阱时，注入所述第一通道和所述第二通道的离子为输入/输出N型器件浅轻掺杂离子，注入所述第三通道和所述第四通道的离子为源漏极N型掺杂离子；当势阱为N型势阱时，注入所述第一通道和所述第二通道的离子为源漏极N型掺杂离子，注入所述第三通道和所述第四通道的离子为输入/输出N型器件浅轻掺杂离子。
可选的，在所述的半导体结构中，所述栅极结构包括：位于所述衬底上的浮栅和位于所述浮栅两侧的ONO层以及位于所述ONO两侧的控制栅。
可选的，在所述的半导体结构中，第三通道位于第一通道内，第四通道位于第二通道内。
可选的，在所述的半导体结构中，所述第三通道位于所述第一通道左侧，所述第四通道位于所述第二通道右侧。
可选的，在所述的半导体结构中，所述三通道和所述第四通道分别连接所述控制栅。
本发明还提供了一种晶体管，包括如上述所述的半导体结构。
本发明还提供了一种可变电容，包括如上述所述的半导体结构。
本发明还提供了一种元器件，包括晶体管以及位于所述晶体管旁边的可变电容，所述晶体管的势阱和所述可变电容的势阱相同。
在本发明提供的半导体结构、晶体管、可变电容及元器件中，晶体管和可变电容的势阱为同一类型的势阱，由于是同一类型的势阱，无需考量类似N型势阱和P型势阱之间的最小隔离需求，可以有效缩减版图面积。
附图说明
图1是本发明实施例的半导体的结构的结构示意图；
图中：110-衬底、120-势阱、130-第一通道、140-第二通道、150-第三通道、160-第四通道、170-栅氧化层、180-浮栅、190-ONO层、200-控制栅。
具体实施方式
下面将结合示意图对本发明的具体实施方式进行更详细的描述。根据下列描述和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
在下文中，术语“第一”“第二”等用于在类似要素之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换。类似的，如果本文所述的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所述的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。
参照图1，本发明提供了一种半导体结构，包括：衬底110以及位于所述衬底上的栅极结构，所述衬底110包括势阱120，所述势阱120中形成有第一通道、130第二通道140、第三通道150和第四通道160，所述第一通道130和所述第二通道140连通，第一通道130和第二通道140注入相同的离子，第三通道150和第四通道160注入相同的离子。
具体地，提供一衬底110，衬底110可以是硅衬底，可以采用晶圆作为衬底，在衬底110内通过离子注入形成势阱120，势阱可以为P型势阱或N型势阱，本发明实施例中，形成P型势阱。
在P型势阱120内通过注入输入/输出N型器件浅轻掺杂离子形成第一通道130和第二通道140，第一通道130和第二通道140连通，继续在P型势阱120内通过注入源漏极N型掺杂离子形成第三通道150和第四通道160。第三通道150位于第一通道130内，第四通道160位于第二通道140内，并且，第三通道150位于第一通道130左侧，第四通道160位于第二通道140右侧，即第三通道150和第四通道160分别位于第一通道130和第二通道140的一侧。
在本发明的其他实施例中，如果形成的是N型势阱，则在N型势阱内通过注入源漏极N型掺杂离子形成第一通道和第二通道，第一通道和第二通道连通，继续在N型势阱内通过注入输入/输出N型器件浅轻掺杂离子形成第三通道和第四通道。
接着，形成位于所述衬底110上的栅氧化层170以及位于所述栅氧化层170上的浮栅180。栅氧化层170可以通过沉积一氧化层来得到，浮栅180可以通过沉积一多晶硅层，再对多晶硅层刻蚀来得到。
接着，形成位于所述浮栅180两侧的ONO层190以及位于所述所述ONO层190两侧的控制栅200，所述ONO层190隔离所述浮栅180和所述控制栅200。ONO层190可以通过依次沉积二氧化硅层、二氮化硅层和二氧化硅层来得到，控制栅200可以通过在ONO层190上沉积多晶硅层，刻蚀多晶硅层来得到。其中，所述三通道150和所述第四通道160分别连接所述控制栅200。
进一步的，本发明还提供了一种晶体管和一种可变电容，晶体管和可变电容均包括上述半导体结构，即以上述方法同时在一晶圆上形成晶体管以及位于所述晶体管旁边的可变电容。
进一步的，本发明还提供了一种元器件，元器件包括晶体管以及位于所述晶体管旁边的可变电容，晶体管的势阱和所述可变电容的势阱相同，也就是说晶体管和可变电容的势阱为同一类型的势阱，要么都为P型势阱或者都为N型势阱。并且在制作时，可以在同一晶圆上同时形成，同样的，由于晶体管和可变电容是同一类型的势阱，就不用像现有技术需要考量N型势阱和P型势阱之间的最小隔离需求，因此，相对于现有技术，本发明实施例可以有效缩减版图面积。
综上，在本发明实施例提供的半导体结构、晶体管、可变电容及元器件中，晶体管和可变电容的势阱为同一类型的势阱，由于是同一类型的势阱，无需考量类似N型势阱和P型势阱之间的最小隔离需求，可以有效缩减版图面积。
上述仅为本发明的优选实施例而已，并不对本发明起到任何限制作用。任何所属技术领域的技术人员，在不脱离本发明的技术方案的范围内，对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动，均属未脱离本发明的技术方案的内容，仍属于本发明的保护范围之内。

Claims (10)

1.一种半导体结构，其特征在于，包括：衬底以及位于所述衬底上的栅极结构，所述衬底包括势阱，所述势阱中形成有第一通道、第二通道、第三通道和第四通道，所述第一通道和所述第二通道连通，第一通道和第二通道注入相同的离子，第三通道和第四通道注入相同的离子。
2.如权利要求1所述的半导体结构，其特征在于，所述势阱为P型势阱或N型势阱。
3.如权利要求2所述的半导体结构，其特征在于，当势阱为P型势阱时，注入所述第一通道和所述第二通道的离子为输入/输出N型器件浅轻掺杂离子，注入所述第三通道和所述第四通道的离子为源漏极N型掺杂离子；当势阱为N型势阱时，注入所述第一通道和所述第二通道的离子为源漏极N型掺杂离子，注入所述第三通道和所述第四通道的离子为输入/输出N型器件浅轻掺杂离子。
4.如权利要求1所述的半导体结构，其特征在于，所述栅极结构包括：位于所述衬底上的浮栅和位于所述浮栅两侧的ONO层以及位于所述ONO两侧的控制栅。
5.如权利要求1所述的半导体结构，其特征在于，第三通道位于第一通道内，第四通道位于第二通道内。
6.如权利要求5所述的半导体结构，其特征在于，所述第三通道位于所述第一通道左侧，所述第四通道位于所述第二通道右侧。
7.如权利要求5所述的半导体结构，其特征在于，所述三通道和所述第四通道分别连接所述控制栅。
8.一种晶体管，其特征在于，包括如权利要求1-7任一项所述的半导体结构。
9.一种可变电容，其特征在于，包括如权利要求1-7任一项所述的半导体结构。
10.一种元器件，其特征在于，包括如权利要求8的晶体管以及位于所述晶体管旁边的如权利要求9的可变电容，所述晶体管的势阱和所述可变电容的势阱相同。
CN201911252048.0A 2019-12-09 2019-12-09 半导体结构、晶体管、可变电容及元器件 Active CN110931564B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911252048.0A CN110931564B (zh) 2019-12-09 2019-12-09 半导体结构、晶体管、可变电容及元器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911252048.0A CN110931564B (zh) 2019-12-09 2019-12-09 半导体结构、晶体管、可变电容及元器件

Publications (2)

Publication Number Publication Date
CN110931564A true CN110931564A (zh) 2020-03-27
CN110931564B CN110931564B (zh) 2023-08-18

Family

ID=69857735

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911252048.0A Active CN110931564B (zh) 2019-12-09 2019-12-09 半导体结构、晶体管、可变电容及元器件

Country Status (1)

Country Link
CN (1) CN110931564B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097485A (zh) * 2011-01-27 2011-06-15 上海宏力半导体制造有限公司 Edmos晶体管及其制作方法
CN103137479A (zh) * 2011-11-24 2013-06-05 中芯国际集成电路制造(上海)有限公司 金属氧化物半导体管及其制作方法
US20150348968A1 (en) * 2014-05-30 2015-12-03 Texas Instruments Incorporated Methods and Apparatus for Artificial Exciton in CMOS Processes
CN105226058A (zh) * 2014-06-30 2016-01-06 万国半导体股份有限公司 利用深扩散区在单片功率集成电路中制备jfet和ldmos晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097485A (zh) * 2011-01-27 2011-06-15 上海宏力半导体制造有限公司 Edmos晶体管及其制作方法
CN103137479A (zh) * 2011-11-24 2013-06-05 中芯国际集成电路制造(上海)有限公司 金属氧化物半导体管及其制作方法
US20150348968A1 (en) * 2014-05-30 2015-12-03 Texas Instruments Incorporated Methods and Apparatus for Artificial Exciton in CMOS Processes
CN105226058A (zh) * 2014-06-30 2016-01-06 万国半导体股份有限公司 利用深扩散区在单片功率集成电路中制备jfet和ldmos晶体管

Also Published As

Publication number Publication date
CN110931564B (zh) 2023-08-18

Similar Documents

Publication Publication Date Title
US11271011B2 (en) Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE)
US8338864B2 (en) Semiconductor device
US7323754B2 (en) Semiconductor device and its manufacture method
US10026753B2 (en) Method for compensating for temperature effects in semiconductor device structures using a diode structure and a tunable resistor
US20100264484A1 (en) Semiconductor device
US7705666B1 (en) Filler circuit cell
US7932563B2 (en) Techniques for improving transistor-to-transistor stress uniformity
US20080061347A1 (en) Configuration and method of manufacturing the one-time programmable (OTP) memory cells
US10157910B2 (en) Circuits and structures including tap cells and fabrication methods thereof
US20130270636A1 (en) Transistor Having An Isolated Body For High Voltage Operation
US6605981B2 (en) Apparatus for biasing ultra-low voltage logic circuits
US8110454B2 (en) Methods of forming drain extended transistors
US7091797B2 (en) MOS-type variable capacitance element and voltage control oscillation circuit
US10381347B2 (en) Semiconductor apparatus
US8735994B2 (en) Electrical-free dummy gate
CN106486425A (zh) Fdsoi技术中使用可调式时序电路的方法、装置及系统
CN110931564A (zh) 半导体结构、晶体管、可变电容及元器件
US10777558B1 (en) CMOS-based integrated circuit products with isolated P-wells for body-biasing transistor devices
JP2015095492A (ja) 半導体装置
WO2006023199A1 (en) High transconductance and drive current high voltage mos transistors
US9012998B2 (en) Gate depletion drain extended MOS transistor
US7759740B1 (en) Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells
CN109103189B (zh) 由n型电容耦合晶体管构成的一次可编程器件
KR20030088763A (ko) 채널 접합을 이용한 씨모스 트랜지스터 및 이를 이용한논리 회로

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant