CN110915117B

CN110915117B - Multi-buck single-boost optimizer

Info

Publication number: CN110915117B
Application number: CN201880024934.5A
Authority: CN
Inventors: 戴和平; 毛小林
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Digital Power Technologies Co Ltd
Priority date: 2017-04-17
Filing date: 2018-04-17
Publication date: 2021-09-03
Anticipated expiration: 2038-04-17
Also published as: US20180301905A1; EP3602765B1; EP3602765A4; WO2018192495A1; US10333314B2; CN110915117A; EP3602765A1

Abstract

The present invention relates to techniques for providing power, voltage and/or current from a DC power supply assembly, such as a photovoltaic module or a DC battery. One aspect includes a buck-boost optimizer (110) having a plurality of inductor-less buck stages (104) and boost stages (106). The buck-boost optimizer (110) may be used in a power generation system. The combined output voltage of each buck stage (104) may be input to a boost stage (106). The boost stage (106) may have an inductor (208) that may be used as an energy storage device to boost the voltage and filter the signal from the buck stage (104). Thus, the buck-boost optimizer (110) may use a single inductor. Using a single inductor can achieve a very efficient power generation system. Further, the cost and size of components in the power generation system may be reduced.

Description

Multi-buck single-boost optimizer

Cross application of related applications

This patent application claims priority from a prior application of U.S. non-provisional patent application No. 15/489,278 entitled "multiple buck stage single boost stage optimizer" filed on 2017, 4, month 17.

Background

Photovoltaic (PV) panels generate a Direct Current (DC) voltage. Typically, the DC voltage and DC current from a photovoltaic panel are much lower than the voltage and current required by an Alternating Current (AC) grid. Typically, multiple photovoltaic panels are employed in a photovoltaic power generation system to provide the necessary voltage and current to an AC power grid. The DC voltage/current also needs to be converted to an AC voltage/current.

One of the major challenges in operating photovoltaic panels is how to obtain maximum power efficiency. For at least some photovoltaic panels, there is an output voltage at which the photovoltaic panel produces maximum power output. The maximum power may vary with such factors as solar radiation and photovoltaic panel temperature. Further, the conditions of the various photovoltaic panels may be different from each other. Thus, in order for a photovoltaic power generation system to operate at or near optimal power efficiency, the various photovoltaic panels may need to operate at different output voltages.

Other power generation systems, such as systems that employ DC battery packs to provide power, also present challenges to operation.

Disclosure of Invention

In a first embodiment, a system includes a plurality of inductor-less buck stages, each having an input for receiving a DC voltage from a DC power source and a buck stage output for providing the DC voltage. The system also includes logic to operate the plurality of buck stages to regulate the power output of each DC power source. The system also includes a boost stage including a boost stage output and a boost stage input for receiving the combined DC voltage from the plurality of buck stage outputs.

In a second embodiment, according to the first embodiment, the voltage increasing stage further comprises a filter for receiving the current outputs of the plurality of voltage decreasing stages.

According to the second embodiment, in a third embodiment, the voltage boost stage is configured to use the filter as an energy storage device.

According to the second and third embodiments, in a fourth embodiment, the filter is an inductor.

In a fifth embodiment, according to the first through fourth embodiments, the logic is further to: receiving a signal from an output of each DC power supply; and controlling a duty cycle of each of the buck stages based on the signal.

According to the first to fifth embodiments, in a sixth embodiment the DC voltage source is a photovoltaic module. The logic is further to: controlling duty cycles of the plurality of buck stages to operate the photovoltaic module at a maximum power point.

In a seventh embodiment, according to the first to sixth embodiments, the system further comprises a DC-AC converter having an input connected to the output of the voltage boost stage, wherein the DC-AC converter is configured to regulate a DC voltage at the input of the DC-AC converter.

In an eighth embodiment in accordance with the first through seventh embodiments, the logic is further configured to control the duty cycle of the voltage boost stage such that when the DC voltage at the input of the DC-AC converter is determined not to satisfy the discrimination condition, in response thereto, the voltage at the input of the voltage boost stage is reduced relative to the voltage at the output of the voltage boost stage.

In a ninth embodiment, in accordance with the first through eighth embodiments, the logic is further to: when it is determined that the combined output voltage of the plurality of buck stages needs to fall below the threshold voltage to maintain the target duty cycle of the buck stage, in response, instructing the boost stage to reduce the input terminal voltage of the boost stage below the threshold voltage.

In a tenth embodiment, the plurality of buck stages are for generating pulse width modulated output voltages at the same switching frequency, wherein the plurality of buck stages are for interleaving the pulse width modulated output voltages.

An eleventh embodiment provides a method for operating a power generation system. The method comprises the following steps: receiving a DC voltage from each of a plurality of photovoltaic modules at a corresponding plurality of inductor-less buck stages; operating each of the plurality of inductor-less buck stages to regulate the power output of the corresponding photovoltaic module, including generating an output voltage for each buck stage; receiving at an input of the voltage increasing stage a combined output voltage from all of the plurality of voltage decreasing stages; operating the voltage increasing stage to increase the combined output voltage from the voltage decreasing stage; and providing the boosted voltage to the solar inverter.

In a twelfth embodiment, the method further comprises receiving the output currents of the plurality of inductor-less buck stages at a filter of the boost stage.

According to the eleventh to twelfth embodiments, in the thirteenth embodiment, the filter includes an inductor. The method further includes operating the voltage increasing stage to increase the output voltage from the voltage decreasing stage includes storing energy in the inductor.

According to the eleventh to thirteenth embodiments, in a fourteenth embodiment, the method further comprises: reducing a voltage at an input of the voltage increasing stage in response to a condition of the plurality of voltage decreasing stages; and boosting the reduced voltage by the voltage boost stage to maintain the output voltage of the voltage boost stage at a target voltage level.

In a fifteenth embodiment, according to the eleventh through fourteenth embodiments, the operating each of the plurality of inductor-less buck stages to regulate the power output of the corresponding photovoltaic module comprises: generating a pulse width modulated output voltage at each of the buck stages at the same switching frequency; and interleaving the pulse width modulated output voltage.

A sixteenth embodiment provides a photovoltaic power system, comprising: a plurality of photovoltaic modules for providing a DC voltage; and a buck-boost converter. The buck-boost converter includes a plurality of inductor-less buck stages and a boost stage. Each said inductor-less buck stage includes an input for receiving a DC voltage from one said photovoltaic module. Each said inductor-less buck stage includes an output for providing a DC voltage. Each of the buck stages is for regulating the power output of a corresponding photovoltaic module. The voltage increasing stage includes an input for receiving a combined DC voltage from a plurality of voltage decreasing stage outputs. The voltage boosting stage comprises an output for providing a DC voltage.

In a seventeenth embodiment, the plurality of buck stages are for providing a series output current according to the sixteenth embodiment. The boost stage includes an inductor for receiving the series current.

In an eighteenth embodiment, according to the sixteenth to seventeenth embodiments, the boost stage is configured to use the inductor as an energy storage device to boost the combined DC voltage from the plurality of buck stages and to provide a boosted voltage at an output of the boost stage.

According to the sixteenth to eighteenth embodiments, in a nineteenth embodiment, the photovoltaic power system includes a plurality of buck-boost converters described in the sixteenth embodiment. The plurality of buck-boost converters are connected in series. The combined DC voltage output from the boost stages of the plurality of buck-boost converters is provided to a solar inverter.

In a twentieth embodiment, the photovoltaic power system further includes a plurality of buck-boost converters as described in the sixteenth embodiment. The plurality of buck-boost converters are connected in series. The photovoltaic power system further includes an additional boost stage having an input for receiving the combined DC voltage from the boost stages of the plurality of buck-boost converters. The photovoltaic power system also includes a solar inverter having a DC input for receiving a DC voltage from the output of the additional boost stage.

According to the sixteenth to twentieth embodiments, in a twenty-first embodiment, the plurality of buck stages are for generating pulse width modulated output voltages at a same switching frequency. The plurality of buck stages are for interleaving the pulse width modulated output voltage.

According to the sixteenth to twenty-first embodiments, in a twenty-second embodiment, a first of the photovoltaic modules comprises a single photovoltaic panel, a plurality of photovoltaic panels connected in series, or a sub-string of photovoltaic panels.

In a twenty-third embodiment, a photovoltaic power system includes a plurality of buck-boost converters as described in the sixteenth embodiment, in accordance with the sixteenth to twenty-second embodiments. The plurality of buck-boost converters are connected in series, in parallel, or a combination of series and parallel.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the background.

Drawings

Aspects of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

FIG. 1 is a diagram of a power generation system with a buck-boost optimizer connected to a DC power source according to an embodiment;

FIG. 2A is a diagram of a buck-boost optimizer of an embodiment;

2B-2D illustrate various embodiments of electrical components that may be used in the circuit of FIG. 2A;

FIG. 2E is a diagram of a power generation system 200 with a buck-boost optimizer of an embodiment;

FIG. 2F is a diagram of a power generation system 250 having a buck-boost optimizer of another embodiment;

FIG. 3 is a diagram of a power generation system 300 with a buck-boost optimizer of an embodiment;

FIG. 4 is a diagram of a power generation system 400 having another configuration of buck modules and another configuration of boost stages;

fig. 5 illustrates an embodiment of a power generation system 500 in which more than one voltage boost stage is present;

FIG. 6 illustrates an embodiment of another power generation system 600 in which multiple voltage boost stages are present;

FIG. 7 illustrates an embodiment of a power generation system 700 with series and parallel connections of modules;

FIG. 8 illustrates an embodiment of another power generation system 800 in which there are multiple buck-boost modules connected together;

FIG. 9 is a flow diagram of a process 900 to operate a buck-boost optimizer of an embodiment;

FIG. 10A shows the output voltages of a set of buck stages;

FIG. 10B shows the combined output voltage of the ten buck stages whose output voltages are shown in FIG. 10;

fig. 10C shows the current through the inductor in the boost stage as an example of fig. 10A and 10B;

FIG. 11A shows the output voltages of a set of buck stages, where the output voltages are interleaved;

FIG. 11B shows the combined output voltage of the ten buck stages whose output voltages are shown in FIG. 11A;

fig. 11C shows the current through the inductor in the boost stage as an example of fig. 11A and 11B;

FIG. 12A shows the output voltages of a set of buck stages;

FIG. 12B shows the combined output voltage of the ten buck stages whose output voltages 1042 are shown in FIG. 12A;

fig. 12C shows the current through the inductor in the boost stage as an example of fig. 12A and 12B;

FIG. 13A shows the output voltages of a set of buck stages, where the output voltages are interleaved with each other but the duty cycles of the buck stages are different;

FIG. 13B shows the combined output voltage of the ten buck stages whose output voltages 1062 are shown in FIG. 13A;

fig. 13C shows the current through the inductor in the boost stage as an example of fig. 13A and 13B;

FIG. 14A is a diagram of a power generation system with a buck-boost optimizer, a PV module, and a solar inverter of an embodiment;

FIG. 14B is a flowchart of a process to operate a buck-boost optimizer, according to an embodiment;

FIG. 15 is an example processing unit that may be used in a power generation system.

Detailed Description

The present invention relates to techniques for providing power, voltage and/or current from a combination of DC sources. The DC source may be a power supply. In one embodiment, the DC source is a photovoltaic (e.g., solar) module. In one embodiment, the DC source is a DC battery. The techniques may be used in a power generation system.

In an embodiment, a buck-boost optimizer is provided having a plurality of inductor-less buck and boost stages. The buck-boost optimizer may be used in a power generation system. The combined output voltage of each buck stage may be input to the boost stage. The voltage increasing stage may have an inductor that may be used as an energy storage device to increase the voltage and filter the signal from the voltage decreasing stage. Thus, the buck-boost optimizer may use a single inductor. Using a single inductor can achieve a very efficient power generation system. Further, the cost and size of components in the power generation system may be reduced.

FIG. 1 is a diagram of a power generation system 100 having a buck-boost optimizer 110 connected to a DC power source 102, according to an embodiment. The buck-boost optimizer 110 has a plurality of buck stages 104 and boost stages 106. The buck-boost optimizer 110 may also be referred to herein as a buck-boost converter. The buck-boost converter 110 may also be referred to as a DC-DC converter. The buck-boost converter 110 may convert a DC input voltage to a DC output voltage. The buck-boost converter 110 may convert a DC input current to a DC output current.

Each buck stage 104 is associated with one of the DC power supplies 102. The DC power source 102 may be a photovoltaic (e.g., solar) module, a DC battery, or the like. Although three buck stages 104 are shown, the number of buck stages 104 may be more or less than three. Each buck stage 104 has an input connected to an output of the DC power supply 102. The inputs of each of the buck stages are labeled as a Vbk + terminal and a Vbk-terminal. Each buck stage 104 has outputs labeled Vbko + and Vbko-terminals. Each buck stage 104 may output a DC voltage across the Vout terminal. The buck stage 104 may be controlled such that the DC voltage at its output terminals (Vbko +, Vbko-) is less than the DC voltage at its input terminals (Vbki +, Vbki-).

In some embodiments, each buck stage 104 is of the non-inductor type. That is, in some embodiments, buck stage 104 does not have an inductor. The inductor-less buck stage 104 may transfer power from its DC power source more efficiently than a buck stage 104 with an inductor. The inductor-less buck stage 104 may also save cost relative to having an inductor in each buck stage 104. The inductor-less buck stage 104 may also be reduced in weight and/or size relative to having an inductor in each buck stage 104.

It is noted that although the positive input terminal of each buck stage 104 uses the same name (Vbki +), it is understood that the positive input terminal is not shorted. Likewise, while the negative input terminal of each buck stage 104 uses the same name (Vbki-), it should be understood that the negative input terminal is not shorted. Likewise, while the positive output terminal of each buck stage 104 uses the same name (Vbko +), it should be understood that the positive output terminal is not shorted. Likewise, while the negative output terminal of each buck stage 104 uses the same name (Vbko-), it should be understood that the negative output terminal is not shorted.

The buck-boost optimizer 110 also has a power regulation circuit 120. The power conditioning circuit 120 may be used to control each of the buck stages 104 to condition the power output of the respective DC power source 102. For example, if the DC power source 102 is a photovoltaic module, each buck stage 104 may be used to operate the photovoltaic module at or near maximum power point. In an embodiment, this may be accomplished by adjusting the DC voltage (e.g., VDC _ in) at the input terminals (Vbki +, Vbki-) of the buck stage 104. It is noted that a buck stage 104 is associated with each DC power source 102, respectively, such that the power output of each DC power source 102 can be controlled independently of the other DC power sources 102. Thus, the power output of each DC power source can be efficiently regulated.

The boost stage 106 has inputs labeled as terminals Vbsti + and Vbsti-. These input terminals receive the combined output voltage of the buck stage 104. Thus, the voltage boost stage 106 is connected to the voltage buck stage 104 to receive the combined output voltage of the voltage buck stage 104. In addition, the buck stages 104 are interconnected such that a current called "Iseries" is provided from the buck stage 104 to the boost stage 106. This current may be processed by filter 108 in boost stage 106.

The voltage boosting stage 106 also has output terminals Vbsto + and Vbsto-, which provide a voltage referred to as VDC _ Y. The boost stage 106 may be used to boost the voltage at its input terminals (Vbsti +, Vbsti-) to generate a boosted voltage at its output terminal. In one embodiment, filter 108 is used as an energy storage device when boosting. The filter may be configured to store energy from a signal on the boost stage input terminal and to transfer the energy to the boost stage output terminal. In one embodiment, the filter 108 is an inductor.

As described above, the buck stage 104 may be of the non-inductor type. Thus, the buck-boost optimizer 110 may use a single inductor (e.g., filter 108). The use of a single inductor in the buck-boost optimizer 110 enables efficient power transfer of power from the DC power source 102 to the output of the boost stage 106.

Further, it is noted that the filter 108 (e.g., an inductor) may serve a dual purpose in the buck-boost optimizer 110. One of which is that the current "Iseries" from the buck stage 104 can be filtered. It is noted that the output current of the buck stage 104 may have some ripple. The filter 108 may facilitate the removal of some of the ripple. In addition, the filter 108 (e.g., an inductor) may be used as an element to facilitate boosting the voltage at the input of the boost stage 106.

Fig. 2A is a diagram of buck-boost optimizer 110 of an embodiment. The buck-boost optimizer 110 has a plurality of buck stages 104(1) through 104(n) and a boost stage 106. The buck-boost optimizer 110 of fig. 2A may also be used with the power generation system 100 of fig. 1.

Each of the buck stages 104 has an input capacitor 112 and two switches. Each of the buck stages 104 is of an inductor-less type. The input capacitance 112 is connected across the input terminals Vbki +, Vbki-. It is noted that the input terminals Vbki +, Vbki-may be connected across a DC power supply, such as a photovoltaic module. However, the DC power supply is not shown in fig. 2A. The input capacitance 112 may be used as an energy storage device to enable at least partial operation of the buck stage 104. Buck stage 104(1) has switches S11 and S12, buck stage 104(2) has switches S21 and S22, and buck stage 104(n) has switches Sn1 and Sn 2. In one embodiment, the switches S11, S21, … …, Sn1 may be open and closed. As shown, the switches S11, S21, … …, Sn1 have a switching element 226 and a diode 228 in parallel with the switching element. The switching element 226 may be implemented by a transistor. A diode 228 in parallel with the switching element 226 is optional. As shown, the switches S12, S22, … …, Sn2 have a switching element 226 and a diode 228 in parallel with the switching element 226. In one embodiment, the switches S12, S22, … …, Sn2 may be open and closed. However, the switches S12, S22, … …, Sn2 may be replaced by circuit elements that do not open and close. For example, one option is to replace the switches S12, S22, … …, Sn2 with rectifiers such as diodes. At this time, the anode and cathode of the diode 228 may be connected to output terminals (Vbko +, Vbko-), as shown in fig. 2A. Fig. 2B-2D illustrate in further detail the electronic components that may implement the switches in the buck stage 104.

Consistent with the description of fig. 1, the positive input terminal of each of the buck stages 104(1) through 104(n) uses the same name (Vbki +). However, it should be understood that the positive input terminal (Vbki +) is not shorted. Likewise, while the negative input terminal of each buck stage 104(1) through 104(n) uses the same name (Vbki-), it is understood that the negative input terminal is not shorted. Likewise, while the positive output terminal of each buck stage 104(1) through 104(n) uses the same name (Vbko +), it is understood that the positive output terminal is not shorted. Likewise, while the negative output terminal of each buck stage 104(1) through 104(n) uses the same name (Vbko-), it is understood that the negative output terminal is not shorted.

In one embodiment, the buck stage 104(1) operates as follows. The operation of the other buck stages 104(2) to 104(n) is similar for the corresponding switches. In one embodiment, the operation of the buck stage 104(1) includes two stages. The two phases may be divided based on whether switch S11 is open or closed. The relative proportion of time spent at each stage may be referred to as the duty cycle. In other words, the duty cycle may be defined as the proportion of time it takes to close/open switch S11. In one embodiment, when switch S11 is open, S12 is closed; when the switch S11 is closed, S12 is open. It is noted, however, that the switching element 226 of switch S12 may be open during operation, with switch S12 actually acting as a rectifier. Therefore, the switch S12 may be replaced by a diode without any switching element (e.g., a transistor). It is noted that the term "duty cycle" may generally apply to the switch S11 or the buck stage 104 (1). Hence, this may refer to the duty cycle of the buck stage 104(1) or the duty cycle of the switch S11.

Opening switch S11 may cause the DC power source (e.g., photovoltaic module) to charge the input capacitance 112. Closing switch S11 may cause current to flow from the input capacitor 112 (and possibly from the DC power supply) to the output of the buck stage 104 (1). The duty cycle may determine how much energy the input capacitance 112 and DC power source provide. In one embodiment, the duty cycle of switch S11 is controlled to regulate the power output of the DC power source. For example, the duty cycle of switch S11 may be established to operate the photovoltaic module at the maximum power point (or at least attempt to maximize the power output of the photovoltaic module).

The boost stage 106 includes an inductor 208, an output capacitor 114, a switch S1, and a switch S2. The inductor 208 is an example of the filter 108 in fig. 1. Switches S1 and S2 are shown as switching element 226 with parallel diode 228. The diode 228 is not necessary. The switches S1 and S2 may include transistors to implement the switching element 226. The switch S1 may have a diode 228 in parallel with the switching element 226, but the diode 228 is not required. In one embodiment, switch S2 may be open and closed. Accordingly, the switch S2 may have a transistor that can be turned on and off to implement the switching element 226. However, the switch S2 may be replaced by a circuit element (e.g., a diode) that acts as a rectifier. Therefore, the switching element 226 is not necessary in the switch S2. Fig. 2B to 2D are described in further detail.

In one embodiment, the boost stage 106(1) operates as follows. The boost stage 106 may operate between a bypass mode and a boost mode. In one embodiment, for the bypass mode, switch S2 is closed and S1 is open. In the bypass mode, the voltage VDC _ x is delivered to the output capacitor 114. Thus, in the bypass mode, VDC _ y is substantially equal to VDC _ x. It should be noted that some non-ideal characteristics may exist for the circuit elements. For example, there may be some resistance along the conductive path. Therefore, the output voltage is not necessarily exactly equal to the input voltage. It should therefore be understood that the term "substantially equal" is used in this context, taking into account the non-ideal characteristics of the circuit components.

The boost stage 106 may operate in what may be referred to as a boost mode. In the boost mode, the input voltage (VDC _ X) may be less than the output voltage (VDC _ Y). In other words, the output voltage (VDC _ Y) may be greater than the input voltage (VDC _ X). In one embodiment of the boost mode, switches S1 and S2 are turned on and off. In an embodiment, the boost mode has a first phase in which switch S1 is closed and switch S2 is open; and a second phase in which switch S1 is open and switch S2 is closed. The duty cycle of the boost stage 106 may be defined by the percentage of time that the switch S1 is closed. Note that the bypass mode may be considered to have a duty cycle of 0% (e.g., switch S1 is always open and switch 2 is always closed).

When switch S1 is closed and switch S2 is open, energy may be stored in the inductor 208. When switch S1 is open and switch S2 is closed, the energy stored in the inductor 208 may be transferred to the output capacitor 114. In general, a higher duty cycle of the voltage boosting stage 106 may result in a lower voltage (VDC _ X) at the input terminals (Vbist +, Vbist-) of the voltage boosting stage 106.

Fig. 2A shows a plurality of switches in the buck stage 104 and the boost stage 106. Fig. 2B-2D illustrate various embodiments of electrical components that may be used in the circuit of fig. 2A. As shown in the depiction of fig. 2A, the switch may or may not have a diode 228 in parallel with a switching element 226, such as a transistor. Fig. 2B is an embodiment in which the switch comprises a transistor 226a and a diode 228a in parallel with said transistor 226 a. The transistor 226a may be used as the switching element 226. The circuit of fig. 2B may be used for any of the switches of fig. 2. The diode 228a may have its anode and cathode arranged as the diode 228 of the switch in fig. 2A.

Fig. 2C shows an embodiment in which each switch includes a transistor 226 b. However, the switch does not include a diode in parallel with transistor 226 b. The circuit of fig. 2C may be used for any of the switches of fig. 2A.

As shown in the description of fig. 2A, the switches S12, S22, … …, Sn2 may be replaced by, for example, rectifying elements. Furthermore, the switch S2 in the voltage boosting stage 106 may be replaced by a rectifying element, for example. Fig. 2D shows an embodiment of a rectifying element that may be used in place of the switches S12, S22, … …, Sn2 in the buck stage 104. Likewise, the rectifying element may be used in place of switch S2 in the voltage boost stage 106. In this embodiment, the rectifying element is a diode 228 b. The diode 228b may have its anode and cathode set as the diode 228 of the switches S12, S22, … …, Sn2 in fig. 2A. The diode 228b may have its anode and cathode arranged as the diode 228 in the switch S2 in the voltage boost stage 106.

The description will now continue with the embodiments of the power generation system (also referred to as a photovoltaic power system) of fig. 2E, 3, 4, 5, 6, 7, and 8 including at least one buck-boost optimizer 110. Those of ordinary skill in the art will appreciate that aspects of buck-boost optimizer 110 in fig. 2A may be applied to buck-boost optimizer 110 in fig. 2E, 3, 4, 5, 6, 7, and 8. Accordingly, the common points of the circuit elements and their operation are not described.

Fig. 2E is a diagram of an embodiment of a power generation system 200 with a buck-boost optimizer 110 (note that this and other power generation systems with photovoltaic modules described herein may also be referred to as photovoltaic power generation systems). The system 200 has a plurality of photovoltaic modules 202(1) through 202 (n). Each photovoltaic module 202(1) to 202(n) is an example of a DC power supply. The output of each opto-electronic module 202 is connected to the input terminal of one of the buck stages 104. Each buck stage 104 may be operated to regulate the power output of its photovoltaic module. For example, the buck stage 104 may be used to operate the optoelectronic module 202 at a maximum power point, or at least attempt to maximize the power output of the optoelectronic module 202.

The photovoltaic power system 200 has a solar inverter 204. The solar inverter may also be referred to as a DC-AC converter. The input terminals (Vsii +, Vsii-) of the solar inverter 204 are connected to the output terminals (Vtsto +, Vtsto-) of the boost stage 106. In one embodiment, the solar inverter 204 is used to regulate the voltage at its input terminals. For example, the solar inverter 204 may be used to attempt to maintain its input voltage at some target voltage. The solar inverter 204 is used to convert the DC voltage at its input to an AC voltage. The solar inverter 204 outputs an AC Voltage (VAC) to its output terminals (Vsio +, Vsio-).

It is noted that although capacitor 114 is shown as part of boost stage 106 in fig. 2E, in one embodiment, capacitor 114 is in solar inverter 204. In one embodiment, the entire boost stage 106 is within the solar inverter 204.

Fig. 2F is a diagram of a power generation system (or photovoltaic power system) 250 having a buck-boost optimizer 110 of another embodiment. The system 250 is similar to the system 200 in FIG. 2E, but the buck stage 104 is constructed somewhat differently. In the embodiment of fig. 2F, the switches S11, S12, … …, Sn1 are in different positions than in the embodiment of fig. 2E. In fig. 2F, switches S11, S12, … …, Sn1 are located between the negative input terminal (Vbki-) of the buck stage 104 and the anode side of the diodes in switches S12, S22, … …, Sn2, respectively. Referring again to fig. 2E, switches S11, S12, … …, Sn1 are located between the negative input terminal of the buck stage 104 and the cathode side of the diodes in switches S12, S22, … …, Sn2, respectively.

It is noted that the inputs (Vbki +, Vbki-) of the buck stages 104 may be connected to the photovoltaic components in a variety of ways. In an embodiment, the inputs (Vbk +, Vbk-) of the buck stage 104 span the entire photovoltaic panel. In other words, in an embodiment, the input terminals (Vbk +, Vbk-) of the buck stage 104 span a single photovoltaic panel. Some photovoltaic panels may have multiple dc outputs. For example, there may be multiple sets of output terminal pairs. At this time, a separate buck stage 104 may be connected to each of the DC outputs. Thus, in an embodiment, the inputs (Vbk +, Vbk-) of buck stage 104 span across a sub-string of the photovoltaic panel. In some cases, the buck stage 104 may be connected to a string of photovoltaic panels. The photovoltaic panels in the string may have their output ends connected in series to form the string. However, the buck stage input (Vbki +) may be connected to the DC output of the photovoltaic panel at one end of the string and the buck stage input (Vbki-) may be connected to the DC output of the photovoltaic panel at the other end of the string. Thus, in an embodiment, the input terminals (Vbk +, Vbk-) of the buck stage 104 span across multiple photovoltaic panels in series.

Fig. 3 is a diagram of a photovoltaic power system 300 with a buck-boost optimizer, under an embodiment. The system 300 has a plurality of voltage reduction modules 304(1), 304(2), … …, 304 (n). The number of buck modules 304 may be more or less than three. Details of the buck modules 304(2), … …, 304(n) are not shown, but may be similar to the buck module 304 (1). The circuitry within the buck module 304(1) in this example is similar to the circuitry in the buck stages 104(1), (… …), and 104(n) in FIG. 2E. Further, the positive output terminal (Vbko +) is connected to the positive input terminal (Vbsti +) of the boosting stage 106. The difference is that the negative output terminal (Vbko-) of the buck stage 104(n) in the buck module 304(1) is not connected to the negative terminal (vbstis-) of the boost stage 106. Conversely, the negative output terminal (Vbko-) of the buck stage 104(n) in the buck module 304(1) is connected to the positive output terminal (Vbko +) of the buck stage 104(1) in the buck module 304 (2). It is noted that the buck stage 104(1) of the buck module 304(2) is not shown in fig. 3. Conversely, the reference "a" is used to denote the positive output terminal (Vbko +) of the buck stage 104(1) in each buck module 304. Further, reference numeral "B" is used to denote the negative output terminal (Vbko-) of the buck stage 104(n) in each buck module 304. Therefore, it is noted that the negative output terminal (Vvbko-) of the buck stage 104(n) is connected to the negative terminal (Vbist-) of the boost stage 106. Thus, the boost stage input terminals (Vbist +, Vbist-) are connected across the combined outputs of all of the buck stages 104 of all of the buck modules 304. In the system 300, the buck-boost optimizer 110 includes a buck stage 104 and a boost stage 106 of multiple buck modules 304(1) through 304 (n).

Fig. 4 is a diagram of a photovoltaic power system 400 having another configuration of voltage-reduction modules. In the embodiment of fig. 4, each buck module 404 has an inductor 408 and an output capacitance 412. The inductor 408 has one terminal connected to the positive output terminal Vbko + of the buck stage 104(1) and the other terminal connected to the positive input terminal Vbsti + of the boost stage 106. One terminal of the output capacitor 412 is connected to the positive input terminal Vbsti + of the voltage boosting stage 106 and the other terminal is connected to the negative output terminal Vbko-of the voltage dropping stage 104 (n). The inductor 408 may be used to filter the output signal (current and/or voltage) of the buck module 404.

The voltage boost stage 106 in fig. 4 may have a bypass switch S3. An optional diode 414 is connected in parallel with the bypass switch S3. The bypass switch S3 may be used to bypass the entire boost stage 106, including the inductor 108. One of the inductors 408 in the buck module 404 functions to filter the output signal of the buck module 404 while bypassing the inductor 108 in the boost stage 106.

The labels "C" and "D" are used in fig. 4 to show how the buck stages 104 of adjacent buck modules 404 are connected. The reference "C" is located at the terminal of the inductor 408 not connected to the positive output terminal Vbko + of the buck stage 104 (1). The reference numeral "D" is located at the negative output terminal Vbko-of the buck stage 104 (n). Thus, the input terminal of the boost stage 106 is connected across the output capacitors 412 of the buck modules 404(1) through 404 (n).

In system 400, buck-boost optimizer 110 includes a buck stage 104 and a boost stage 106 of a plurality of buck modules 404(1) through 404 (n).

Fig. 5 illustrates an embodiment of a photovoltaic power system 500 in which there is more than one voltage boost stage 106. In addition, there are multiple buck-boost optimizers 110. The system 500 has a plurality of buck-boost modules 504(1) through 504 (n). Buck-boost module 504(1) has buck-boost optimizer 110 connected to PV module 302. Each PV module 302 is connected to one buck stage 104. The positive input terminal Vbsti + of the boost stage 106(a) is connected to the positive output terminal Vbko + of the buck stage 104 (1). The negative input terminal Vbsti-of the voltage boosting stage 106(a) is connected to the negative output terminal Vbko-of the voltage dropping stage 104 (n).

The labels "E" and "F" are used in fig. 5 to illustrate how the optimizers 110 of adjacent buck-boost modules 504 are connected. The reference "E" is located at the positive output terminal Vbsto + of the voltage boosting stage 106 (a). The label "F" is located at the negative terminal Vbsto-of the voltage boosting stage 106 (a). In the embodiment of fig. 5, multiple buck-boost optimizers 110 are connected in series within photovoltaic power system 500.

It is noted that in system 500, the boost stage 106(a) in buck-boost optimizer 110 is not directly connected to solar inverter 204. Instead, the system 500 has another voltage boosting stage 106(b) whose output terminals are connected to the solar inverter 204. The input terminal of the boost stage 106(b) is connected across a series of output capacitors 412 of the boost stage 106(a) of the buck-boost modules 504(1) through 504 (n).

Fig. 6 illustrates an embodiment of another photovoltaic power system 600 in which there are multiple voltage boosting stages 106. In addition, there are multiple buck-boost optimizers 110. In the embodiment of fig. 6, multiple buck-boost optimizers 110 are connected in series within photovoltaic power system 600. Unlike the system in fig. 5, the boost stage in the system 600 of fig. 6 does not correspond to the boost stage 106(b) in the system 500. The system 600 has a capacitance 612 connected across the input terminals (Vsii +, Vsii-) of the solar inverter 402. One terminal of capacitor 612 is connected to the positive output terminal Vbsto + of boost stage 106 in buck-boost module 504 (1). The other terminal of the capacitor 612 is connected to the negative output terminal Vbsto-of the boost stage 106 in the buck-boost module 504 (n). Thus, the capacitor 612 spans across the series of output capacitors 114 in the boost stage 106 of all buck-boost modules 504. It is noted that the capacitor 612 may be integrated within the solar inverter 402.

Figures 3 to 6 show various series connections of modules that may be referenced which may increase the combined voltage of the PV modules by allowing more PV modules to be connected. Parallel connections of modules may also be formed to provide more current. Fig. 7 illustrates an embodiment of a photovoltaic power system 700 with series and parallel connection of modules. The modules in system 700 may be similar to the modules in system 600. In system 700, modules 504(1, 1), 504(2, 1), and 504(n, 1) are connected in series in a manner similar to modules 504(1), (504), (2), and 504(n) in system 600. There are multiple "strings" (string 1, string 2, and string m) of such series-connected buck-boost modules 504 in the system 700.

In system 700, the modules 504(1, 2), 504(2, 2), and 504(n, 2) are connected in series in a manner similar to modules 504(1), (504), (2), and 504(n) in system 600. In system 700, the modules 504(1, m), 504(2, m), and 504(n, m) are connected in series in a manner similar to modules 504(1), (504), (2), and 504(n) in system 600. There may be more or less than these three strings. The buck-boost optimizers 110 at the top of each string are connected together and are referred to herein as being connected in parallel. In particular, the positive output terminals Vbsto + of the boost stages 106 in buck-boost modules 504(1, 1), 504(1, 2), and 504(1, m) are connected together. This point is also connected to the positive input terminal Vsii + of the solar inverter 402. The buck-boost optimizers 110 at the bottom of each string are connected together and are referred to herein as being connected in parallel. In particular, the negative output terminals Vbsto of the boost stages 106 in buck-boost modules 504(n, 1), 504(n, 2) and 504(n, m) are connected together. This point is also connected to the negative input terminal Vsii-of the solar inverter 402. In the embodiment of fig. 7, multiple buck-boost optimizers 110 are connected in series and multiple buck-boost optimizers 110 are connected in parallel within photovoltaic power system 700.

Thus, the input terminals of the solar inverter 402 are connected across the series-connected output capacitors 114 of the voltage boost stages 106 in string 1. Likewise, the input terminals of the solar inverter 402 are connected across the series-connected output capacitors 114 of the boost stages 106 in string 2. Likewise, the input terminals of the solar inverter 402 are connected across the series-connected output capacitors 114 of the boost stages 106 in string m.

Furthermore, each string is capable of providing its own string current. Thus, string 1 provides the string current, string 2 provides the string current, and string m provides the string current. These three string currents may be added to increase the amount of current provided by the system 700 to the solar inverter 402.

Fig. 8 illustrates an embodiment of another photovoltaic power system 800 in which there are multiple buck-boost modules 504 connected together. System 800 differs from system 700 in that there is a boost stage 106(d) between solar inverter 402 and the set of buck-boost modules 504. The positive output terminal Vbsto + of the boost stage 106d is connected to the positive input terminal Vsii + of the solar inverter 402. The negative output terminal Vbsto-of the boost stage 106d is connected to the negative input terminal Vsii-of said solar inverter 402.

The positive output terminals Vbsto + of the boost stages 106c in the buck-boost modules 504(1, 1), 504(1, 2) and 504(1, m) are connected together. This point is also connected to the positive input terminal Vbsti + of the boost stage 106 d. The negative output terminals Vbsto of the boost stages 106c in the buck-boost modules 504(n, 1), 504(n, 2) and 504(n, m) are connected together. This point is also connected to the negative input terminal Vbsti-of the voltage boosting stage 106 d. In the embodiment of fig. 8, multiple buck-boost optimizers 110 are connected in series and multiple buck-boost optimizers 110 are connected in parallel within photovoltaic power system 800.

The power generation systems in fig. 2E, 2F, 3, 4, 5, 6, 7 and 8 each have at least one buck-boost optimizer 110. These switches are shown in buck-boost optimizer 110 of fig. 2E, 2F, 3, 4, 5, 6, 7, and 8 in a manner similar to the switches of buck-boost optimizer 110 of fig. 2A. Those of ordinary skill in the art will appreciate that the description of the circuit elements in fig. 2B, 2C, and 2D applies to the buck-boost optimizer 110 in fig. 2E, 2F, 3, 4, 5, 6, 7, and 8. Thus, the switches in buck-boost optimizer 110 shown in fig. 2E, 2F, 3, 4, 5, 6, 7, and 8 may be implemented by circuit elements in fig. 2B, 2C, and 2D similar to buck-boost optimizer 110 of fig. 2A.

FIG. 9 is a flow diagram of a process 900 to operate a buck-boost optimizer of an embodiment. The process 900 may be used to operate any of the buck-boost optimizers of fig. 1, 2A, 2E, 2F, 3-8, but is not limited to such. Step 902 includes receiving a DC voltage from each of a plurality of photovoltaic modules at a corresponding plurality of inductor-less buck stages.

Step 904 includes operating each of the plurality of inductor-less buck stages to regulate a power output of a corresponding photovoltaic module. Step 904 may include generating an output voltage for each buck stage 104. Step 904 may include generating an output current for a set of buck stages 104. In one embodiment, an output current is generated for a series of buck stages. Step 904 may include running each buck stage independently of each other to independently control pulse width modulation of the buck stage. Step 904 may include operating each photovoltaic module at a maximum power point, or at least attempting to maximize the power output of each photovoltaic module.

Step 906 includes receiving a combined output voltage from all of the plurality of buck stages at an input of the boost stage. Referring to fig. 2A, 2E and 2F, the voltage boost stage 106 receives the combined output voltage from the voltage buck stages 104(1) to 104 (n). Referring to fig. 3, the voltage boost stage 106 receives a combined output voltage from the voltage buck stage 104(1) to 104(n) of each of the voltage buck modules 304(1) to 304 (n). Referring to fig. 4, the voltage boost stage 106 receives a combined output voltage from the voltage buck stage 104(1) to 104(n) of each of the voltage buck modules 404(1) to 404 (n). Referring to fig. 5, the boost stage 106a in the buck-boost module 504 receives the combined output voltage from the buck stages 104(1) through 104(n) in the buck-boost module 504. Referring to fig. 6, the boost stage 106 in the buck-boost module 504 receives the combined output voltage from the buck stages 104(1) through 104(n) in the buck-boost module 504. Referring to fig. 7, the boost stage 106 in the buck-boost module 504 receives the combined output voltage from the buck stages 104(1) through 104(n) in the buck-boost module 504. Referring to fig. 8, the boost stage 106(c) in the buck-boost module 504 receives the combined output voltage from the buck stages 104(1) through 104(n) in the buck-boost module 504.

Step 908 includes operating the voltage increasing stage to increase the combined output voltage from the voltage decreasing stage. Step 908 may include controlling the duty cycle of the boost stage 106. Step 908 may include reducing the voltage at the input terminal of the voltage boost stage relative to the voltage at the output terminal of the voltage boost stage 106.

Step 910 includes providing the boosted voltage to the solar inverter.

In some embodiments, the output voltages of the buck stages 104 are interleaved with each other. Interleaving the output voltage may reduce ripple in inductor 108 in the boost stage 106. Fig. 10A to 13C show various signals for convenience of explanation.

Fig. 10A shows the output voltages of a set of buck stages. In this example, the individual output voltages 1002(1) through 1002(10) of the ten buck stages are shown. In this example, all buck stages currently have the same duty cycle. The duty ratio is reflected by the high level and the low level of each of the output voltages 1002(1) to 1002 (10). Furthermore, the buck stages are synchronized, which means that they operate at the same frequency. In other words, the output voltages 1002 have the same period. One cycle between times t0 and t1 and a second cycle between times t1 and t 2. Also, the output voltages 1002(1) to 1002(10) are not interleaved. For each output voltage 1002(1) to 1002(10), pulses start simultaneously (e.g., t0, t1, and t 2). Because the duty cycle of each buck stage is the same, the pulses end at the same time for each output voltage 1002(1) through 1002 (10).

Fig. 10B shows the combined output voltage of the ten buck stages whose output voltages 1002 are shown in fig. 10A. Since output voltages 1002(1) through 1002(10) are not interleaved, output voltage 1004 varies between a very low value and a very high value. For example, the low value may be 0V and the high value may be 200V.

Fig. 10C shows the current through inductor 108 in boost stage 106 as an example of fig. 10A and 10B. Since the output voltages 1002(1) through 1002(10) are not interleaved, the current may vary significantly between the lower and upper points. For example, the current may vary between about 9.5A and 10.5A. Thus, the range between the maximum current and the minimum current may be about 1A.

Fig. 11A shows the output voltages of a set of buck stages, where the output voltages are interleaved with each other. In this example, the individual output voltages 1022(1) to 1022(10) of ten buck stages are shown. In this example, all buck stages currently have the same duty cycle. The duty ratio is reflected by the high level and the low level of each of the output voltages 1022(1) to 1022 (10). Furthermore, the buck stages are synchronized, which means that they operate at the same frequency. However, unlike the example of fig. 10A, the output voltages 1022(1) to 1022(10) are interleaved with each other. For each output voltage 1022(1) to 1022(10), the pulse starts at a different point in time.

Fig. 11B shows the combined output voltage of the ten buck stages whose output voltages 1022 are shown in fig. 11A. Since the output voltages 1022(1) to 1022(10) are interleaved with each other, the amplitude of variation of the output voltage 1024 is not as large as in the example of fig. 10B. For example, the low value may be 190V and the high value may be 210V.

Fig. 11C shows the current through inductor 108 in boost stage 106 as an example of fig. 11A and 11B. Since the output voltages 1022(1) to 1022(10) are interleaved with each other, the current does not significantly vary between the lower point and the upper point. For example, the current may vary between about 9.965a and 9.98A. Thus, the range between the maximum current and the minimum current may be about 0.015A.

Fig. 10A to 11C show the case where the buck stages have the same duty ratio. Fig. 12A to 13C show the case where the buck stages have different duty ratios. It is noted that to maximize the power output of each photovoltaic module, it may be desirable to operate the respective buck stages at different duty cycles. One of the reasons that various photovoltaic modules may need to operate differently is that various photovoltaic modules may receive different amounts of sunlight due to shadows, etc.

Fig. 12A shows the output voltages of a set of buck stages. In this example, the individual output voltages 1042(1) to 1042(10) of the ten buck stages are indicated. In this example, the various buck stages have different duty cycles. The duty ratio is reflected by the high level and the low level of each of the output voltages 1042(1) to 1042 (10). Furthermore, the buck stages are synchronized, which means that they operate at the same frequency. Also, the output voltages 1042(1) to 1042(10) are not interleaved.

Fig. 12B shows the combined output voltage of the ten buck stages whose output voltages 1042 are shown in fig. 12A. Since the output voltages 1042(1) to 1042(10) are not interleaved and the buck stages have different duty cycles, the output voltage 1044 varies between a very low value and a very high value. For example, the low value may be 0V and the high value may be 250V. Note that this difference may be greater than if the buck stage in fig. 10B had the same duty cycle.

Fig. 12C shows the current through inductor 108 in boost stage 106 as an example of fig. 12A and 12B. Since the output voltages 1042(1) to 1042(10) are not interleaved and the buck stages have different duty cycles, the current may vary significantly between a lower point and an upper point. For example, the current may vary between about 8.5A and 9.5A. Thus, the range between the maximum current and the minimum current may be about 1A.

Fig. 13A shows the output voltages of a set of buck stages, where the output voltages are interleaved but the duty cycles of the buck stages are different. In this example, the respective output voltages 1062(1) to 1062(10) of the ten buck stages are indicated. In this example, the various buck stages have different duty cycles. The duty ratio is reflected by the high level and the low level of each of the output voltages 1062(1) to 1062 (10). Furthermore, the buck stages are synchronized, which means that they operate at the same frequency. However, unlike the example of fig. 12A, the output voltages 1062(1) to 1062(10) are interleaved with each other.

Fig. 13B shows the combined output voltage of the ten buck stages whose output voltages 1062 are shown in fig. 13A. Since output voltages 1062(1) through 1062(10) are interleaved, output voltage 1064 does not vary as much between high and low values (relative to fig. 12B) despite the different duty cycles. For example, the low value may be 80V and the high value may be 180V. Note that this difference may be less than if the buck stage outputs in fig. 12B were not interleaved.

Fig. 13C shows the current through inductor 108 in boost stage 106 as an example of fig. 13A and 13B. Since the output voltages 1062(1) to 1062(10) are interleaved with each other, the current variation may be smaller than the example of fig. 12B. For example, the current may vary between about 8.8A and 9.1A. Thus, the range between the maximum current and the minimum current may be about 0.3A.

Fig. 14A is a diagram of a photovoltaic power system with buck-boost optimizer 110, PV module 202, and solar inverter 204 of an embodiment. The power conditioning circuit 120 has a sampling circuit 1420 and a duty cycle selection element 1430. The sampling circuit 1420 is used to sample a signal (e.g., current and/or voltage) at the output of the PV module 202. The duty cycle selection element 1430 is used to select a duty cycle for each of the buck stages 104. The duty cycle of each buck stage 104 may be based on the signal sampled from the corresponding PV module 202. In one embodiment, the power regulation circuit 120 is configured to control the duty cycle of each buck stage to regulate the power output of the corresponding PV module 202. The power conditioning circuit 120 may be implemented by a combination of hardware and/or software. Processing unit 1500 in fig. 15 may be used to implement at least a portion of the power regulating circuit 120.

The duty cycle selection element 1430 is also used to select the duty cycle of the operating voltage boost stage 106. In an embodiment, the duty cycle selection element 1430 is used to operate the boost stage 106 in a boost mode or a bypass mode. The power conditioning circuit 120 may be responsive to a signal from the solar inverter 204 to determine whether to operate the boost stage 106 in a boost mode or a bypass mode. The power conditioning circuit 120 may be responsive to a signal from a buck stage 104 to determine whether to operate the boost stage 106 in a boost mode or a bypass mode. One embodiment is further described in conjunction with the process shown in FIG. 14B.

FIG. 14B is a flowchart of a process 1400 to operate buck-boost optimizer 110, under an embodiment. The process 1400 will be described with reference to the system in FIG. 14A, but the process 1400 is not limited to the system. Step 1402 includes monitoring signals at the output of each photovoltaic module. For example, the current and/or voltage at the DC output of each PV module 202 may be sampled by a sampling circuit 1420.

Step 1404 includes controlling a duty cycle of the buck stage to regulate a power output of the corresponding PV module. The process 1400 is not limited to any particular technique for regulating the power output of the PV module. In some embodiments, both step 1402 and step 1404 are used simultaneously to attempt to run each PV module at the maximum power point. In one example, hill climbing techniques may be used in steps 1402-1404. One example of a hill climbing technique is commonly referred to as "perturb observation". In perturbation observation, the power regulation circuit 120 may slightly adjust the duty cycle of a given buck stage 104 and observe the effect on the current and voltage (i.e., power) output by the corresponding PV module. This adjustment may be made until the maximum power point is found. Since environmental conditions (e.g., solar radiation, operating temperature, etc.) may change over time, the power conditioning circuit 120 may again look for a maximum power point at certain periodic intervals. Many other techniques may be used in addition to perturb observations. Step 1404 may include the duty cycle select element 1430 sending a control signal to each of the buck stages 104. The control signal may indicate when the switches S11 and S12 in the buck stage 104(1) are open and closed. Similar control signals may be sent to the other buck stages 104(2) to 104 (n). In one embodiment, the control signal simply indicates when switch S11 is open and closed (since switch S12 may be implemented by a diode that does not contain an active switch).

Step 1406 includes determining whether the boost stage 106 should be operated in a boost mode or a bypass mode. In boost mode, the voltage at the input terminals (e.g., Vbist + and Vbist-) of the boost stage 106 is less than the voltage at the output terminals (e.g., Vtsto + and Vtsto-) of the boost stage 106. In bypass mode, the voltage at the input terminals (e.g., Vbist + and Vbist-) is substantially the same as the voltage at the output terminals (e.g., Vtsto + and Vtsto-). By "substantially the same" is meant that the voltages at the input and output terminals are the same, but that there may be some difference in the input and output voltages due to some non-idealities that may exist with the circuit elements. For example, there may be some resistance along the conductive path between the input and output of the voltage boost stage 106. There may be a voltage drop between the input and the output of the boost stage 106.

Various techniques may be used to determine whether boost stage 106 of buck-boost optimizer 110 should operate in boost mode or bypass mode. In an embodiment, the solar inverter 204 determines whether it is difficult to maintain the voltage at its input terminals (e.g., Vsii + and Vsii-). It is noted that the solar inverter 204 may be used to attempt to regulate the voltage at its input terminals (e.g., Vsii + and Vsii-) to some target voltage, such as 350V. If the solar inverter 204 is unable to maintain the voltage at its input terminals (e.g., Vsii + and Vsii-) at the target voltage, the solar inverter may not operate efficiently and/or may not be able to provide the appropriate AC voltage at its output terminals (e.g., Vsio + and Vsio-). Thus, in an embodiment, when the solar inverter 204 has difficulty maintaining a voltage at its input terminals (e.g., Vsii + and Vsii-), the solar inverter 204 sends a signal to the power conditioning circuit 120. In one embodiment, when it is determined that the DC voltage at the input of the solar inverter 204 (or DC-AC converter) does not satisfy a discrimination condition, in response, the power conditioning circuit 120 determines that the boost stage 106 should be operated in the boost mode.

In an embodiment, the power conditioning circuit 120 determines that the boost stage 106 should be operated in the boost mode in response to some condition of the buck stage 104. In an embodiment, the power conditioning circuit 120 determines that the combined output voltage of the buck stage 104 needs to fall below the current input voltage of the boost stage 106 to maintain the target duty cycle of the buck stage. For example, to maintain a target power efficiency, at least a portion of the buck stage may need to operate at a substantially high duty cycle. This means that the combined output voltage of the buck stage may need to fall below the current input voltage of the boost stage.

In response to determining in step 1406 that the voltage boost stage 106 should be operated in a boost mode, the duty cycle of the voltage boost stage 106 is controlled in step 1408 to provide a target input voltage for the voltage boost stage 106. In one embodiment, the power regulation circuit 120 sends a control signal to the boost stage 106 to control the duty cycle of the boost stage 106. The control signal may indicate when the switches S1 and S2 are open and closed.

In response to determining in step 1406 that the boost stage 106 should be operated in a bypass mode, the boost stage 106 is operated in a bypass mode in step 1410. In an embodiment, the power regulation circuit 120 sends a control signal to the boost stage 106 to indicate a bypass mode. In one embodiment, the bypass mode is selected by keeping switch S1 always open and switch S2 always closed.

In one embodiment, the boost stage 106 has circuit elements that allow the inductor 108 to be bypassed. In conjunction with fig. 4, switch S3 allows the inductor 108 (and switch S2) to be bypassed. Thus, in one embodiment, switch S3 is closed and switch S2 is open in the bypass mode. Closing switch S3 may connect the positive input terminal (Vbsti-) to the positive output terminal (Vbsto +).

Fig. 15 is an example processing unit 1500. A particular device (e.g., buck-boost optimizer 110, solar inverter 204, etc.) may use all of the components shown, or only a subset of the components, and the degree of integration between devices may vary. In an embodiment, all or part of power conditioning circuit 120 is implemented by processing unit 1500. In addition, a device may contain multiple instances of a component, such as multiple processing units, processors, memories, transmitters, receivers, and so forth. The processing unit 1500 may include one or more input/output (I/O) devices 1560, a Central Processing Unit (CPU) 1552, a memory 1556, an auxiliary storage device 1554, and a network interface 1562.

The CPU 1552 may include any type of electronic data processor. The CPU 1552 may be used to implement aspects described herein, such as the process 1400 shown in fig. 14B. The CPU 1552 may be used to implement the selection steps in the process 900 of fig. 9. For example, the CPU 1552 may be configured to implement steps 904 and/or 908 of process 900. It is noted that this may involve sending appropriate control signals to the buck stage 104 and/or the boost stage 106.

The memory 1556 may include any type of system memory, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), read-only memory (ROM), or a combination thereof. In one embodiment, the memory 1556 may include ROM used at power-on, and DRAM used to store programs and data used during program execution. In an embodiment, the memory 1556 is non-transitory. The secondary memory device 1554 may include any type of storage device for storing data, programs, and other information and enabling the data, programs, and other information to be accessed via the bus. The secondary memory device 1554 may include one or more of the following: solid state drives, hard disk drives, magnetic disk drives, optical disk drives, and the like.

The processing unit 1500 also includes one or more network interfaces 1562, which network interfaces 1562 may include wired links such as ethernet lines and/or wireless links. In one embodiment, the network interface 1562 allows the processing unit 1500 to communicate with the solar inverter 204. The network interface 1562 may provide wireless communication via one or more transmitter/transmit antennas and one or more receiver/receive antennas. In one embodiment, the processing unit 1500 is coupled to a local or wide area network for data processing and communication with remote devices, such as other processing units, the Internet, remote storage facilities, and the like.

The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the disclosed embodiments. Various modifications and alterations to this invention will become apparent to those skilled in the art without departing from the scope and spirit of this invention. The aspects of the invention were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various modifications as are suited to the particular use contemplated.

For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in the process may be performed by the same or different computing device as used in the other steps, and each step is not necessarily performed by a single computing device.

Aspects of the present invention are described herein in connection with flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" include plural references unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A power generation system, comprising:

a plurality of inductor-less buck stages, each inductor-less buck stage having an input for receiving a DC voltage from a DC power source and a buck stage output for providing the DC voltage;

logic to operate the plurality of buck stages to regulate the power output of each DC power source, wherein the logic is further to operate a respective buck stage for each of the buck stages at a respective target duty cycle to maintain a target power efficiency, a combined DC voltage of the plurality of buck stage output voltages being determined in accordance with the target duty cycle; and

a boost stage comprising a boost stage output and a boost stage input for receiving the combined DC voltage from a plurality of buck stage outputs, the boost stage comprising a boost mode in which a voltage at the boost stage input is less than a voltage at the boost stage output and a bypass mode in which the voltage at the boost stage input is the same as the voltage at the boost stage output;

wherein the logic is further to determine that the voltage boost stage should be operated in the boost mode in response to a condition of the plurality of voltage buck stages, and to indicate that a combined output voltage of the voltage buck stages falls below a current input voltage of the voltage boost stage in response thereto when it is determined that the combined DC voltage of the plurality of voltage buck stages needs to fall below a threshold voltage to maintain a target duty cycle of the voltage buck stages.

2. The system of claim 1, wherein the voltage increasing stage further comprises a filter for receiving current outputs of the plurality of voltage decreasing stages.

3. The system of claim 2, wherein the boost stage is configured to use the filter as an energy storage device.

4. The system of claim 3, wherein the filter is an inductor.

5. The system of claim 1, wherein the logic is further configured to:

receiving a signal from an output of each DC power supply; and

controlling a duty cycle of each of the buck stages based on the signal.

6. The system of claim 1, wherein the DC voltage source is a photovoltaic PV module, wherein the target power efficiency of each of the buck stages is at a maximum power point of the corresponding photovoltaic module.

7. The system of claim 1, further comprising:

a DC-AC converter having an input connected to the output of the voltage boost stage, wherein the DC-AC converter is for regulating a DC voltage at the input of the DC-AC converter.

8. The system of claim 7, wherein the logic is further configured to:

the duty cycle of the boost stage is controlled such that, when it is determined that the DC voltage at the input of the DC-AC converter does not meet the discrimination condition, in response thereto, the input voltage of the boost stage is reduced relative to the output voltage of the boost stage.

9. The system of claim 1, wherein the plurality of buck stages are to generate pulse width modulated output voltages at a same switching frequency, wherein the plurality of buck stages are to interleave the pulse width modulated output voltages.

10. A method for operating a power generation system, the method comprising:

receiving a DC voltage from each of a plurality of photovoltaic PV modules at a corresponding plurality of inductor-less buck stages;

operating each of the plurality of inductor-less buck stages to regulate the power output of the corresponding photovoltaic module, including generating an output voltage for each buck stage, wherein for each buck stage operating the respective buck stage at a respective target duty cycle to maintain a target power efficiency, a combined DC voltage of the plurality of buck stage output voltages is determined according to the target duty cycle;

receiving a combined output voltage from all of the plurality of buck stages at an input of a boost stage, the boost stage comprising a boost mode in which a voltage at the input is less than a voltage at an output of the boost stage and a bypass mode in which the voltage at the input is the same as the voltage at the output;

operating the voltage increasing stage to increase the combined output voltage from the voltage decreasing stage; and

the boosted voltage is provided to the solar inverter,

wherein the method further comprises:

determining that the voltage boosting stage should be operated in the boost mode in response to a condition of the plurality of voltage reducing stages, and when it is determined that the combined output voltage of the plurality of voltage reducing stages needs to fall below a threshold voltage to maintain a target duty cycle of the voltage reducing stage, in response thereto, indicating that the combined output voltage of the voltage reducing stages falls below a current input voltage of the voltage boosting stage.

11. The method of claim 10, further comprising receiving the output currents of the plurality of inductor-less buck stages at a filter of the boost stage.

12. The method of claim 11, wherein the filter comprises an inductor, and wherein operating the boost stage to boost the output voltage from the buck stage comprises storing energy in the inductor.

13. The method of claim 10, further comprising:

the reduced voltage is boosted by the voltage boosting stage to maintain an output voltage of the voltage boosting stage at a target voltage level.

14. The method of claim 10, wherein the operating each of the plurality of inductor-less buck stages to regulate the power output of the corresponding photovoltaic module comprises:

generating a pulse width modulated output voltage at each of the buck stages at the same switching frequency; and

interleaving the pulse width modulated output voltage.

15. A Photovoltaic (PV) power system, comprising:

a plurality of photovoltaic modules for providing a DC voltage; and

a buck-boost converter comprising a plurality of inductor-less buck stages and a boost stage, wherein each of the inductor-less buck stages comprises an input for receiving a DC voltage from one of the photovoltaic modules, each of the inductor-less buck stages comprises an output for providing the DC voltage, and each of the buck stages is for regulating a power output of the corresponding photovoltaic module, wherein the boost stage comprises an input for receiving a combined DC voltage from a plurality of buck stage outputs, the boost stage comprises an output for providing the DC voltage, the boost stage comprises a boost mode in which a voltage at the input is less than a voltage at the output of the boost stage, and a bypass mode in which the voltage at the input is the same as the voltage at the output;

wherein the photovoltaic power system operates a respective buck stage for each of the buck stages at a respective target duty cycle to maintain a target power efficiency, the combined DC voltage of the plurality of buck stage output voltages determined in accordance with the target duty cycle,

wherein it is determined that the voltage boost stage should be operated in the boost mode in response to the condition of the plurality of voltage buck stages, and upon determining that the combined output voltage of the plurality of voltage buck stages needs to fall below a threshold voltage to maintain a target duty cycle for the voltage buck stages, in response thereto, the photovoltaic power system instructs the combined output voltage of the voltage buck stages to fall below a current input voltage of the voltage boost stage.

16. The photovoltaic power system of claim 15, wherein the plurality of buck stages are configured to provide a series output current, wherein the boost stage comprises an inductor configured to receive the series current.

17. The photovoltaic power system of claim 16, wherein the boost stage is configured to use the inductor as an energy storage device to boost the combined DC voltage from the plurality of buck stages and to provide a boosted voltage at an output of the boost stage.

18. The photovoltaic power system of claim 15, comprising a plurality of buck-boost converters, wherein the plurality of buck-boost converters are connected in series, the combined DC voltage output from the boost stages of the plurality of buck-boost converters being provided to a solar inverter.

19. The photovoltaic power system of claim 15, comprising a plurality of buck-boost converters connected in series;

an additional boost stage having an input for receiving the combined DC voltage from a boost stage of the plurality of buck-boost converters; and

a solar inverter having a DC input for receiving a DC voltage from the output of the additional boost stage.

20. The photovoltaic power system of claim 15, wherein the plurality of buck stages are configured to generate pulse width modulated output voltages at a same switching frequency, wherein the plurality of buck stages are configured to interleave the pulse width modulated output voltages.

21. The photovoltaic power system of claim 15, wherein a first of the photovoltaic modules comprises a single photovoltaic panel, a plurality of photovoltaic panels connected in series, or a sub-string of photovoltaic panels.

22. The photovoltaic power system of claim 15, comprising a plurality of buck-boost converters, wherein the plurality of buck-boost converters are connected in series, in parallel, or a combination of series and parallel.