CN110896117B - Crystalline silicon solar cell diffusion layer and preparation method thereof - Google Patents

Crystalline silicon solar cell diffusion layer and preparation method thereof Download PDF

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CN110896117B
CN110896117B CN201811050878.0A CN201811050878A CN110896117B CN 110896117 B CN110896117 B CN 110896117B CN 201811050878 A CN201811050878 A CN 201811050878A CN 110896117 B CN110896117 B CN 110896117B
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silicon wafer
diffusion
layer
solar cell
diffusion layer
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CN110896117A (en
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冯雪
蒋晔
陈颖
付浩然
张柏诚
刘兰兰
王志建
邰艳龙
彭祖军
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Tsinghua University
Institute of Flexible Electronics Technology of THU Zhejiang
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Tsinghua University
Institute of Flexible Electronics Technology of THU Zhejiang
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention relates to a crystalline silicon solar cell diffusion layer and a preparation method thereof, wherein the preparation method comprises the following steps: the method includes the steps of providing a silicon wafer and a diffusion source; placing the diffusion source on the surface of the silicon wafer to form a prefabricated layer, wherein the thickness of the prefabricated layer is less than or equal to 2 microns; thirdly, annealing the silicon wafer with the prefabricated layer, so that the diffusion elements in the prefabricated layer are diffused into the silicon wafer to form a diffusion layer. The preparation method is not limited by the thickness of the silicon wafer, can realize the controllable preparation of the diffusion layer, has simple process and low cost, can ensure the integrity and the process stability of the silicon wafer, has good repeatability, and has good practical application value, and the sheet resistance of the obtained crystalline silicon solar cell diffusion layer is 20 omega/□ -110 omega/□.

Description

Crystalline silicon solar cell diffusion layer and preparation method thereof
Technical Field
The invention relates to the field of solar cells, in particular to a crystalline silicon solar cell diffusion layer and a preparation method thereof.
Background
The process for manufacturing the crystalline silicon solar cell in a large-scale mode comprises diffusion, and a PN junction obtained after a diffusion layer is formed by diffusion is the heart of the crystalline silicon solar cell and directly influences the electrical property of the crystalline silicon solar cell.
Currently, the crystalline silicon solar cell generally adopts (100) p-type silicon as a base material, and is vertically inserted into a quartz boat back to use liquid phosphorus oxychloride (POCl) 3 ) As a diffusion source, a phosphorus source is carried into a reaction system by protective gas, and then a diffusion layer is formed in the silicon wafer through thermal diffusion treatment. Wherein, the thermal diffusion treatment is to decompose the phosphorus source at about 1000 ℃, deposit the phosphorus source on the surface of the silicon wafer, and then carry out knot pushing for a period of time at 800-900 ℃ to form a diffusion layer.
However, with the decreasing thickness of silicon wafers, ultra-thin silicon wafers cannot be inserted into a quartz boat back-to-back vertically, which causes a problem of greater compatibility in the above processes. In addition, in the thermal diffusion treatment, diffusion layers are formed on both sides and edges of the silicon wafer, and the diffusion layers at the edges can conduct the upper and lower surfaces, so that the battery cannot work normally. In order to ensure the performance of the solar cell, the silicon wafer is generally floated on an acid solution in industrial production to remove the diffusion layer on the back surface and the edge. However, the existing post-cleaning equipment mainly adopts a roller assembly line to remove the diffusion layer on the back and the edge, and the minimum thickness of the silicon wafer is generally required to be 140-160 μm. If the process is adopted to directly etch the ultrathin silicon wafer, the corrosive solution at the bottom of the silicon wafer bypasses the edge of the silicon wafer and reaches the front side of the silicon wafer, so that the diffusion layer on the front side is damaged. Meanwhile, the ultrathin silicon wafer has certain flexibility, so that the ultrathin silicon wafer can be bent to a certain degree between the rollers, and the stability of the etching process is greatly reduced. Therefore, in the prior art, a method for directly growing a diffusion layer exists, but the method has higher equipment cost; the preparation of the diffusion layer can be realized by a method of spin coating the diffusion source or a method of diffusion after coating the diffusion source in a photoetching technology area, but the controllability of the diffusion layer is not high, the diffusion can only be realized in the whole area, and the photoetching technology cost of the diffusion layer is higher and the production efficiency is lower.
Disclosure of Invention
Therefore, the preparation method of the crystalline silicon solar cell diffusion layer is not limited by the thickness of a silicon wafer, controllable preparation of the diffusion layer can be realized, the integrity of the silicon wafer can be ensured, and the sheet resistance of the prepared diffusion layer is controllable.
A preparation method of a crystalline silicon solar cell diffusion layer comprises the following steps:
the method includes the steps of providing a silicon wafer and a diffusion source;
placing the diffusion source on the surface of the silicon wafer to form a prefabricated layer, wherein the thickness of the prefabricated layer is less than or equal to 2 microns;
thirdly, annealing the silicon wafer with the prefabricated layer, so that the diffusion elements in the prefabricated layer are diffused into the silicon wafer to form a diffusion layer.
In one embodiment, in step (2), the diffusion source is placed on a surface of the silicon wafer by a printing method to form a prefabricated layer.
In one embodiment, the printing method includes one of ink direct write, ink jet printing.
In one embodiment, the thickness of the silicon wafer is 5-100 μm.
In one embodiment, the diffusion source comprises a diffusion element comprising a B element or a P element;
when a P-type silicon wafer is adopted, the diffusion element is a P element;
when an n-type silicon wafer is adopted, the diffusion element is a B element.
In one embodiment, a plurality of the prefabricated layers are formed on the silicon wafer at intervals.
In one embodiment, the temperature of the annealing treatment is 600-1000 ℃ and the time is 20-120 minutes.
In one embodiment, a protective gas is introduced during the annealing process, and the protective gas comprises at least one of nitrogen and argon.
In one embodiment, the protective gas further comprises oxygen, and the introduction amount of the oxygen is less than or equal to 50%.
The preparation method of the invention has the following beneficial effects:
the invention realizes the uniform and controllable preparation of the prefabricated layer on the silicon wafer by the printing method without the limitation of the thickness of the silicon wafer. Especially, when the silicon wafer is an ultrathin silicon wafer, the printing probe of the printing method is not contacted with the silicon wafer, the method for preparing the prefabricated layer in a non-pressure non-contact way can not damage the ultrathin silicon wafer, the method is beneficial to protecting the integrity of the ultrathin silicon wafer and improving the reliability of the diffusion process of the ultrathin silicon wafer solar cell.
In the annealing treatment process, the prefabricated layer is kept in the printing area and does not deviate, the diffusion elements diffuse into the silicon wafer after the solvent of the prefabricated layer is volatilized, the solid diffusion is realized, the diffusion layer cannot be formed on the other surface and the side surface of the silicon wafer, and the subsequent complicated cleaning process of the diffusion layer is not needed. And after annealing, no residual prefabricated layer is formed on the silicon wafer, compared with a preparation method for retaining the residual prefabricated layer, the whole preparation process is shortened, the whole preparation efficiency is improved, the process is simple, the cost is low, the integrity and the process stability of the silicon wafer can be ensured, the repeatability is good, and the method has good practical application value.
The sheet resistance of the crystalline silicon solar cell diffusion layer obtained by the preparation method is 20 omega/□ -110 omega/□.
The diffusion layer has good uniformity and proper sheet resistance range, can form a good pn junction with a silicon wafer, realizes the separation of photon-generated carriers under the illumination condition, can form good ohmic contact with a subsequently prepared electrode, realizes the transmission of the carriers, and is suitable for being applied to high-sensitivity devices, thin film batteries in the aviation field and the like.
Drawings
FIG. 1 is a flow chart of a preparation process of a crystalline silicon solar cell diffusion layer.
In the figure: 1. a silicon wafer; 2. prefabricating a layer; 3. a diffusion layer.
Detailed Description
The crystalline silicon solar cell diffusion layer and the preparation method thereof provided by the invention will be further explained below.
As shown in fig. 1, the method for preparing the crystalline silicon solar cell diffusion layer provided by the invention comprises the following steps:
the method includes the steps that a silicon chip 1 and a diffusion source are provided;
secondly, placing the diffusion source on the surface of the silicon wafer 1 to form a prefabricated layer 2, wherein the thickness of the prefabricated layer 2 is less than or equal to 2 microns;
thirdly, annealing the silicon wafer 1 with the prefabricated layer 2, so that the diffusion elements in the prefabricated layer 2 diffuse into the silicon wafer 1 to form a diffusion layer 3.
In the step (1), the thickness of the silicon wafer 1 is not limited, and the preparation method is suitable for mainstream silicon wafers and ultrathin silicon wafers with the thickness of about 160-180 μm at present. Considering that the silicon wafer with the thickness of 5-100 microns has flexibility, the printing method belongs to a non-pressure non-contact additive manufacturing method, and cannot damage the silicon wafer, so that the silicon wafer 1 is preferably an ultrathin silicon wafer with the thickness of 5-100 microns, the controllable preparation of a diffusion layer on the ultrathin silicon wafer can be realized, the cost is low, and the efficiency is high.
The diffusion source is prepared by mixing an organic vehicle with various functional powders, such as phosphorus doped (POCl) 3 、P 2 O 5 ) Or boron doping (BBr) 3 、BCl 3 、B 2 H 6 Boron powder), or boron-aluminum doped slurry obtained by doping a certain proportion of boron element in aluminum slurry, or a mixture containing phosphorus and silicon and using ethanol/ester as a solvent.
In the diffusion source, the diffusion element includes a B element or a P element. Preferably, when a P-type silicon wafer is used, the diffusion element is a P element to form n + A p-type crystalline silicon solar cell; when an n-type silicon wafer is used, the diffusion element is B element to form p + An/n-type crystalline silicon solar cell. The two types of crystalline silicon solar cells have equivalent performances, but n + The irradiation resistance of the p-type crystalline silicon solar cell is superior to that of p + The/n type crystalline silicon solar cell is more suitable for space application.
In the step (2), a printing method is adopted to place the diffusion source on one surface of the silicon wafer 1 to form a prefabricated layer 2. Compared with pressure contact type coating methods such as a spin coating method, a screen printing method, an ink jet printing method, a slit coating method, a spraying method, a relief printing method, a gravure printing method and the like, a printing probe of the printing method is not in contact with a silicon wafer, the silicon wafer 1 is not damaged, a uniform prefabricated layer 2 can be formed on the silicon wafer 1, and the printing method is particularly suitable for ultrathin flexible silicon wafers and has an obvious effect.
Specifically, the printing method is not limited, and may preferably be one of direct ink writing and inkjet printing which are easy to handle.
If many small cells are made on the same silicon wafer 1, then the division is performed. The pitch of the preform layer 2 can be controlled to form a plurality of preform layers 2 at intervals on the silicon wafer 1.
It will be appreciated that the pre-form layer 2 may be formed in a single pass by modification of the printing apparatus. On the basis of the existing printing equipment, the prefabricated layer 2 can be formed by back and forth printing through the printing probe. Under the condition of the same printing speed, the cross-sectional volume of single printing is the same, and at the moment, the distance between the printing probe and the silicon wafer 1 needs to be adjusted to control the aspect ratio (the ratio of the height to the width) of single printing, so as to control the thickness of the prefabricated layer 2. Considering that if the aspect ratio is too large during single printing, the diffusion source is easy to spread unevenly and is not beneficial to fully entering the silicon wafer 1 by diffusion elements during diffusion; if the aspect ratio is too small, surface holes are easy to appear in the printing process, so that the diffusion of the diffusion elements in the silicon wafer 1 is not uniform. Therefore, the aspect ratio at the time of single printing is preferably 2:1 to 1, which not only allows the thickness of the formed preform layer 2 to be controlled, but also relatively ensures the uniformity of the formed preform layer 2.
In the step (3), the diffusion elements in the prefabricated layer 2 are diffused into the silicon wafer 1 through annealing treatment, and a diffusion layer 3 is formed in the silicon wafer 1. The diffusion process belongs to solid state diffusion, and a diffusion layer is not formed on other surfaces of the silicon wafer 1, so that the controllable preparation of the diffusion layer 3 can be realized.
Specifically, in the annealing process, with the rise of temperature, the organic carriers in the prefabricated layer 2 begin to volatilize, then the functional powder begins to melt and keeps good contact with the surface of the silicon wafer 1, and when the silicon wafer is melted for a period of time and reaches a thermal equilibrium state, the diffusion element boron or phosphorus begins to diffuse into the silicon wafer 1. After the annealing treatment is completed, the temperature starts to decrease, and the diffusion elements in the silicon wafer 1 start to precipitate due to saturation, and partially move in the direction of the original preform layer 2, thereby forming a concentration gradient. When the temperature drops below the active temperature of the diffusing element, the diffusion layer 3 reaches a steady state.
In particular, the gradient concentration of the diffusion layer ideally exhibits a steep drop, but in practice it is generally not completely steep, and only a relatively steep drop effect can be exhibited. The thickness of the prefabricated layer 2 is less than or equal to 2 micrometers, no prefabricated layer 2 is left after annealing, at the moment, if all diffusion elements in the prefabricated layer 2 are diffused into the silicon wafer 1 to form the diffusion layer 3, the temperature or the heat preservation time is improperly controlled, the diffusion distance of the diffusion elements is increased, and further, on the premise that the total amount of the elements is limited, the concentration distribution of the diffusion layer 3 in the silicon wafer 1 is uniform, so that the relatively steep decline trend becomes gentle. Therefore, the corresponding relation between the annealing time, temperature and thickness needs to be strictly controlled, otherwise, the concentration gradient of the annealed diffusion layer is damaged, and the performance of the subsequent battery is influenced. Preferably, the temperature of the annealing treatment is 600-1000 ℃, and the time is 20-120 minutes, so as to obtain the diffusion layer 3 with proper sheet resistance.
Preferably, a protective gas is introduced during the annealing treatment, and the protective gas comprises at least one of nitrogen and argon.
Preferably, when the diffusion source is phosphorus doped (POCl) 3 、P 2 O 5 ) Or boron doping (BBr) 3 、BCl 3 、B 2 H 6 Boron powder), oxygen can be introduced into the protective gas, and a thin silicon oxide layer is formed on the surface of the silicon wafer by a thermal oxidation method, so that the solid solubility of the prefabricated layer 2 in the silicon oxide layer is higher, and the diffusion element can be conveniently diffused into the silicon wafer 1 to form the diffusion layer 3 with higher concentration. And the silicon oxide layer can be removed by etching solution such as HF solution after the diffusion is finished. Of course, when the oxygen concentration is too highSince it is difficult to control the thickness and the mass of the silicon oxide layer, the amount of oxygen gas introduced is 50% or less, and more preferably 5% to 50%.
The invention realizes the uniform and controllable preparation of the prefabricated layer on the silicon wafer by the printing method without the limitation of the thickness of the silicon wafer. Particularly, when the silicon wafer is an ultrathin silicon wafer, a printing probe of the printing method is not in contact with the silicon wafer, and the method for preparing the prefabricated layer in a non-pressure non-contact mode cannot damage the ultrathin silicon wafer, so that the integrity of the ultrathin silicon wafer is protected, and the reliability of the diffusion process of the solar cell of the ultrathin silicon wafer is improved.
In the annealing treatment process, the prefabricated layer is kept in the printing area and does not deviate, the solvent of the prefabricated layer is volatilized, and then the diffusion elements are diffused into the silicon wafer, so that the solid diffusion is realized, the diffusion layer is not formed on the other surface and the side surface of the silicon wafer, and the subsequent complicated cleaning process of the diffusion layer is not needed. And after annealing, no residual prefabricated layer is left on the silicon wafer, compared with a preparation method for retaining the residual prefabricated layer, the whole preparation process is shortened, the whole preparation efficiency is improved, the process is simple, the cost is low, the integrity and the process stability of the silicon wafer can be ensured, the repeatability is good, and the method has a good practical application value.
The invention also provides a crystalline silicon solar cell diffusion layer obtained by the preparation method, and the sheet resistance of the diffusion layer is 20 omega/□ -110 omega/□.
Specifically, when the prefabricated layers are arranged on the surface of the silicon wafer at intervals, the obtained diffusion layers are mutually spaced.
Preferably, when the silicon wafer is an ultra-thin silicon wafer of 5 μm to 100 μm, the diffusion layer is formed. The flexible crystalline silicon solar cell can be prepared on the basis of the ultrathin silicon wafer, and further, the flexible solar cell module can be prepared on the basis of the flexible crystalline silicon solar cell.
The diffusion layer has good uniformity and proper sheet resistance range, can form a good pn junction with a silicon wafer, realizes the separation of photon-generated carriers under the illumination condition, can form good ohmic contact with a subsequently prepared electrode, realizes the transmission of the carriers, and is suitable for being applied to high-sensitivity devices, thin film batteries in the aviation field and the like.
Hereinafter, the crystalline silicon solar cell diffusion layer and the method for preparing the same will be further described by the following specific examples.
Example 1:
providing a p-type silicon wafer with the thickness of 20 mu m, firstly carrying out ultrasonic cleaning on the silicon wafer by using an acetone solution, then rinsing by using ultrapure water (DI water), then carrying out ultrasonic cleaning by using an alcohol solution, rinsing by using ultrapure water (DI water), then cleaning by using a dilute hydrofluoric acid solution, rinsing by using ultrapure water (DI water), and finally drying by using a low-boiling-point organic solvent.
Forming a complete prefabricated layer on the cleaned silicon wafer surface by adopting an ink-jet printing mode, wherein the aspect ratio of single printing is 1:2, the thickness of the formed prefabricated layer is 2 mu m, and the diffusion source of the prefabricated layer is POCl 3 Doped silicon ink.
And (3) placing the silicon wafer covered with the prefabricated layer in vacuum annealing equipment, introducing argon protective gas, annealing for 80min at the temperature of 900 ℃, and diffusing diffusion elements into the silicon wafer to obtain the crystalline silicon solar cell diffusion layer with the sheet resistance of 60 omega/□.
Example 2:
example 2 is different from example 1 only in that example 2 is annealed at 800 ℃ for 80min to obtain a crystalline silicon solar cell diffusion layer with sheet resistance of 65 omega/□.
Example 3:
example 3 is different from example 1 only in that example 3 is annealed at a temperature of 700 ℃ for 65min to obtain a crystalline silicon solar cell diffusion layer with the sheet resistance of 70 omega/□.
Example 4:
example 4 is different from example 1 only in that example 4 is annealed at 600 ℃ for 80min to obtain a crystalline silicon solar cell diffusion layer with sheet resistance of 105 Ω/□.
Example 5:
example 5 differs from example 1 only in that the aspect ratio of the preform layer in example 5 is 1:3, resulting in a crystalline silicon solar cell diffusion layer with sheet resistance of 75 Ω/□.
Example 6:
example 6 differs from example 1 only in that the aspect ratio of the prefabricated layer in example 6 is 1.
Example 7:
an n-type silicon wafer having a thickness of 100 μm was provided, and was subjected to ultrasonic cleaning with an acetone solution, then rinsing with ultrapure water (DI water), then ultrasonic cleaning with an alcohol solution, rinsing with ultrapure water (DI water), then cleaning with a dilute hydrofluoric acid solution, rinsing with ultrapure water (DI water), and finally drying with a low-boiling organic solvent.
And forming a complete prefabricated layer on the surface of the cleaned silicon wafer by adopting an ink-jet printing mode, wherein the aspect ratio of single printing is 1:5, the thickness of the formed prefabricated layer is 1 mu m, and a diffusion source of the prefabricated layer is boron-aluminum doped slurry.
And (3) placing the silicon wafer covered with the prefabricated layer in vacuum annealing equipment, introducing nitrogen protective gas, annealing for 100min at the temperature of 800 ℃ to diffuse diffusion elements into the silicon wafer, and obtaining the crystalline silicon solar cell diffusion layer with the sheet resistance of 80 omega/□.
Example 8:
a p-type silicon wafer having a thickness of 40 μm was provided, and was subjected to ultrasonic cleaning with an acetone solution, then rinsing with ultrapure water (DI water), then ultrasonic cleaning with an alcohol solution, rinsing with ultrapure water (DI water), then cleaning with a dilute hydrofluoric acid solution, rinsing with ultrapure water (DI water), and finally drying with a low-boiling organic solvent.
And forming a complete prefabricated layer on the surface of the cleaned silicon wafer by adopting an ink-jet printing mode, wherein the aspect ratio of single printing is 2:1, the thickness of the formed prefabricated layer is 1.5 mu m, and a diffusion source of the prefabricated layer is a mixture containing phosphorus and silicon and taking ethanol as a solvent.
And (3) placing the silicon wafer covered with the prefabricated layer in vacuum annealing equipment, introducing argon protective gas, annealing for 120min at the temperature of 1000 ℃, and diffusing diffusion elements into the silicon wafer to obtain the crystalline silicon solar cell diffusion layer with the sheet resistance of 20 omega/□.
Example 9:
an n-type silicon wafer having a thickness of 5 μm was provided, and was subjected to ultrasonic cleaning with an acetone solution, then rinsing with ultrapure water (DI water), then ultrasonic cleaning with an alcohol solution, rinsing with ultrapure water (DI water), then cleaning with a dilute hydrofluoric acid solution, rinsing with ultrapure water (DI water), and finally drying with a low-boiling organic solvent.
And forming a complete prefabricated layer on the surface of the cleaned silicon wafer by adopting an ink direct writing mode, wherein the aspect ratio of single printing is 1:4, the thickness of the formed prefabricated layer is 1.6 mu m, and the diffusion source of the prefabricated layer is silicon ink containing boron powder.
And (3) placing the silicon wafer covered with the prefabricated layer in vacuum annealing equipment, introducing nitrogen protective gas, annealing for 100min at the temperature of 900 ℃, and diffusing diffusion elements into the silicon wafer to obtain the crystalline silicon solar cell diffusion layer with the sheet resistance of 75 omega/□.
Example 10:
a p-type silicon wafer having a thickness of 50 μm was provided, and was subjected to ultrasonic cleaning with an acetone solution, then rinsing with ultrapure water (DI water), then ultrasonic cleaning with an alcohol solution, rinsing with ultrapure water (DI water), then cleaning with a dilute hydrofluoric acid solution, rinsing with ultrapure water (DI water), and finally drying with a low-boiling organic solvent.
Forming a complete prefabricated layer on the cleaned silicon wafer surface by adopting an ink direct writing mode, wherein the aspect ratio of single printing is 1:3, the thickness of the formed prefabricated layer is 1.2 mu m, and the diffusion source of the prefabricated layer is BBr 3 Doped silicon ink.
And (3) placing the silicon wafer covered with the prefabricated layer in vacuum annealing equipment, and introducing Ar: o is 2 Annealing the mixed gas of =8:1 at 900 ℃ for 120min to diffuse the diffusion elements into the silicon wafer, thereby obtaining the crystalline silicon solar cell diffusion layer with the sheet resistance of 30 Ω/□.
Example 11:
example 11 differs from example 10 only in that example 11Ar: o is 2 And (3) mixing gas of =1:1 to obtain the crystalline silicon solar cell diffusion layer with the sheet resistance of 50 Ω/□.
Example 12:
example 12 differs from example 1 only in that the thickness of the silicon wafer in example 12 is 140 μm, resulting in a crystalline silicon solar cell diffusion layer with a sheet resistance of 70 Ω/□.
Example 13:
example 13 differs from example 1 only in that the thickness of the silicon wafer in example 13 is 160 μm, resulting in a crystalline silicon solar cell diffusion layer with a sheet resistance of 60 Ω/□.
Example 14:
example 14 differs from example 1 only in that the annealing time of example 14 was 20min, resulting in a crystalline silicon solar cell diffusion layer with a sheet resistance of 90 Ω/□.
Example 15:
a p-type silicon wafer having a thickness of 50 μm was provided, and was subjected to ultrasonic cleaning with an acetone solution, then rinsing with ultrapure water (DI water), then ultrasonic cleaning with an alcohol solution, rinsing with ultrapure water (DI water), then cleaning with a dilute hydrofluoric acid solution, rinsing with ultrapure water (DI water), and finally drying with a low-boiling organic solvent.
And forming prefabricated layers which are mutually spaced on the surface of the cleaned silicon wafer in an ink-jet printing mode, wherein the spacing distance is 1mm, the aspect ratio of single printing is 1:5, the thickness of the formed prefabricated layer is 0.8 mu m, and the diffusion source of the prefabricated layer is boron-aluminum doped slurry.
And (3) placing the silicon wafer covered with the prefabricated layer in vacuum annealing equipment, introducing nitrogen protective gas, annealing for 110min at the temperature of 800 ℃ to diffuse diffusion elements into the silicon wafer, and obtaining the crystalline silicon solar cell diffusion layer with the square resistance of the diffusion region of which the spacing distance is 1mm and the sheet resistance of which is 80 omega/□.
Example 16:
example 16 differs from example 15 only in that example 16 has a separation distance of 5mm, resulting in a crystalline silicon solar cell diffusion layer having a diffusion region sheet resistance size of 80 Ω/□ with a separation distance of 5 mm.
Example 17:
example 17 differs from example 15 only in that example 17 has a separation distance of 8mm, resulting in a crystalline silicon solar cell diffusion layer having a diffusion region sheet resistance size of 80 Ω/□ with a separation distance of 8 mm.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (5)

1. A preparation method of a crystalline silicon solar cell diffusion layer is characterized by comprising the following steps:
the method includes the steps of providing a silicon wafer and a diffusion source;
placing the diffusion source on the surface of the silicon wafer to form a prefabricated layer, wherein the thickness of the prefabricated layer is less than or equal to 2 microns; placing the diffusion source on one surface of the silicon wafer by adopting a printing method to form a prefabricated layer; the aspect ratio in single printing is 2:1-1;
thirdly, annealing the silicon wafer with the prefabricated layer to enable diffusion elements in the prefabricated layer to diffuse into the silicon wafer to form a diffusion layer; the temperature of the annealing treatment is 600-1000 ℃, and the time is 20-120 minutes;
in the annealing treatment process, the prefabricated layer is kept in the printing area and does not deviate, and after the solvent of the prefabricated layer is volatilized, the diffusion elements are diffused into the silicon wafer and belong to solid diffusion, so that a diffusion layer cannot be formed on the other surface and the side surface of the silicon wafer;
the diffusion source is POCl 3 、P 2 O 5 、BBr 3 、BCl 3 、B 2 H 6 Or boron powder doped silicon ink;
and introducing protective gas during annealing treatment, wherein the protective gas comprises at least one of nitrogen and argon, the protective gas also comprises oxygen, and the introduction amount of the oxygen is 5-50%.
2. The method for preparing the crystalline silicon solar cell diffusion layer according to claim 1, wherein the printing method comprises one of ink direct writing and ink jet printing.
3. The method for preparing the crystalline silicon solar cell diffusion layer according to claim 1, wherein the thickness of the silicon wafer is 5 μm to 100 μm.
4. The method for preparing the crystalline silicon solar cell diffusion layer as claimed in claim 1, wherein a plurality of the pre-fabricated layers are formed on the silicon wafer at intervals.
5. The crystalline silicon solar cell diffusion layer obtained by the preparation method of any one of claims 1 to 4, wherein the sheet resistance of the diffusion layer is 20 Ω/□ -110 Ω/□.
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CN103500774A (en) * 2013-09-18 2014-01-08 南京航空航天大学 Method for utilizing P-type silicon ball as boron source to prepare local back field

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