CN110896050A - Method for forming dielectric film - Google Patents

Method for forming dielectric film Download PDF

Info

Publication number
CN110896050A
CN110896050A CN201811062992.5A CN201811062992A CN110896050A CN 110896050 A CN110896050 A CN 110896050A CN 201811062992 A CN201811062992 A CN 201811062992A CN 110896050 A CN110896050 A CN 110896050A
Authority
CN
China
Prior art keywords
precursor
dielectric film
dielectric
film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811062992.5A
Other languages
Chinese (zh)
Inventor
储江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN201811062992.5A priority Critical patent/CN110896050A/en
Publication of CN110896050A publication Critical patent/CN110896050A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Provided is a method for forming a dielectric film, including: injecting the precursor-A into a reaction chamber in which an element to be processed is arranged, and adsorbing the precursor-A on the surface of the element to be processed to form a monomolecular layer; cleaning with cleaning gas to remove unadsorbed precursor-A on the surface of the element to be treated; injecting the precursor-B into the reaction chamber after plasma is formed outside the reaction chamber, and reacting with the precursor-A to form a dielectric film; cleaning the cleaning gas to remove unreacted precursor-B and reaction byproducts; repeating the steps a-d a predetermined number of times until the film reaches a predetermined thickness. The dielectric film formed by the method provided by the invention has lower dielectric constant, and the formed interlayer dielectric layer can effectively reduce the resistance-capacitance delay, so that the device has better electrical property.

Description

Method for forming dielectric film
Technical Field
The invention relates to a semiconductor memory manufacturing technology. And more particularly to methods for forming dielectric films in semiconductors.
Background
As Integrated Circuit (IC) dimensions shrink, the field of semiconductor fabrication presents many technical challenges. In the back end of line (BEOL), wiring, resistance-capacitance (RC) delay (product of metal line resistance and mutual capacitance) becomes IC scaleThe main problem of cun reduction. As an Interlayer Dielectric (ILD), a better ground Dielectric constant material is selected to replace SiO2To obtain more excellent device performance, it is an important issue in the art.
Disclosure of Invention
The invention provides a method for forming a dielectric film. The dielectric film with low dielectric constant prepared by the method forms an interlayer dielectric layer to replace the mainstream SiO in the prior art2And forming an interlayer dielectric layer. Meanwhile, the manufacturing method can form better carbon content and porosity so as to be suitable for the low dielectric constant of the film and ensure the quality of the dielectric film.
The invention provides a method for forming a dielectric film, which comprises the steps of forming an interlayer dielectric layer with a low dielectric constant in the process of forming the interlayer dielectric layer; the method comprises the following steps: a. injecting the precursor-A into a reaction chamber in which an element to be processed is arranged, and adsorbing the precursor-A on the surface of the element to be processed to form a monomolecular layer; b. cleaning with cleaning gas to remove unadsorbed precursor-A on the surface of the element to be treated; c. injecting the precursor-B into the reaction chamber after plasma is formed outside the reaction chamber, and reacting with the precursor-A to form a dielectric film; d. cleaning the cleaning gas to remove unreacted precursor-B and reaction byproducts; e. repeating the steps a-d a predetermined number of times until the film reaches a predetermined thickness.
In some embodiments, the element to be processed has a structure of multiple layers of metal interconnects.
In some embodiments, precursor-a is octamethylcyclotetrasiloxane; the precursor-B is H2。
In some embodiments, precursor-B forms a plasma at a voltage of 100W.
In some embodiments, steps a-e of the method of forming a dielectric film are performed at a temperature between 100 ℃ and 300 ℃.
In some embodiments, steps a-e of the method of forming a dielectric film are performed at a pressure of between 1.5 torr and 2 torr.
In some embodiments, H2The flow rate of (A) is 50-100 sccm.
In some embodiments, the purge gas is an inert gas.
In some embodiments, the inert gas is Ar, He, N2Or any two or more of them.
In some embodiments, the deposition rate of the dielectric film is in the range of 0.5 to
Figure BDA0001797588960000021
Between/cycles.
In some embodiments, the dielectric film has a carbon content of 10% to 20%, an oxygen content of 40% to 50%, and a dielectric constant of 2 to 3.
The method has the advantages that the dielectric film formed by the method has a low dielectric constant (2-3), and the formed interlayer dielectric layer can effectively reduce the resistance-capacitance delay, so that the device has better electrical property.
Drawings
FIG. 1 is a process diagram of a method of forming a dielectric film according to the present invention;
FIG. 2 shows a plasma H in the method for forming a dielectric film according to the present invention2Schematic diagram of performing an atomic layer deposition step;
FIG. 3 is a comparison of the formation of a dielectric film of the present invention with a prior art dielectric film;
FIG. 4 is a schematic diagram of a dielectric film covered groove structure of the present invention;
fig. 5 is a schematic structural diagram of an IC chip formed by an embodiment of the method of the present invention.
Detailed Description
The following is a description of the embodiments of the present disclosure relating to a method for etching an oxide layer of a semiconductor chip, and those skilled in the art will understand the advantages and effects of the present disclosure from the disclosure of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modification and various other changes, which can be made in various details within the specification and without departing from the spirit and scope of the invention. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention.
See fig. 1-2. The invention provides a method for forming an interlayer dielectric layer, which replaces SiO in the prior art with an SiOC dielectric film with lower dielectric constant2The dielectric film of (2) forms an interlayer dielectric layer. The main component of the dielectric film is SiO2With a lower dielectric constant after replacement with SiOC. Detailed description of the inventionreferring to fig. 1, fig. 1 is a schematic view of a process in a method for manufacturing a dielectric thin film according to the present invention. A dielectric film whose main component is SiOC is manufactured by the method, and an interlayer dielectric layer of an IC chip is formed by the dielectric film. Referring to fig. 1, the process essentially comprises 4 steps:
a. injecting a precursor-A (octamethylcyclotetrasiloxane) into a reaction chamber in which an element to be processed is placed; carrying out atomic layer deposition on the precursor-A on the surface of an element to be processed (a silicon substrate), and adsorbing to form a monomolecular layer;
b. cleaning the precursor-A which is not adsorbed on the surface of the element to be treated by the cleaning gas;
c. precursor-B (plasma H)2) Is converted into Plasma H through a Plasma System (PS) outside the reaction chamber under the control of a Mass Flow Controller (MFC) outside the reaction chamber2Injecting the gas into the reaction chamber; performing atomic layer deposition on the surface of the element to be treated by the precursor-B (see figure 2), and simultaneously reacting with the precursor-A (octamethylcyclotetrasiloxane) adsorbed to form a monomolecular layer in the step a to generate SiOC and a byproduct;
d. the purge gas purges away residues and byproducts.
Wherein the element to be processed may have a multi-layer metal interconnect structure.
In the above process, the following reaction occurs
C8H24O4Si4+H2(plasma) → SiOC + by-product
Wherein the by-products include but are not limited to CO, CO2、CH2O、H2O。
e. Repeating the steps a-d for a predetermined number of times, and superposing the SiOC layers until the SiOC film reaches a predetermined thickness.
In the above process, the temperature of the process may be between 100 ℃ and 300 ℃. The process can have a pressure of between 1.5 torr and 2 torr. precursor-B formed a plasma at a voltage of 100W. Plasma H2The flow rate of (A) is 50-100 sccm. The cleaning gas is an inert gas, preferably Ar, He, N2Or any two or more of them. In some preferred embodiments, the process temperature is 130 ± 30 ℃ and the process gas pressure is 2 torr.
The thickness of the dielectric film is determined by a predetermined period (cycle number) according to the actual deposition rate. The deposition rate is preferably 0.5 to
Figure BDA0001797588960000041
Between/cycles. In some preferred embodiments, the deposition rate is
Figure BDA0001797588960000042
Period (c).
The film formed by the method has the carbon content of about 10-20%, the oxygen content of about 40-50% and the dielectric constant of about 2-3, usually less than 2.7, and can reach 2.5, 2.3 or even close to 2 by adjusting the reaction conditions. SiO commonly used in the prior art2The dielectric constant of the dielectric film is usually 3.9 or more. Therefore, compared with the prior art using SiO2The dielectric film formed by the method of the present invention has a lower dielectric constant as a main component of the dielectric film. The dielectric film in the prior art is linearly increased in thickness with time, while the film formation process in the method of the present invention is periodically performed (see fig. 3), i.e., the film formation in the prior art is controlled by time alone, while the film formation in the method of the present invention is controlled by the period unit. Such periodically growing films have better controllability in production. Meanwhile, the whole formed film can better keep the original shape of the structure covered by the film. And the film has better uniformity as a whole. The uniformity of the film canReferring to fig. 4, the film thickness d at the bottom of the groove structure and the film thickness a at the top of the protrusion structure may reach d/a of 1, while the sidewall film thickness b of the protrusion structure and the film thickness a at the top of the protrusion structure may reach b/a of 0.99. The interlayer dielectric layer formed by the dielectric film formed by the method can effectively reduce the resistance-capacitance delay, so that the equipment has better electrical property. Because the parasitic capacitance between the metal interconnection layers is C ═ epsilon S/d (epsilon is the dielectric constant of the metal interlayer dielectric, S is the area of the metal layer, and d is the distance between the metal layers), the main component of the dielectric film formed by the method of the invention of the interlayer dielectric layer is SiOC, the dielectric constant is higher than that of SiO in the prior art2The dielectric film of (a) is low, and thus the parasitic capacitance is relatively small, thereby reducing the resistance-capacitance delay and enabling the current to transmit signals faster. In addition, in the method, the plasma is generated outside the chamber, and is introduced into the chamber for reaction after the flow is controlled. Whereas in the prior art plasma is typically generated and reacted directly inside the chamber. Compared with the prior art, the method can reduce the damage to the film and the contact part of the film in the plasma generation process and can also reduce the damage of the plasma to the machine table and the cavity in the cavity.
An example of an IC chip using a dielectric film formed by the method of the present invention is provided below. The chip is provided with a plurality of metal interconnection layers, the metal interconnection layers are connected through contact parts, and an interlayer dielectric layer is formed between every two conductive metal layers through a dielectric film. The multilayer metal interconnection layer includes an upper metal layer M3, a wiring metal layer M2, and a lower metal layer M1 (see fig. 5). The interlayer dielectric layers (M1Ox, V1Ox, V2Ox) are formed of one or more dielectric films.
In this embodiment, the interlayer dielectric layer is formed of a plurality of dielectric films in which the portion V2Ox covering the wiring metal layer (i.e., the portion around the wiring metal layer M2 and between the wiring metal layer and the upper metal layer M3) is formed of three layers of dielectric films of the same material, the thicknesses of the three layers of dielectric films being 100nm, 400nm, and 400nm from the bottom layer to the top layer, respectively. These dielectric films are formed by the above-described formation method. The dielectric film has a main component of SiOC, a carbon content of 10 to 20%, an oxygen content of 40 to 50%, and a dielectric constant of 2 to 3.
In other embodiments, the thickness (dielectric film thickness) of the interlayer dielectric layer M1Ox between the metal portions of the lower metal layer M1 is 200 nm. The thickness (dielectric film thickness) of the interlayer dielectric layer V1Ox between the lower metal layer M1 and the wiring metal layer M2 was 300 nm.
The IC chip has an interlayer dielectric layer formed by a dielectric film containing SiOC as a main component, and has SiO content higher than that of the prior art2The dielectric film of (2) has a lower dielectric constant. The resistance-capacitance delay can be effectively reduced, and the device has better electrical property. Meanwhile, on the premise that V2Ox has a lower dielectric constant by using a dielectric film containing SiOC as a main component, the thicknesses of V1Ox and M1Ox can be further reduced. The interlayer distance can be reduced on the premise of not influencing the electrical property between metal layers.
As described above, the present invention is advantageous in that a method for forming a dielectric thin film is provided. And provides an example of an IC chip having such a dielectric film forming an interlayer dielectric layer. The dielectric film formed by the method has SiOC as the main component, compared with SiO in the prior art2The film as a main component has a low dielectric constant (2 to 3) and the uniformity of the film is better. The interlayer dielectric layer formed by the dielectric film formed by the method can effectively reduce the resistance-capacitance delay, so that the equipment has better electrical property.
The above embodiments of the method for forming a dielectric film according to the present invention are provided, and it is believed that those skilled in the art can understand the technical solutions and the operating principles of the present invention through the description of the embodiments. However, the above is only a preferred embodiment of the present invention and does not limit the present invention. The technical solution provided by the present invention can be modified appropriately according to the actual needs by those skilled in the art, and modifications and equivalent changes can be made without departing from the scope of the present invention as claimed. The scope of the invention is to be determined by the following claims.

Claims (11)

1. A method of forming a dielectric film, comprising:
a. injecting the precursor-A into a reaction chamber in which an element to be processed is arranged, and adsorbing the precursor-A on the surface of the element to be processed to form a monomolecular layer;
b. cleaning with cleaning gas to remove unadsorbed precursor-A on the surface of the element to be treated;
c. injecting the precursor-B into the reaction chamber after plasma is formed outside the reaction chamber, and reacting with the precursor-A to form a dielectric film;
d. cleaning the cleaning gas to remove unreacted precursor-B and reaction byproducts;
e. repeating the steps a-d a predetermined number of times until the film reaches a predetermined thickness.
2. The method for forming a dielectric film according to claim 1, wherein the element to be processed has a structure of a multilayer metal interconnection.
3. The method for forming a dielectric thin film according to claim 1, wherein the precursor-a is octamethylcyclotetrasiloxane; the precursor-B is H2。
4. The method of claim 1, wherein the precursor-B forms a plasma at a voltage of 100W.
5. The method of claim 1, wherein the steps a-e of the method of forming a dielectric film are performed at a temperature of 100 ℃ to 300 ℃.
6. The method of claim 1, wherein the process steps a-e of the method are performed at a pressure of 1.5 torr to 2 torr.
7. The method of claim 3, wherein the H is2The flow rate of (A) is 50-100 sccm.
8. The method of claim 1, wherein the purge gas is an inert gas.
9. The method for forming a dielectric thin film according to claim 8, wherein the inert gas is Ar, He, N2Or any two or more of them.
10. The method of claim 1, wherein the deposition rate of the dielectric film is in the range of 0.5 to
Figure FDA0001797588950000011
Between/cycles.
11. The method of claim 1, wherein the dielectric film has a carbon content of 10% to 20%, an oxygen content of 40% to 50%, and a dielectric constant of 2 to 3.
CN201811062992.5A 2018-09-12 2018-09-12 Method for forming dielectric film Pending CN110896050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811062992.5A CN110896050A (en) 2018-09-12 2018-09-12 Method for forming dielectric film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811062992.5A CN110896050A (en) 2018-09-12 2018-09-12 Method for forming dielectric film

Publications (1)

Publication Number Publication Date
CN110896050A true CN110896050A (en) 2020-03-20

Family

ID=69785108

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811062992.5A Pending CN110896050A (en) 2018-09-12 2018-09-12 Method for forming dielectric film

Country Status (1)

Country Link
CN (1) CN110896050A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115522180A (en) * 2022-09-20 2022-12-27 苏州源展材料科技有限公司 Preparation method and application of silicon-based thin film with low dielectric constant

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101416293A (en) * 2006-03-31 2009-04-22 应用材料股份有限公司 Method to improve the step coverage and pattern loading for dielectric films
CN102074500A (en) * 2009-11-12 2011-05-25 诺发系统有限公司 Uv and reducing treatment for K recovery and surface clean in semiconductor processing
CN104517994A (en) * 2013-10-01 2015-04-15 乐金显示有限公司 Organic light emitting diode display device and method of manufacturing the same
CN105088191A (en) * 2009-07-15 2015-11-25 应用材料公司 Flow control features of CVD chambers
US20150357181A1 (en) * 2014-06-04 2015-12-10 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
CN108315717A (en) * 2018-01-24 2018-07-24 复旦大学 A kind of preparation method of manganese nitride film

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101416293A (en) * 2006-03-31 2009-04-22 应用材料股份有限公司 Method to improve the step coverage and pattern loading for dielectric films
CN105088191A (en) * 2009-07-15 2015-11-25 应用材料公司 Flow control features of CVD chambers
CN102074500A (en) * 2009-11-12 2011-05-25 诺发系统有限公司 Uv and reducing treatment for K recovery and surface clean in semiconductor processing
CN104517994A (en) * 2013-10-01 2015-04-15 乐金显示有限公司 Organic light emitting diode display device and method of manufacturing the same
US20150357181A1 (en) * 2014-06-04 2015-12-10 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
CN108315717A (en) * 2018-01-24 2018-07-24 复旦大学 A kind of preparation method of manganese nitride film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115522180A (en) * 2022-09-20 2022-12-27 苏州源展材料科技有限公司 Preparation method and application of silicon-based thin film with low dielectric constant

Similar Documents

Publication Publication Date Title
TWI630654B (en) Recessing ultra-low k dielectric using remote plasma source
US6949450B2 (en) Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber
US20150126027A1 (en) Method for manufacturing semiconductor device
JP6467239B2 (en) Ruthenium film forming method, film forming apparatus, and semiconductor device manufacturing method
US8377821B2 (en) Method for forming contact hole structure
TWI295485B (en) Method of improving low-k film property and damascene process using the same
TW200407979A (en) Method of manufacturing low K layer
TW202017108A (en) Semiconductor structures and methods for forming the same
CN110896050A (en) Method for forming dielectric film
US11830741B2 (en) Method for forming film
KR101767538B1 (en) Metal-containing films as dielectric capping barrier for advanced interconnects
CN101123214B (en) Making method for dual enchasing structure
KR102118580B1 (en) Chemical vapor deposition (cvd) of ruthenium films and applications for same
KR20150101359A (en) Method for forming ruthenium containing thin film by atomic layer deposition
TW517271B (en) Method of manufacturing semiconductor device
JP2006024668A (en) Process for fabricating semiconductor device
JP4948278B2 (en) Manufacturing method of semiconductor device
CN115775768B (en) Semiconductor structure and manufacturing method thereof
US20230098689A1 (en) Deposition of boron nitride films using hydrazido-based precursors
CN116190209B (en) Manufacturing method of low-dielectric-constant dielectric layer and metal interconnection structure
KR20060058583A (en) Conductive structure, method of manufacturing the conductive structure, semiconductor device including the conductive structure and method of manufacturing the semiconductor device
KR101078728B1 (en) Method for forming dielectric layer of semiconductor device
TW200849467A (en) Interconnection process
US10381264B2 (en) Process for producing connections to an electronic chip
KR100850107B1 (en) Method for fabricating a semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200320