CN116190209B - Manufacturing method of low-dielectric-constant dielectric layer and metal interconnection structure - Google Patents
Manufacturing method of low-dielectric-constant dielectric layer and metal interconnection structure Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method of a low-dielectric-constant dielectric layer and a metal interconnection structure, which ensures that the low-dielectric-constant dielectric layer has improved mechanical strength and small dielectric constant change by optimizing the component ratio of a precursor and oxygen-containing reaction gas in the manufacturing method of the low-dielectric-constant dielectric layer. The manufacturing method of the metal interconnection structure comprises the steps of manufacturing an intermetallic dielectric layer according to the manufacturing method of the low-dielectric-constant dielectric layer, wherein the intermetallic dielectric layer has hardness close to that of an oxide layer, and deformation caused by mismatch of mechanical strength is reduced; meanwhile, in the subsequent etching process, the etching resistance of the intermetallic dielectric layer is improved, the etching selectivity of the intermetallic dielectric layer relative to the oxide layer serving as the protective layer is reduced, the appearance of a through hole or a groove formed by etching in the intermetallic dielectric layer is improved, the difficulty of the subsequent metal filling process and/or the introduction of holes caused by abnormal etching patterns are avoided, and the electrical performance among elements is improved.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor device.
Background
In Back End of Line (BEOL) processes of advanced chip processes, the dielectric constant k of the inter-metal dielectric (IMD) used together with the resistance of the interconnect metal determine the RC delay performance of the chip transmission. Therefore, the use of low dielectric constant materials is of great importance for reducing the RC delay of the chip. In the prior art, two means for reducing the dielectric constant are: reducing the polarizability of the constituent material; the density of polarized molecules per unit volume is reduced.
Black Diamond (BD) film material is one of the commonly used low dielectric constant materials, and the k value of the low dielectric constant material can be controlled between 2.7 and 3.0. The low dielectric constant material can well reduce signal attenuation caused by impedance and capacitive reactance delay of the circuit during electric signal propagation, namely reduce RC delay phenomenon of back-end interconnection, and meet the technical requirements of 130nm, 90nm, 65nm and 45nm back-end processes.
At present, the porous Black Diamond (BD) material manufactured by the existing interconnection process can meet the requirement of reducing RC delay, but the etching rate of the Black Diamond (BD) dielectric layer in the interconnection process is too fast and is easy to deform, so that the problems of connection and defects of the subsequent process are brought, and the process technology is more and more challenged. At present, a common solution is to adjust process conditions such as an etchant and a reaction temperature during etching, but this complicates a process flow and thus increases production costs.
Accordingly, it is desirable to provide an improved method of fabricating low-k dielectric layers to achieve metal interconnect structures with desirable electrical properties.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a low-k dielectric layer and a metal interconnect structure, which considers the problem that the low-k dielectric layer commonly used in the existing interconnect process is easy to deform during etching, resulting in the introduction of holes in the etched pattern abnormal interconnect structure formed therein.
To achieve the above and other related objects, the present invention provides a method for manufacturing a low-k dielectric layer, comprising:
providing a substrate;
providing a gas mixture comprising a precursor and an oxygen-containing reactant gas;
introducing the gas mixture into a reaction chamber, and forming a low-dielectric-constant dielectric layer on the substrate through a plasma-enhanced chemical vapor deposition process, wherein the low-dielectric-constant dielectric layer comprises a first silicon oxide and a second silicon oxide containing carbon;
wherein the component content of the first silicon oxide in the intermetallic dielectric layer is reduced by increasing the content percentage of the reaction gas in the gas mixture to enhance the mechanical strength of the low-dielectric-constant dielectric layer.
Optionally, the reaction gas comprises O 2 、N 2 O and CO 2 The precursor is selected from any ring structure organic silicon in tetramethyl cyclization tetrasiloxane, octamethyl cyclization tetrasiloxane, decamethyl cyclization pentasiloxane, tetravinyl tetramethyl cyclization tetrasiloxane and trimethyl trivinyl cyclization tetrasiloxane.
Further, the low-dielectric-constant dielectric layer is selected from Black Diamond with a dielectric constant of 2.7-3.0, the first silicon oxide comprises SiOCH, and the second silicon oxide is represented by SiO in stoichiometric formula x 。
Further, the precursor comprises octamethyl cyclization tetrasiloxane, and the reaction gas comprises O 2 The step of forming the low-k dielectric layer by a chemical vapor deposition process with a radio frequency source includes adjusting octamethyl cyclotetrasiloxane relative to O 2 The flow ratio between them is between 15.6 and 16.9.
Optionally, the apparatus for performing the plasma enhanced chemical vapor deposition process comprises one of an electron cyclotron resonance plasma enhanced chemical vapor deposition device and an inductively coupled discharge plasma enhanced chemical vapor deposition device.
Further, performing the plasma enhanced chemical vapor deposition process using the inductively coupled discharge plasma enhanced chemical vapor deposition apparatus includes: and adjusting the radio frequency power of the plasma enhanced chemical vapor deposition process to be 100kW-150kW.
The invention also provides a manufacturing method of the metal interconnection structure, which comprises the following steps:
according to the method for manufacturing the low-dielectric-constant dielectric layer, an intermetallic dielectric layer is formed on the substrate, and a device layer is also formed on the substrate;
forming a hard mask layer on the intermetallic dielectric layer;
forming a patterned hard mask layer, and selectively etching the intermetallic dielectric layer based on the patterned hard mask layer to form an interconnection through hole penetrating through the intermetallic dielectric layer;
and forming a diffusion barrier layer, a metal seed layer and a metal filler in the interconnection through hole in sequence to form a metal interconnection structure.
Optionally, the manufacturing method further includes: forming a protective layer on the intermetallic dielectric layer before forming the hard mask layer, wherein the protective layer comprises a TEOS layer and SiO 2 One of the layers.
Further, the protective layer and the intermetallic dielectric layer are selectively etched sequentially by adopting a dry etching process, and etching gas used for the dry etching process comprises CF 4 、C 4 F 8 、C 5 F 8 、C 4 F 6 And CHF 3 One or more of the following.
As described above, the manufacturing method of the low-dielectric-constant dielectric layer and the metal interconnection structure has the following beneficial effects:
in the manufacturing method of the low-dielectric-constant dielectric layer, the mechanical strength of the low-dielectric-constant dielectric layer is improved by optimizing the component ratio of the precursor and the oxygen-containing reaction gas in the manufacturing method of the low-dielectric-constant dielectric layer, and the manufacturing method is simple and can meet the requirement of mass production.
The manufacturing method of the metal interconnection structure comprises the steps of manufacturing an intermetallic dielectric layer according to the manufacturing method of the low-dielectric-constant dielectric layer, wherein the intermetallic dielectric layer has hardness close to that of an oxide layer, and deformation caused by mismatch of mechanical strength is reduced; meanwhile, in the subsequent etching process, the etching resistance of the intermetallic dielectric layer is improved, the etching selectivity of the intermetallic dielectric layer relative to the oxide layer serving as the protective layer is reduced, the appearance of a through hole or a groove formed by etching in the intermetallic dielectric layer is improved, the difficulty of the subsequent metal filling process and/or the introduction of holes caused by abnormal etching patterns are avoided, and the electrical performance among elements is improved.
Drawings
Fig. 1 shows an SEM image of an etched cross section of a low-k dielectric layer according to a comparative example of the present invention.
Fig. 2 shows SEM images of metal filling in etched trenches of a low-k dielectric layer according to a comparative example of the present invention.
Fig. 3 shows a table of material properties of low-k dielectric layers of comparative examples and examples of the present invention.
Fig. 4 is a graph illustrating the variation of two silicon oxides with the flow ratio of precursor to reactant gas in an intermetal dielectric layer formed in accordance with an embodiment of the present invention.
Fig. 5 is a graph illustrating the variation of two silicon oxides with rf power in an intermetal dielectric layer formed in accordance with an embodiment of the present invention.
Fig. 6A to 6E are schematic structural diagrams of steps of a method for manufacturing a metal interconnection structure according to an embodiment of the present invention.
Fig. 7 is a SEM image of a structure obtained by the method for manufacturing a metal interconnection structure according to an embodiment of the present invention.
Description of element numbers:
a substrate-300; etching the stop layer-310; an intermetallic dielectric layer-320; interconnect vias-322; a protective layer-330; a hard mask layer-340; a patterned hard mask layer-342; metal filler-350.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of this application, unless otherwise specified and defined, the terms of construction described as "over" a first feature and "a second feature are to be construed broadly, and may include, for example, embodiments in which the first and second features are formed in direct contact, and embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The black diamond is a porous low-dielectric-constant material, and in practical application, the problems of poor thermal stability, poor mechanical strength and the like occur due to low density of a black diamond dielectric layer, the texture of the black diamond dielectric layer is soft, the black diamond dielectric layer is applied to a dielectric material in an interconnection process, deformation can occur in the etching process of the black diamond dielectric layer, or abnormal patterns can occur in the formed etching section, the subsequent diffusion barrier layer, seed layer deposition step and electrochemical plating process are difficult, and even holes (void) appear in a metal interconnection structure, so that the performance and stability of a device are affected. As shown in fig. 1, the etching profile of the low-k dielectric layer of the comparative example is abnormal, the edge of the trench formed by etching is bent, as shown in fig. 2, metal filler is plated in the low-k dielectric layer of the comparative example, and holes are generated in the bending position of the sidewall of the trench in the filling process due to the deformation of the etching profile.
In order to improve the mechanical strength of the low-dielectric-constant dielectric layer and simultaneously manufacture the low-dielectric-constant dielectric layer into an interconnection structure so as to ensure the electrical performance among elements, the invention provides a manufacturing method of the low-dielectric-constant dielectric layer and the metal interconnection structure.
Manufacturing method of low-dielectric-constant dielectric layer
The invention provides a manufacturing method of a low-dielectric-constant dielectric layer, which comprises the following steps:
s100: providing a substrate;
s110: providing a gas mixture comprising a precursor and an oxygen-containing reactant gas;
s120: and introducing the gas mixture into a reaction chamber, and forming a low-dielectric-constant dielectric layer on the substrate through a plasma-enhanced chemical vapor deposition process, wherein the low-dielectric-constant dielectric layer comprises a first silicon oxide and a second silicon oxide containing carbon.
Specifically, in step S100, the substrate 200 may comprise a silicon substrate, a germanium substrate, a silicon germanium substrate, or an insulator substrate, such as a silicon-on-insulator ("SOI") substrate, including but not limited to a silicon-on-sapphire ("SOS") substrate or a silicon-on-glass ("SOG") substrate), an epitaxial silicon layer on a base semiconductor basis, or other semiconductor or optoelectronic materials, such as gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP).
As an example, in step S110, a gas mixture is provided, the gas mixture including a precursor that may be selected from chain-structured silicones and ring-structured silicones, and a reactive gas that may be selected from oxygen-containing gases including, but not limited to, for example, O 2 、N 2 O and CO 2 Wherein the ring structure organosilicon source includes, but is not limited to: for example, selected from tetramethyl cyclized tetrasiloxane, octamethyl cyclized tetrasiloxane (OMCTS), decamethyl cyclized pentasiloxane, tetravinyl tetramethyl cyclized tetrasiloxane, and trisiloxaneAny one of the cyclic structure organosilicon sources of methyl trivinyl cyclization tetrasiloxane.
Step S120 includes: and placing the substrate into a reaction chamber, introducing a gas mixture, forming a Low-dielectric-constant dielectric layer on the substrate through a plasma-enhanced chemical vapor deposition process, and reducing the component content of the first silicon oxide in the Low-dielectric-constant dielectric layer by increasing the content percentage of the reaction gas in the gas mixture so as to enhance the mechanical strength of the Low-dielectric-constant (Low-K) dielectric layer.
Specifically, the apparatus for performing the plasma enhanced chemical vapor deposition process includes one of an Electron Cyclotron Resonance (ECR) plasma enhanced chemical vapor deposition device and an inductively coupled discharge (ICP) plasma enhanced chemical vapor deposition device.
By way of example, the introduction of a source of weakly polarized bonds to the dielectric layer by selection of an appropriate precursor, and the introduction of O doping facilitates the bonding of a cage structure containing Si-O and a Si-O-Si lattice structure in the system, thereby producing changes in the polarizability and porosity. In this example, octamethyl cyclotetrasiloxane (OMCTS) was used as a precursor, O 2 As a reaction gas.
As an example, the gas mixture further includes as a carrier gas, such as helium (He), for carrying the precursor.
As an example, the first silicon oxide is SiOCH and the second silicon oxide is represented by stoichiometric formula SiO x 。
The composition content of the first silicon oxide in the low-dielectric-constant dielectric layer can be adjusted to change the hardness of the low-dielectric-constant dielectric layer, and the dielectric constant of the low-dielectric-constant dielectric layer is not changed obviously. Specifically, by reducing the flow of the precursor relative to the flow of the reactant gas, an increase in the amount of O doping promotes more Si-CH since the precursor in the gas mixture will provide a ring structured organosilicon source 3 The cage structure and the Si-O-Si grid structure converted into Si-O reduce the component content of the first silicon oxide in the low-dielectric constant dielectric layer. In this example, by reducing octamethyl cyclizationTetrasiloxane OMCTS vs O 2 The flow ratio between the two components reduces the component content of SiOCH. With SiO in the obtained black diamond dielectric layer x The component content of the Low-K dielectric material is increased, the hardness of the Low-K dielectric material is closer to that of an oxide, the deformation of the Low-K dielectric layer possibly caused by the mismatch of mechanical strength in an etching process is avoided, and the etching resistance of the Low-K dielectric material can be improved.
Specifically, the tetra-siloxane OMCTS is cyclized relative to O by modulating octamethyl 2 The flow ratio between them is between 15.6 and 16.9, for example 16.0, 16.4 and 16.8, siOCH and SiO in the porous black diamond medium layer x The component content of the porous black diamond dielectric layer is optimized so that the mechanical strength of the porous black diamond dielectric layer is more matched with that of the oxide, and the dielectric constant of the porous black diamond layer is not changed obviously. It should be noted that, the "flow rate" herein may be a mass flow rate and a volume flow rate, which are well known to those skilled in the art, where the flow rates of the precursor and the reaction gas may be based on the physical state of the precursor and the reaction gas and a conventional metering manner in the actual process, so the flow rate ratio of the precursor and the reaction gas herein may be a ratio of the volume flow rate of the precursor to the volume flow rate of the reaction gas, or a ratio of the mass flow rate of the precursor to the volume flow rate of the reaction gas.
As an example, performing a plasma enhanced chemical vapor deposition process using a chemical vapor deposition process with a radio frequency source, i.e., using an inductively coupled discharge (ICP) plasma enhanced chemical vapor deposition apparatus, includes: and adjusting the radio frequency power of the plasma enhanced chemical vapor deposition process to be 100-150 kW so as to reduce the component content of the first silicon oxide in the intermetallic dielectric layer.
The reaction temperature and chamber pressure employed in the plasma enhanced chemical vapor deposition process may be determined based on the film uniformity and deposition rate of the Low-K dielectric layer. In this embodiment, the plasma enhanced chemical vapor deposition process is performed at a reaction temperature of 300 ℃ to 370 ℃ and a chamber pressure of 5Torr or less.
Examples
Here, a black diamond dielectric layer is taken as an example, and the description is givenSpecific details of forming a low dielectric constant dielectric layer by a plasma enhanced chemical vapor deposition process performed in an inductively coupled discharge (ICP) plasma enhanced chemical vapor deposition apparatus, the gas composition introduced into the reaction chamber comprising: octamethyl cyclized tetrasiloxane (OMCTS) as precursor, O as reaction gas 2 And helium (He) as a carrier gas, the process parameters employed are as follows: the radio frequency power is between 125W and 150W, OMCTS/O 2 The flow ratio is between 15.6 and 16.9.
OMCTS and O during deposition 2 The dissociation products of the two interact to deposit porous Black Diamond (Black Diamond), the reaction formula can be expressed by the expressions (1) and (2), respectively, wherein the expression (1) is the main reaction for forming SiOCH, and the reaction product obtained by the expression (2) is SiO x Which constitutes a competing reaction for the formation of SiOCH.
As is known from the expressions (1) and (2), the chemical structure participating in the main reaction includes a cyclic group, a silicon atom, a carbon atom and a hydrogen atom, and the chemical structure participating in the competing reaction includes a cyclic group, which includes a carbon atom and a hydrogen atom, and an oxygen atom. Testing chemical composition and chemical bond variation of low-k dielectric layer by X-ray photoelectron Spectrometry (XPS), siOCH and SiO based on total BD dielectric layer x Is related to the ratio of OMCTS to O 2 The flow ratio and the radio frequency power are shown in fig. 4 to 5, wherein the ratio is an atomic ratio or a mass ratio. Due to the increase of Si-O bonds, the increase of the cage-like structure of Si-O and the increase of the grid structure of Si-O-Si, the change of the material property of the obtained black diamond dielectric layer can change the polarization rate and the porosity.
To illustrate the advantages of the set manufacturing process, for realityThe black diamond dielectric layer material properties of the examples and comparative examples were characterized and the test results obtained are shown in fig. 3. The specific process parameters adopted by the black diamond dielectric layer of the example are as follows: the flow rate of OMCTS is 2700mgm and O is used 2 The gas composition was introduced into the reaction chamber at a flow rate of 160sccm and a plasma enhanced chemical vapor deposition process was performed at a reaction temperature of 350 c and a radio frequency power of 150kW. The process parameters of the black diamond dielectric layer of the comparative example are substantially the same as those of the example, except that: the flow of OMCTS is 2500mgm under the condition of 125kW of radio frequency power.
Analysis of results:
as shown in fig. 3, by optimizing the selected rf power, precursor to oxygen containing reactive gas flow ratio, the resulting BD dielectric layer has improved mechanical strength without significantly affecting its dielectric properties. Specifically, the BD dielectric layer Reflectivity (RI) of the comparative and example changed from 1.4316 to 1.4471, indicating that the BD material properties were significantly changed and the dielectric constant was not significantly changed.
The peak position and peak intensity of XPS spectrum can be used to characterize Si-O and Si- (CH) 3 ) In which Si- (CH) 3 ) Is a characteristic bond representing SiOCH. As can be seen from FIG. 4, with OMCTS and O 2 Is increased, based on the total amount of the BD dielectric layer obtained, siOCH and SiO x The component content of (c) increases and decreases, respectively. Combining expressions (1) and (2) to form SiOCH and SiO in the same system x The reaction of the two components has a competitive relationship, and reduces OMCTS and O 2 The content of SiOCH has a tendency to decrease.
As can be seen from fig. 5, in the example of forming the BD dielectric layer by using the chemical vapor deposition process with the rf source, the process parameters of the rf power in the deposition process are appropriately increased to increase the ionization rate, which is beneficial to si—ch y Dissociation tends to increase the content of siloxane bonds in the product, so that the component content of SiOCH in the intermetallic dielectric layer is reduced. Referring to FIG. 3, it can be seen that the RF power is increased by 20% -36% relative to the RF power used in the comparative example in the plasma enhanced chemical vapor deposition process, siO x Has a content of (3)The mechanical strength of the obtained BD dielectric layer is improved, and the dielectric constant is not changed obviously.
The results show that by controlling OMCTS and O 2 The flow ratio of the two is between 15.6 and 16.9, and the radio frequency power of the PECVD process is between 125W and 150W, so that the content of SiOCH is more than 80 percent based on the total amount of the final film product, wherein the ratio of Si-O bonds is in the range of 28 percent to 41 percent.
Manufacturing method of metal interconnection structure
Thereafter, referring to fig. 6A to 6E, the present invention provides a method for manufacturing a metal interconnection structure, including the following steps:
s200: providing a substrate;
s210: forming an intermetallic dielectric layer on the substrate through a plasma enhanced chemical vapor deposition process, wherein the intermetallic dielectric layer comprises a first silicon oxide containing carbon and a second silicon oxide containing carbon;
s220: depositing a hard mask layer through a physical vapor deposition process to form a patterned hard mask layer, wherein a through hole pattern is defined in the patterned hard mask layer;
s230: selectively etching the intermetallic dielectric layer based on the patterned hard mask layer to form an interconnection through hole;
s240: and forming a diffusion barrier layer, a metal seed layer and a metal filler in the interconnection through hole in sequence to form a metal interconnection structure.
As shown in fig. 6A, referring to the aforementioned step S110, a plasma enhanced chemical vapor deposition process at step S210 may be performed to fabricate an inter-metal dielectric layer 320 on the substrate 300.
As an example, step S210 further includes: an etch stop layer 310 is formed on the substrate 300 prior to forming the inter-metal dielectric layer 320. For example, the etch stop layer 310 may be one of silicon nitride, nitrogen doped silicon carbide (NDC) material, and polysilicon.
As an example, at step S220, the hard mask layer 340 may be formed using a physical vapor deposition process, for example, the physical vapor deposition process may be a reactive sputtering process, and the hard mask layer 340 may include one of a titanium nitride hard mask layer, a tantalum nitride hard mask layer, and a boron nitride hard mask layer.
As an example, step S220 further includes: before forming the hard mask layer 340, a protection layer 330 is formed on the inter-metal dielectric layer 320, the protection layer 330 including a TEOS layer and SiO layer 2 One of the layers. The protective layer 330 may be formed, for example, using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
Then, referring to fig. 6B to 6C, step S230 is performed: a patterned hard mask layer 342 is formed, and the inter-metal dielectric layer 320 is etched based on the patterned hard mask layer 342 to form an interconnect via through the inter-metal dielectric layer.
Specifically, step S230 includes: forming a patterned hard mask layer 342 through a photolithography process and an etching process; the interconnection via 322 is formed by performing a dry etching process using the patterned hard mask layer 342 as a mask, wherein the etching gas used for the dry etching process includes CF 4 、C 4 F 8 、C 5 F 8 、C 4 F 6 And CHF 3 One or more of the following.
Next, referring to fig. 6D, in step S230, the intermetal dielectric layer 320 is selectively etched using a dry etching process using an etchant having a high selectivity to the hard mask material, wherein the intermetal dielectric layer has optimized SiOCH and SiO therein, and an etching rate of the intermetal dielectric material is tens or hundreds of times that of the hard mask layer x As shown in fig. 7, the boundary of the etching section is clearly defined, and the morphology of the through hole in the intermetallic dielectric layer is almost free from deformation.
Referring back to fig. 6D, a protective layer 330 may be further formed between the intermetal dielectric layer 320 and the hard mask layer 340, and the protective layer 330 and the intermetal dielectric layer 320 may be sequentially selectively etched using a dry etching process to form an interconnection via 322, wherein the interconnection via 322 penetrates the protective layer 330 and the intermetal dielectric layer 320 to stop in the etch stop layer 310.In this embodiment, the addition of SiO in the intermetallic dielectric layer is used x The obtained intermetallic dielectric layer has a composition closer to that of oxide and mechanical strength, so that the etching rates of the intermetallic dielectric layer 320 and the protective layer 310 tend to be consistent in the dry etching process, and the abnormal patterns introduced in the etching process are avoided.
As an example, step S230 further includes: after forming the patterned hard mask layer, the residual photoresist is removed by an ashing process. For example, oxygen radicals may be used to remove residual photoresist. In some examples, a protective layer 330 is present between the hard mask layer 340 and the inter-metal dielectric layer 320, and after the step of forming the patterned hard mask layer, the protective layer 330 is exposed in the area of the wafer not covered by the hard mask layer, and the protective layer 330 is present to prevent oxygen radicals used in the photoresist ashing process from damaging the inter-metal dielectric layer 320.
Specifically, referring to fig. 6E, step S240 includes: a diffusion barrier layer, a metal seed layer, and a metal fill 350 are sequentially formed in the interconnect via 322 to form a metal interconnect structure. By way of example, the metal filler material may be any suitable metal material, such as ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), or the like.
By using the manufacturing method of the metal interconnection structure, the clearly defined appearance of the through hole at the boundary can be realized, especially the mechanical strength of the intermetallic dielectric layer is improved, the deformation of the intermetallic dielectric layer and the abnormal etching pattern caused by the mismatch of the mechanical strength are restrained, the metal interconnection structure is formed on the basis of the through hole or the groove with the improved etching pattern, and the risk of introducing holes in the subsequent metal filling process is reduced.
As described above, the method for manufacturing the low-dielectric-constant dielectric layer and the method for manufacturing the metal interconnection structure provided by the invention have the following beneficial effects:
in the manufacturing method of the low-dielectric-constant dielectric layer, the mechanical strength of the low-dielectric-constant dielectric layer is improved by optimizing the component ratio of the precursor and the oxygen-containing reaction gas in the manufacturing method of the low-dielectric-constant dielectric layer.
The manufacturing method of the metal interconnection structure comprises the steps of manufacturing an intermetallic dielectric layer according to the manufacturing method of the low-dielectric-constant dielectric layer, wherein the intermetallic dielectric layer has hardness close to that of an oxide layer, and deformation caused by mismatch of mechanical strength is reduced; meanwhile, in the subsequent etching process, the etching resistance of the intermetallic dielectric layer is improved, the etching selectivity of the intermetallic dielectric layer relative to the oxide layer serving as the protective layer is reduced, the appearance of a through hole or a groove formed by etching in the intermetallic dielectric layer is improved, the difficulty of the subsequent metal filling process and/or the introduction of holes caused by abnormal etching patterns are avoided, and the electrical performance among elements is improved.
Therefore, the invention effectively overcomes several defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A method for manufacturing a low-dielectric-constant dielectric layer is characterized in that: the method comprises the following steps:
providing a substrate;
providing a gas mixture comprising a precursor comprising octamethyl cyclized tetrasiloxane and an oxygen-containing reactive gas comprising O 2 ；
Introducing the gas mixture into a reaction chamber, forming a low-dielectric-constant dielectric layer on the substrate by a plasma-enhanced chemical vapor deposition process, wherein the step of forming the low-dielectric-constant dielectric layer by the chemical vapor deposition process with a radio frequency source comprises adjusting octamethyl cyclization tetrasiloxane relative to O 2 The flow ratio between them is between 15.6 and 16.9, the lowThe dielectric constant dielectric layer comprises a first silicon oxide containing carbon and a second silicon oxide containing carbon;
wherein the component content of the first silicon oxide in the low-k dielectric layer is reduced by increasing the content percentage of the reaction gas in the gas mixture to enhance the mechanical strength of the low-k dielectric layer, the first silicon oxide comprises SiOCH, and the second silicon oxide is represented by stoichiometric formula as SiO x 。
2. The method of manufacturing according to claim 1, wherein: the reaction gas includes O 2 、N 2 O and CO 2 The precursor is selected from any ring structure organic silicon in tetramethyl cyclization tetrasiloxane, octamethyl cyclization tetrasiloxane, decamethyl cyclization pentasiloxane, tetravinyl tetramethyl cyclization tetrasiloxane and trimethyl trivinyl cyclization tetrasiloxane.
3. The method of manufacturing according to claim 2, wherein: the low-dielectric-constant dielectric layer is selected from Black Diamond, and the dielectric constant of the low-dielectric-constant dielectric layer is between 2.7 and 3.0.
4. The method of manufacturing according to claim 1, wherein: the apparatus for performing the plasma enhanced chemical vapor deposition process includes one of an electron cyclotron resonance plasma enhanced chemical vapor deposition device and an inductively coupled discharge plasma enhanced chemical vapor deposition device.
5. The method of manufacturing according to claim 4, wherein: the performing the plasma enhanced chemical vapor deposition process using the inductively coupled discharge plasma enhanced chemical vapor deposition apparatus comprises: and adjusting the radio frequency power of the plasma enhanced chemical vapor deposition process to be 100-150 kw.
6. A method for fabricating a metal interconnect structure, the method comprising:
the method for fabricating a low-k dielectric layer according to any one of claims 1 to 5, wherein an intermetallic dielectric layer is formed on the substrate, and a device layer is further formed on the substrate;
forming a hard mask layer on the intermetallic dielectric layer;
forming a patterned hard mask layer, and selectively etching the intermetallic dielectric layer based on the patterned hard mask layer to form an interconnection through hole penetrating through the intermetallic dielectric layer;
and forming a diffusion barrier layer, a metal seed layer and a metal filler in the interconnection through hole in sequence to form a metal interconnection structure.
7. The method of manufacturing of claim 6, further comprising: forming a protective layer on the intermetallic dielectric layer before forming the hard mask layer, wherein the protective layer comprises a TEOS layer and SiO 2 One of the layers.
8. The method of claim 7, wherein the protective layer and the intermetallic dielectric layer are sequentially selectively etched using a dry etching process, the etching gas used for the dry etching process comprising CF 4 、C 4 F 8 、C 5 F 8 、C 4 F 6 And CHF 3 One or more of the following.
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