CN110880450A - Method for improving ILD oxide layer peeling - Google Patents
Method for improving ILD oxide layer peeling Download PDFInfo
- Publication number
- CN110880450A CN110880450A CN201911192613.9A CN201911192613A CN110880450A CN 110880450 A CN110880450 A CN 110880450A CN 201911192613 A CN201911192613 A CN 201911192613A CN 110880450 A CN110880450 A CN 110880450A
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- CN
- China
- Prior art keywords
- oxide layer
- improving
- peeling
- edge
- ild
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Abstract
The invention discloses a method for improving peeling of an ILD oxide layer, which comprises the following steps: step 1, stacking an oxide layer after ILD0 CMP; step 2, applying a photoresist and exposing to display the middle position without the crystal edge; step 3, removing the oxide layer in the exposed area in an etching mode; and 4, removing the residual photoresist on the wafer edge to thicken the oxide layer on the reserved wafer edge. The invention can effectively improve the follow-up aluminum metal residue and oxide layer peeling.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly to a method for improving oxide layer peeling of an ILD (dielectric layer).
Background
The HK (high dielectric coefficient metal) 28nm product is used as a process (2.2mm) for etching a crystal edge in an STI (shallow trench isolation) process, so that the process continues to be too low and has no pattern in the region in the middle and later stages, a serious collapse problem is generated at the position after the dielectric layer is subjected to zero chemical mechanical polishing, and further, the aluminum metal residue problem after the subsequent aluminum gate mechanical polishing is caused, and a thinner oxide layer is left on the residual aluminum metal because of the lower position after the subsequent dielectric layer is subjected to chemical mechanical polishing, so that the thinner oxide layer is not firm, the structure is damaged in the subsequent contact hole etching process, the oxide layer is peeled off, and further, a hole which is filled with tungsten metal is blocked.
Disclosure of Invention
The present invention provides a method for improving ILD oxide layer peeling, which can effectively improve subsequent aluminum metal residue and oxide layer peeling.
In order to solve the technical problem, the method for improving the peeling of the ILD oxide layer is realized by adopting the following technical scheme:
step 1, stacking an oxide layer after ILD0 (dielectric layer zero) CMP (chemical mechanical polishing);
step 2, applying a photoresist and exposing to display the middle position without the crystal edge;
step 3, removing the oxide layer in the exposed area in an etching mode;
and 4, removing the residual photoresist on the wafer edge to thicken the oxide layer on the reserved wafer edge.
Tungsten metal lines are an important bridge for connecting copper metal layers and devices, and therefore, the tungsten metal lines that are blocked by the dielectric layer so as to be non-conductive will cause the device to fail in performance. In the process of manufacturing the aluminum metal gate, if there is a residue of aluminum metal, short circuit between devices will be caused, and the final electrical performance will be affected. Therefore, by adopting the method of the invention, the oxide layer is thickened through the crystal edge, the following aluminum metal residue and oxide layer peeling can be improved, and the two fatal problems can be improved at the same time.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a flow chart illustrating the method for improving ILD oxide layer exfoliation.
Detailed Description
Referring to fig. 1, the method for improving the ILD oxide layer peeling is implemented in the following embodiments by using the following technical solutions:
step 1, an oxide layer is stacked after ILD0CMP, and the thickness of the stacked oxide layer is
And 2, coating photoresist and exposing to display the middle position without crystal edge. The radius of the edge is larger than 147 mm.
And 3, removing the oxide layer in the exposed area. And removing the oxide layer by adopting an etching mode, wherein the height of the grid electrode is not damaged in specific implementation.
And 4, removing the residual photoresist on the wafer edge, and thickening the oxide layer on the reserved wafer edge.
The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (4)
1. A method for improving peeling of an oxide layer of an ILD, comprising the steps of:
step 1, stacking an oxide layer after ILD0 CMP;
step 2, applying a photoresist and exposing to display the middle position without the crystal edge;
step 3, removing the oxide layer in the exposed area in an etching mode;
and 4, removing the residual photoresist on the wafer edge to thicken the oxide layer on the reserved wafer edge.
2. The method of claim 1, wherein: step 1 the thickness of the oxide layer is
3. The method of claim 1, wherein: and 2, the radius of the crystal edge is larger than 147 mm.
4. The method of claim 1, wherein: the gate height should not be damaged when step 3 is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911192613.9A CN110880450A (en) | 2019-11-28 | 2019-11-28 | Method for improving ILD oxide layer peeling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911192613.9A CN110880450A (en) | 2019-11-28 | 2019-11-28 | Method for improving ILD oxide layer peeling |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110880450A true CN110880450A (en) | 2020-03-13 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911192613.9A Pending CN110880450A (en) | 2019-11-28 | 2019-11-28 | Method for improving ILD oxide layer peeling |
Country Status (1)
| Country | Link |
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| CN (1) | CN110880450A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1064904A (en) * | 1996-08-16 | 1998-03-06 | Sony Corp | Manufacturing method of semiconductor device |
| KR20090035783A (en) * | 2007-10-08 | 2009-04-13 | 주식회사 동부하이텍 | Wafer edge oxide peeling preventing method for cis device |
| CN102361008A (en) * | 2011-10-28 | 2012-02-22 | 上海华力微电子有限公司 | Method for controlling defects of wafer edge |
| CN104201095A (en) * | 2014-09-02 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | Wafer edge etching technique |
| US20150001682A1 (en) * | 2013-06-28 | 2015-01-01 | Taiwan Semiconductor Manufacturing Company Limited | Wafer edge protection structure |
| CN105280476A (en) * | 2015-09-17 | 2016-01-27 | 上海华力微电子有限公司 | Method for improving wafer edge product yield rate |
| CN105742183A (en) * | 2014-12-10 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN109285773A (en) * | 2018-09-12 | 2019-01-29 | 上海华力集成电路制造有限公司 | The manufacturing method of semiconductor devices |
-
2019
- 2019-11-28 CN CN201911192613.9A patent/CN110880450A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1064904A (en) * | 1996-08-16 | 1998-03-06 | Sony Corp | Manufacturing method of semiconductor device |
| KR20090035783A (en) * | 2007-10-08 | 2009-04-13 | 주식회사 동부하이텍 | Wafer edge oxide peeling preventing method for cis device |
| CN102361008A (en) * | 2011-10-28 | 2012-02-22 | 上海华力微电子有限公司 | Method for controlling defects of wafer edge |
| US20150001682A1 (en) * | 2013-06-28 | 2015-01-01 | Taiwan Semiconductor Manufacturing Company Limited | Wafer edge protection structure |
| CN104201095A (en) * | 2014-09-02 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | Wafer edge etching technique |
| CN105742183A (en) * | 2014-12-10 | 2016-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105280476A (en) * | 2015-09-17 | 2016-01-27 | 上海华力微电子有限公司 | Method for improving wafer edge product yield rate |
| CN109285773A (en) * | 2018-09-12 | 2019-01-29 | 上海华力集成电路制造有限公司 | The manufacturing method of semiconductor devices |
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Application publication date: 20200313 |