CN110879310A - Signal power factor acquisition method and device, processor and electronic equipment - Google Patents

Signal power factor acquisition method and device, processor and electronic equipment Download PDF

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Publication number
CN110879310A
CN110879310A CN201911232479.0A CN201911232479A CN110879310A CN 110879310 A CN110879310 A CN 110879310A CN 201911232479 A CN201911232479 A CN 201911232479A CN 110879310 A CN110879310 A CN 110879310A
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signal
reference signal
target
obtaining
component
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颜宁
朱新坡
王宇坤
王鹏
江再玉
马少华
刘佳良
周涛
杨冰
李思维
刘健
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State Grid Information and Telecommunication Co Ltd
Beijing China Power Information Technology Co Ltd
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State Grid Information and Telecommunication Co Ltd
Beijing China Power Information Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/006—Measuring power factor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/133—Arrangements for measuring electric power or power factor by using digital technique

Abstract

The application discloses a method, a device, a processor and electronic equipment for acquiring power factor of a signal, wherein the method is applied to the processor and comprises the following steps: obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal; multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal; obtaining an in-phase component in the first output signal and a quadrature component in the second output signal; and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.

Description

Signal power factor acquisition method and device, processor and electronic equipment
Technical Field
The present disclosure relates to the field of signal processing technologies, and in particular, to a method and an apparatus for acquiring a power factor of a signal, a processor, and an electronic device.
Background
At present, when the power factor of a signal is obtained, the phase difference between two signals of current and voltage, namely the phase angle difference is obtained through phase detection
Figure BDA0002303947240000011
Then, the phase difference needs to be sent to another instrument for power factor acquisition, such as an analog multiplication and division circuit or an analog-to-digital conversion circuit.
Therefore, there may be a case where the connection of elements in the circuit and signal transmission cause signal delay, and the like, thereby resulting in low efficiency of the power factor.
Disclosure of Invention
In view of this, the present application provides a method and an apparatus for acquiring a power factor of a signal, and an electronic device, so as to solve the technical problem in the prior art that the efficiency of the power factor is low due to signal delay caused by connection of circuit elements and signal transmission. As follows:
a method for acquiring a power factor of a signal, applied to a processor, comprises the following steps:
obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal;
multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal;
obtaining an in-phase component in the first output signal and a quadrature component in the second output signal;
and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
The above method, preferably, obtaining the first reference signal and the second reference signal includes:
obtaining a first reference signal, wherein the first reference signal and a target signal to be detected have the same signal frequency;
the first reference signal is phase shifted to obtain a second reference signal.
The above method, preferably, obtaining an in-phase component in the first output signal and a quadrature component in the second output signal, includes:
and respectively filtering the first output signal and the second output signal to obtain an in-phase component in the first output signal and a quadrature component in the second output signal.
The above method, preferably, obtaining the power factor of the target signal according to the in-phase component and the quadrature component, includes:
dividing the in-phase component by the quadrature component to obtain a tangent component;
taking an inverse tangent value of the tangent component;
and taking a cosine value for the arc tangent value to obtain the power factor of the target signal.
In the method, preferably, the signal amplitude of the first reference signal is 1, and the initial phase is 0 degree.
The method preferably, phase-shifting the first reference signal to output a second reference signal, includes:
the first reference signal is phase shifted by 90 degrees to output a second reference signal.
In the above method, preferably, before multiplying the first reference signal by the target signal to obtain a first output signal, the method further includes:
and filtering the target signal to remove a noise signal in the target signal.
An apparatus for obtaining power factor of a signal, applied to a processor, the apparatus comprising:
the signal acquisition unit is used for acquiring a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of the digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal;
the signal multiplying unit is used for multiplying the first reference signal and the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal;
a component obtaining unit for obtaining an in-phase component in the first output signal and a quadrature component in the second output signal;
and the factor obtaining unit is used for obtaining the power factor of the target signal according to the in-phase component and the orthogonal component.
A processor for:
obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal;
multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal;
obtaining an in-phase component in the first output signal and a quadrature component in the second output signal;
and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
An electronic device, comprising:
the memory stores the application program and the data generated by the application program;
a processor for executing the application to perform the functions of: obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal; multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal; obtaining an in-phase component in the first output signal and a quadrature component in the second output signal; and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
According to the technical scheme, after the digital signal processor obtains the reference signals of the two digital signals with the same frequency and different phases, the reference signals are multiplied by the target signal of the digital signal to be detected respectively to obtain the two output signals, then the in-phase component and the quadrature component in the two output signals are obtained, and further the power factor of the target signal is obtained according to the in-phase component and the quadrature component. Therefore, the power factor of the target signal can be acquired by using one electronic device in a digital processing mode, the signal delay caused by signal transmission among a plurality of elements is avoided, the time consumed by signal processing is saved, and the acquisition efficiency of the power factor is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a method for acquiring a power factor of a signal according to an embodiment of the present disclosure;
fig. 2 is another flowchart of a method for acquiring a power factor of a signal according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a signal power factor obtaining apparatus according to a second embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a processor according to a third embodiment of the present application;
FIG. 5 is a schematic diagram of a logic implementation of a processor according to a third embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present application;
fig. 7 is a schematic diagram of connection between an electronic device and a utilization circuit according to a fourth embodiment of the present application;
fig. 8 is a schematic flowchart illustrating a process of performing power factor acquisition on a weak signal according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a flowchart of a method for obtaining a power factor of a Signal according to an embodiment of the present application is shown, where the method is applied to a processor of an electronic device, and the processor may be a chip or a component capable of performing digital Signal processing, such as a microprocessor or a digital Signal processing (dsp). The technical scheme in the embodiment is mainly used for realizing the acquisition of the signal power factor by utilizing the digital demodulation function in the digital signal processor, thereby improving the power factor acquisition efficiency.
Specifically, the method in this embodiment may include the following steps:
step 101: a first reference signal and a second reference signal are obtained.
The first reference signal and the second reference signal are both digital signals, and have the same signal frequency as a target signal of the digital signal to be detected, and a phase difference, such as a phase difference of 90 degrees, exists between the first reference signal and the second reference signal. The signal amplitudes of the first reference signal and the second reference signal are both 1, the initial phase of one of the first reference signal and the second reference signal is 0 degree, and the initial phase of the other corresponding reference signal has a phase different from 0 degree.
Specifically, the processor in this embodiment may utilize the digital signal generator to obtain the first reference signal and the second reference signal of the digital signal.
For example, the target signal may be represented by
Figure BDA0002303947240000051
Which means a digital signal outputted after signal and conditioning by a sampling circuit, a conditioning circuit, etc., where a is the signal amplitude of the target signal, ω corresponds to the signal frequency of the target signal,
Figure BDA0002303947240000052
is the phase of the target signal. Accordingly, using a digital signal generator in the DSPAnd forming a corresponding digital sequence to form a first reference signal and a second reference signal, wherein the signal frequencies of the first reference signal and the second reference signal are both signal frequencies corresponding to omega, and the phases of the first reference signal and the second reference signal are different.
Specifically, in this embodiment, the first reference signal may be obtained by using the digital signal generator first, and may be represented by Ix(t) ═ sin (ω t) denotes when the first reference signal is the same as the target signal with respect to the signal frequency, i.e. ω corresponds to the signal frequency and has an amplitude of 1 and an initial phase of 0 degrees, after which the first reference signal is phase-shifted, e.g. by 90 degrees, to obtain the second reference signal, e.g. for Ix(t) sin (ω t) is phase shifted by 90 degrees to obtain the orthogonal reference signal Iy(t) ═ cos (ω t), the second reference signal at this time is the same as the target signal with respect to the signal frequency, i.e., the signal frequency corresponding to ω.
Step 102: the first reference signal is multiplied by the target signal to obtain a first output signal.
In this embodiment, the first reference signal may be multiplied by the target signal by using a digital circuit multiplier in the processor to obtain the first output signal.
For example, the first reference signal I is multiplied by a digital circuit multiplier in the DSPx(t) ═ sin (ω t) and
Figure BDA0002303947240000061
multiplying to obtain a first output signal
Figure BDA0002303947240000062
And (4) showing.
Step 103: the second reference signal is multiplied by the target signal to obtain a second output signal.
In this embodiment, a multiplier in the processor may be used to multiply the second reference signal with the target signal to obtain a second output signal.
For example, the second reference signal I is multiplied by a digital circuit multiplier in the DSPy(t) ═ cos (ω t) and
Figure BDA0002303947240000063
multiplying to obtain a second output signal
Figure BDA0002303947240000064
And (4) showing.
Step 104: an in-phase component in the first output signal and a quadrature component in the second output signal are obtained.
Specifically, in this embodiment, the obtaining of the in-phase component and the quadrature component may be implemented by a digital low-pass filter in the processor, for example, the first output signal is filtered by the digital low-pass filter in the DSP to obtain the in-phase component in the first output signal, and the second output signal is filtered by the digital low-pass filter in the DSP to obtain the quadrature component in the second output signal.
For example, the first output signal is obtained in the present embodiment
Figure BDA0002303947240000065
In phase component
Figure BDA0002303947240000066
And obtaining a second output signal
Figure BDA0002303947240000067
Quadrature component of (1)
Figure BDA0002303947240000068
Step 105: and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
For example, in this embodiment, corresponding digital calculation processing may be performed on the in-phase component and the quadrature component to obtain the power factor of the target signal.
It can be known from the foregoing solution that, in the method for obtaining a power factor of a signal provided in the first embodiment of the present application, after obtaining reference signals of two digital signals with the same frequency and different phases by using a digital signal processor, the reference signals are respectively multiplied by a target signal of the digital signal to be detected to obtain two output signals, then an in-phase component and an orthogonal component in the two output signals are obtained, and then the power factor of the target signal is obtained according to the in-phase component and the orthogonal component. Therefore, the power factor of the target signal can be acquired by using one electronic device in a digital processing mode, the signal delay caused by signal transmission among a plurality of elements is avoided, the time consumed by signal processing is saved, and the acquisition efficiency of the power factor is improved.
In one implementation, the processor in step 105 may be implemented by:
first, the in-phase component is divided by the quadrature component to obtain a tangent component.
For example, the in-phase component
Figure BDA0002303947240000071
Divided by orthogonal components
Figure BDA0002303947240000072
Obtaining tangent component
Figure BDA0002303947240000073
Then, the arctan value is taken for the tangent component.
For example, for the tangential component
Figure BDA0002303947240000074
Taking the inverse tangent to obtain
Figure BDA0002303947240000075
The value of (c).
And finally, taking the cosine value of the arc tangent value to obtain the power factor of the target signal.
For example, to
Figure BDA0002303947240000076
The cosine value is taken as the value of (A), and the target signal can be obtained
Figure BDA0002303947240000077
Power factor of
Figure BDA0002303947240000078
Is that
Figure BDA0002303947240000079
In addition, the target signal is obtained after sampling and corresponding processing by the sampling circuit and the conditioning circuit, and thus, a noise signal may exist in the target signal, before step 102 and step 103, the method in this embodiment may further include the following steps, as shown in fig. 2:
step 106: and filtering the target signal to remove the noise signal in the target signal.
When the target signal includes a noise signal n (t), x (t) u (t) n (t) may be represented,
Figure BDA00023039472400000710
in this embodiment, x (t) ═ u (t) + n (t) can be filtered by using the demodulation function in the DSP to obtain the target signal with the noise signal n (t) removed for the effective voltage signal in the target signal
Figure BDA00023039472400000711
Referring to fig. 3, a schematic structural diagram of a power factor obtaining apparatus for a signal according to the second embodiment of the present application is provided, where the apparatus may be configured in a processor, and the processor may be a chip or a component capable of performing digital signal processing, such as a microprocessor or a DSP. The technical scheme in the embodiment is mainly used for realizing the acquisition of the signal power factor by utilizing the digital demodulation function in the digital signal processor, thereby improving the power factor acquisition efficiency.
Specifically, the apparatus in this embodiment may include the following functional units:
a signal obtaining unit 301, configured to obtain a first reference signal and a second reference signal.
The first reference signal and the second reference signal are both digital signals, and have the same signal frequency as a target signal of the digital signal to be detected, and a phase difference, such as a phase difference of 90 degrees, exists between the first reference signal and the second reference signal. The signal amplitudes of the first reference signal and the second reference signal are both 1, the initial phase of one of the first reference signal and the second reference signal is 0 degree, and the initial phase of the other corresponding reference signal has a phase different from 0 degree.
Specifically, in this embodiment, the signal obtaining unit 301 may be implemented as a digital signal generator, and is configured to obtain a first reference signal and a second reference signal of the digital signal.
For example, the target signal may be represented by
Figure BDA0002303947240000081
Which means that the digital signal is output after signal and conditioning by the sampling circuit and the conditioning circuit, wherein a is the signal amplitude of the target signal, ω corresponds to the signal frequency of the target signal,
Figure BDA0002303947240000082
is the phase of the target signal. Correspondingly, a digital signal generator in the DSP is used to generate a corresponding digital sequence to form the first reference signal and the second reference signal, where the signal frequencies of the first reference signal and the second reference signal are both signal frequencies corresponding to ω, and the phases of the first reference signal and the second reference signal are different.
Specifically, in this embodiment, the first reference signal may be obtained by using the digital signal generator first, and may be represented by Ix(t) ═ sin (ω t) denotes when the first reference signal is the same as the target signal with respect to the signal frequency, i.e. ω corresponds to the signal frequency and has an amplitude of 1 and an initial phase of 0 degrees, after which the first reference signal is phase-shifted, e.g. by 90 degrees, to obtain the second reference signal, e.g. for Ix(t) sin (ω t) is phase shifted by 90 degrees to obtain the orthogonal reference signal Iy(t) cos (ω t), the second reference signal at this time andthe target signal is the same with respect to the signal frequency, i.e. the signal frequency for ω.
A signal multiplying unit 302, configured to multiply the first reference signal and the target signal to obtain a first output signal, and multiply the second reference signal and the target signal to obtain a second output signal.
In this embodiment, the signal multiplying unit 302 may be implemented as a digital circuit multiplier, and is configured to multiply the first reference signal and the target signal to obtain a first output signal, and multiply the second reference signal and the target signal to obtain a second output signal.
For example, the first reference signal I is multiplied by a digital circuit multiplier in the DSPx(t) ═ sin (ω t) and
Figure BDA0002303947240000091
multiplying to obtain a first output signal
Figure BDA0002303947240000092
Represents;
and using a digital circuit multiplier in the DSP to generate a second reference signal Iy(t) ═ cos (ω t) and
Figure BDA0002303947240000093
multiplying to obtain a second output signal
Figure BDA0002303947240000094
And (4) showing.
A component obtaining unit 303, configured to obtain an in-phase component in the first output signal and a quadrature component in the second output signal.
Specifically, in this embodiment, the component obtaining unit 303 may be a digital low-pass filter in the processor, and further in this embodiment, the in-phase component and the quadrature component may be obtained by the digital low-pass filter in the processor, for example, the first output signal is filtered by the digital low-pass filter in the DSP to obtain the in-phase component in the first output signal, and the second output signal is filtered by the digital low-pass filter in the DSP to obtain the quadrature component in the second output signal.
For example, the first output signal is obtained in the present embodiment
Figure BDA0002303947240000095
In phase component
Figure BDA0002303947240000096
And obtaining a second output signal
Figure BDA0002303947240000097
Quadrature component of (1)
Figure BDA0002303947240000098
A factor obtaining unit 304, configured to obtain a power factor of the target signal according to the in-phase component and the quadrature component.
For example, in this embodiment, corresponding digital calculation processing may be performed on the in-phase component and the quadrature component to obtain the power factor of the target signal.
Specifically, the factor obtaining unit 304 may be implemented by:
first, the in-phase component is divided by the quadrature component to obtain a tangent component. For example, the in-phase component
Figure BDA0002303947240000101
Divided by orthogonal components
Figure BDA0002303947240000102
Obtaining tangent component
Figure BDA0002303947240000103
Then, the arctan value is taken for the tangent component. For example, for the tangential component
Figure BDA0002303947240000104
Taking the inverse tangent to obtain
Figure BDA0002303947240000105
The value of (c).
And finally, taking the cosine value of the arc tangent value to obtain the power factor of the target signal.
For example, to
Figure BDA0002303947240000106
The cosine value is taken as the value of (A), and the target signal can be obtained
Figure BDA0002303947240000107
Power factor of
Figure BDA0002303947240000108
Is that
Figure BDA0002303947240000109
It can be known from the foregoing solution that, in the power factor obtaining apparatus for a signal provided in the second embodiment of the present application, after obtaining the reference signals of two digital signals with the same frequency and different phases through the digital signal processor, the reference signals are respectively multiplied by the target signal of the digital signal to be detected to obtain two output signals, then the in-phase component and the quadrature component in the two output signals are obtained, and then the power factor of the target signal is obtained according to the in-phase component and the quadrature component. Therefore, the power factor of the target signal can be acquired by using one electronic device in a digital processing mode, the signal delay caused by signal transmission among a plurality of elements is avoided, the time consumed by signal processing is saved, and the acquisition efficiency of the power factor is improved.
Referring to fig. 4, a schematic structural diagram of a processor provided in the third embodiment of the present application is shown, where the processor may be a digital signal processor, such as a microprocessor or a DSP, and is connected to a sampling circuit that outputs a target signal to be detected, so as to achieve signal power factor acquisition by using a digital demodulation function in the digital signal processor, and further improve power factor acquisition efficiency.
Specifically, the processor in this embodiment is mainly configured to:
obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal; multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal; obtaining an in-phase component in the first output signal and a quadrature component in the second output signal; and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
In logic, the processor may be divided into a schematic diagram of a structure as shown in fig. 5, in which after a digital signal generator is used in the processor to generate a first reference signal of a digital signal, the first reference signal is phase-shifted by 90 degrees by a phase shifter to obtain a second reference signal, the first reference signal and the second reference signal are further multiplied by a target signal of the digital signal to be detected by digital circuit multipliers, and then pass through digital low-pass filters respectively to obtain an in-phase component and an orthogonal component, and further a power factor is obtained by digital processing.
It can be known from the foregoing solution that, in the processor provided in the third embodiment of the present application, after obtaining the reference signals of the two digital signals with the same frequency and different phases through the digital signal processor, the reference signals are respectively multiplied by the target signal of the digital signal to be detected to obtain two output signals, then the in-phase component and the quadrature component in the two output signals are obtained, and then the power factor of the target signal is obtained according to the in-phase component and the quadrature component. Therefore, the power factor of the target signal can be acquired by using one electronic device in a digital processing mode, the signal delay caused by signal transmission among a plurality of elements is avoided, the time consumed by signal processing is saved, and the acquisition efficiency of the power factor is improved.
Referring to fig. 6, a schematic structural diagram of an electronic device according to a fourth embodiment of the present disclosure is shown, where the electronic device may be a device including a digital signal processor capable of performing digital signal processing, and the processor is connected to a sampling circuit that outputs a target signal to be detected, and is configured to utilize a digital demodulation function in the digital signal processor to achieve signal power factor acquisition, so as to improve power factor acquisition efficiency.
Specifically, the electronic device in this embodiment may include the following structure:
a memory 601 for storing an application program and data generated by the application program;
a processor 602 for executing an application to implement:
obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal; multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal; obtaining an in-phase component in the first output signal and a quadrature component in the second output signal; and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
The electronic device may further include a component, such as a sampling circuit, for outputting a target signal of a digital signal, in addition to the processor 602, based on which the target signal of an analog signal is input to the sampling circuit, passes through an amplifier, a filter and an analog-to-digital conversion circuit, as shown in fig. 7, and is input to the processor 602 in this embodiment, after the processor 602 generates a first reference signal by using a digital signal generator, the first reference signal is phase-shifted by 90 degrees by using a phase shifter to obtain a second reference signal, and then the target signals of the first reference signal, the second reference signal and the digital signal are phase-sensitive detected by using an amplifier algorithm, as shown in fig. 5, after obtaining an in-phase component and a quadrature component, the power factor is calculated to obtain the power factor of the target signal.
It can be known from the foregoing solution that, in the electronic device provided in the fourth embodiment of the present application, after obtaining the reference signals of the two digital signals with the same frequency and different phases through the digital signal processor, the reference signals are respectively multiplied by the target signal of the digital signal to be detected to obtain two output signals, then the in-phase component and the quadrature component in the two output signals are obtained, and then the power factor of the target signal is obtained according to the in-phase component and the quadrature component. Therefore, the power factor of the target signal can be acquired by using one electronic device in a digital processing mode, the signal delay caused by signal transmission among a plurality of elements is avoided, the time consumed by signal processing is saved, and the acquisition efficiency of the power factor is improved.
The following takes a processor as a DSP processor as an example to illustrate the technical solution of the present application:
firstly, in the technical scheme of the application, based on a phase-locked loop amplifier algorithm, the power factor of a weak target signal is acquired: firstly, decomposing an input digital target signal into a voltage component and a noise component; secondly, adding reference current with the same frequency and reference current obtained by a phase shifter according to the frequency of the voltage component of the target signal, and obtaining a corresponding output signal through a multiplier; and finally, filtering the high-frequency signals through filtering to obtain the power factor. Therefore, the technical scheme of the application is simple in control logic and easy to realize digitally, so that the obtaining efficiency and accuracy of the power factor are improved.
As shown in fig. 8, the specific scheme of the present application is implemented as follows:
step 1, formula (1) is an input digital target signal x (t), and specifically, the digital target signal can be obtained through a sampling circuit and the like, and is decomposed into a voltage signal and a noise signal through a phase-locked loop amplifier algorithm:
X(t)＝u(t)+n(t) (1)
Figure BDA0002303947240000131
in the formula (2), u (t) is an input voltage signal with amplitude a, and n (t) is a noise signal.
Step 2, inputting a sinusoidal current reference signal Ix(t) generating a pre-current reference signal I by phase shifting with a phase shiftery(t)：
Ix(t)＝sin(ωt) (3)
Iy(t)＝cos(ωt) (4)
Wherein, the first reference signal I in the formula (3)xThe amplitude of (t) is 1, the initial phase is 0 degree and is the same as the frequency of the digital target signal to be measured, I in the formula (4)y(t) is Ix(t) a quadrature reference signal (second reference signal) obtained by shifting the phase of 90 ° by the phase shifter.
Step 3, multiplying the digital target signal to be detected by the sine and cosine reference signal through a digital circuit multiplier to obtain an output signal Z (t):
Figure BDA0002303947240000132
Figure BDA0002303947240000133
wherein Z in the formula (5)x(t) and Z in the formula (6)y(t) is the corresponding output signal.
And 4, filtering noise components and high-frequency components of the two paths of output signals by a digital low-pass filter to obtain orthogonal components Q (t) in a formula (7) and in-phase components D (t) in a formula (8):
Figure BDA0002303947240000134
Figure BDA0002303947240000135
step 5, calculating the power factor by using the digital phase-locked loop amplifier algorithm according to the following formulas (9) and (10)
Figure BDA0002303947240000141
Figure BDA0002303947240000142
Figure BDA0002303947240000143
Therefore, in the technical scheme of the application, based on the digital phase-locked loop amplifier algorithm, the digital demodulator in the digital signal processor is used for realizing digital signal processing, and the reference signal is realized through the microprocessor or the digital signal generator inside the DSP, so that the design of a hardware circuit is simplified to a certain extent, and the efficiency of acquiring the power factor is improved; meanwhile, circuit elements of the traditional phase-locked loop amplifier are replaced by the digital device in the application, harmonic components are reduced, the condition of direct current drift is avoided, a direct current amplifying circuit is not needed in direct current output, no extra error is generated, and the power factor is more accurately obtained; furthermore, in the technical scheme of the application, the core algorithm of the digital phase-locked loop amplifier is realized through software programming, and the digital phase-locked loop amplifier has the characteristics of convenience in debugging and good flexibility.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method for obtaining a power factor of a signal, applied to a processor, the method comprising:
obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal;
multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal;
obtaining an in-phase component in the first output signal and a quadrature component in the second output signal;
and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
2. The method of claim 1, wherein obtaining the first reference signal and the second reference signal comprises:
obtaining a first reference signal, wherein the first reference signal and a target signal to be detected have the same signal frequency;
the first reference signal is phase shifted to obtain a second reference signal.
3. The method of claim 1, wherein obtaining an in-phase component in the first output signal and a quadrature component in the second output signal comprises:
and respectively filtering the first output signal and the second output signal to obtain an in-phase component in the first output signal and a quadrature component in the second output signal.
4. The method of claim 1, wherein obtaining the power factor of the target signal from the in-phase component and the quadrature component comprises:
dividing the in-phase component by the quadrature component to obtain a tangent component;
taking an inverse tangent value of the tangent component;
and taking a cosine value for the arc tangent value to obtain the power factor of the target signal.
5. The method of claim 1, wherein the first reference signal has a signal amplitude of 1 and an initial phase of 0 degrees.
6. The method of claim 5, wherein phase shifting the first reference signal to output a second reference signal comprises:
the first reference signal is phase shifted by 90 degrees to output a second reference signal.
7. The method of claim 1, wherein before multiplying the first reference signal with the target signal to obtain the first output signal, the method further comprises:
and filtering the target signal to remove a noise signal in the target signal.
8. An apparatus for obtaining power factor of a signal, applied to a processor, the apparatus comprising:
the signal acquisition unit is used for acquiring a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of the digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal;
the signal multiplying unit is used for multiplying the first reference signal and the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal;
a component obtaining unit for obtaining an in-phase component in the first output signal and a quadrature component in the second output signal;
and the factor obtaining unit is used for obtaining the power factor of the target signal according to the in-phase component and the orthogonal component.
9. A processor, configured to:
obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal;
multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal;
obtaining an in-phase component in the first output signal and a quadrature component in the second output signal;
and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
10. An electronic device, comprising:
the memory stores the application program and the data generated by the application program;
a processor for executing the application to perform the functions of: obtaining a first reference signal and a second reference signal, wherein the first reference signal and the second reference signal are digital signals and have the same signal frequency with a target signal of a digital signal to be detected, and a phase difference exists between the first reference signal and the second reference signal; multiplying the first reference signal by the target signal to obtain a first output signal; multiplying the second reference signal by the target signal to obtain a second output signal; obtaining an in-phase component in the first output signal and a quadrature component in the second output signal; and obtaining the power factor of the target signal according to the in-phase component and the quadrature component.
CN201911232479.0A 2019-12-05 2019-12-05 Signal power factor acquisition method and device, processor and electronic equipment Pending CN110879310A (en)

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