CN110865912A - System and method for detecting serial port communication reliability of DSP (digital Signal processor) - Google Patents
System and method for detecting serial port communication reliability of DSP (digital Signal processor) Download PDFInfo
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- CN110865912A CN110865912A CN201911050300.XA CN201911050300A CN110865912A CN 110865912 A CN110865912 A CN 110865912A CN 201911050300 A CN201911050300 A CN 201911050300A CN 110865912 A CN110865912 A CN 110865912A
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- 238000004891 communication Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000012360 testing method Methods 0.000 claims abstract description 25
- 238000001514 detection method Methods 0.000 claims description 4
- 238000012795 verification Methods 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 3
- 230000001186 cumulative effect Effects 0.000 claims 1
- 230000002457 bidirectional effect Effects 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000009825 accumulation Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
The scheme discloses a system and a method for detecting serial port communication reliability of a DSP (digital signal processor). by means of pre-detecting bidirectional data transmission of a serial port chip and a driving circuit, external communication is started after the circuit is ensured to be safe and reliable. The invention is characterized in that the FPGA is used for carrying out communication test on the serial port circuit, and the post switch is opened after the communication test is successful, thereby ensuring the good state of the serial port hardware when the application program is executed and improving the reliability of the system.
Description
Technical Field
The invention relates to a system and a method for detecting serial port communication reliability of a DSP (digital signal processor).
Background
With the high-speed development of embedded computers, the application of technologies based on the DSP is more and more extensive, and the technologies almost permeate into various information fields, including industrial control, information processing, aerospace, communication equipment and other industries. Among them, DSP6000 series processors of TI become a kind of DSP processors widely used.
The common traditional DSP serial port communication design scheme is that a DSP + serial port chip is adopted, and software directly controls the chip to receive and transmit data. Due to the influence of factors such as aging of electronic components, hardware between the DSP and the peripheral interface may have problems, external communication cannot be performed, faults cannot be reported, measurement can be performed only by using tools such as an oscilloscope, and fault detection may be very costly due to the limitation of conditions such as the working environment of equipment.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a system and a method for detecting the serial port communication reliability of a DSP (digital signal processor).
In order to achieve the purpose, the technical scheme of the invention is as follows:
a DSP processor serial port communication reliability detection system comprises: the device comprises a DSP, an FPGA, a serial port chip, a serial port driving circuit and a control switch, wherein the DSP is respectively connected with the serial port chip and the FPGA through an EMIF, and the rear end of the serial port chip is connected with the serial port driving circuit in a cascading manner; the FPGA is also connected with a serial port driving circuit and a control switch and is used for receiving and transmitting signals of the extraction driving circuit, the received and transmitted signals are connected to an interface of the external connector after passing through the control switch, and the FPGA can control the switch; when the power is on, the control switch is closed by default, and the serial port cannot communicate with the outside.
A method for detecting the serial port communication reliability of a DSP processor is characterized in that after a system is powered on, a DSP executes a checking program, and the checking program comprises the following steps:
1) sending first serial port test data to the FPGA;
2) after the FPGA carries out verification judgment on the first serial port test data, reading a first judgment result from the FPGA;
3) reporting an error state if the first judgment result is that the judgment fails; if the judgment is successful, controlling the FPGA to send second serial port test data;
4) receiving second serial port test data, carrying out verification judgment, and determining a second judgment result;
5) reporting an error state if the second judgment result is judgment failure; and if the second judgment result is that the judgment is successful, the control switch is turned on through the FPGA, and then the user program is skipped to execute.
The first serial port test data format is a frame header (0x55) + length (0x64) + content + check + frame tail (0xAA), and the checking is performed in an accumulation sum mode.
And the FPGA receives the check of the calculation length and the content of the test data and compares the check with the received check to form a first judgment result, writes the first judgment result into a result register and waits for the DSP to read the result.
The format of the second serial port test data is frame header (0x33) + length (0x64) + content + check + frame tail (0xCC), and the second serial port test data is checked in an accumulation sum mode.
And the DSP receives the check of the calculation length + content of the test data and compares the check with the received check to form a second judgment result.
And reporting an error state if the judgment fails, wherein an interface is adopted as an LED, and 8 paths are adopted to form 8bit data which represent different errors.
The design idea of the scheme is that the bidirectional data transmission of the serial port chip and the driving circuit is detected in advance, and the circuit starts to communicate with the outside after being safe and reliable.
The invention is characterized in that the FPGA is used for carrying out communication test on the serial port circuit, and the post switch is opened after the communication test is successful, thereby ensuring the good state of the serial port hardware when the application program is executed and improving the reliability of the system.
Drawings
Fig. 1 is a hardware schematic block diagram of a serial port communication reliability detection system of a DSP processor according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method for detecting reliability of serial port communication of a DSP processor according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
As shown in fig. 1, a system for detecting serial port communication reliability of a DSP processor includes: the device comprises a DSP, an FPGA, a serial port chip, a serial port driving circuit and a control switch, wherein the DSP is respectively connected with the serial port chip and the FPGA through an EMIF, and the rear end of the serial port chip is connected with the serial port driving circuit in a cascading manner; the FPGA is also connected with a serial port driving circuit and a control switch and is used for receiving and transmitting signals of the extraction driving circuit, the received and transmitted signals are connected to an interface of the external connector after passing through the control switch, and the FPGA can control the switch; when the power is on, the control switch is closed by default, and the serial port cannot communicate with the outside.
A method for detecting the serial port communication reliability of a DSP processor is characterized in that after a system is powered on, a DSP executes a checking program, and the checking program comprises the following steps:
the method comprises the steps that a check program sends serial port test data, an FPGA receives the data and generates a judgment result, and the check program reads the judgment result from the FPGA; the format of the data sent by the DSP is frame header (0x55) + length (0x64) + content + check + frame tail (0xAA), wherein the length + content is checked and checked in an accumulation sum mode. The FPGA calculates the length + content check and compares the check with the received check, writes the check result into a result register and waits for the DSP program to read the result.
After the serial port test data is successfully judged, the FPGA is controlled by the check program to send the serial port test data, and the check program receives the serial port test data and judges a result; the format of the data sent by the FPGA is frame header (0x33) + length (0x64) + content + check + frame tail (0xCC), wherein the length + content is checked and checked in an accumulation sum mode. The DSP calculates the length + content check and compares it with the received check to form a decision result.
After the verification program is judged successfully, the control switch is turned on through the FPGA, and then the user program is skipped to execute; the user program is a secondary development program of a client, and the system is powered off after the user program is finished.
And if the judgment fails, reporting an error state through other interfaces. The interface is an LED, 8 paths are adopted, 8bit data are formed, and different errors are represented.
Claims (7)
1. A DSP processor serial port communication reliability detection system comprises: the device comprises a DSP, an FPGA, a serial port chip, a serial port driving circuit and a control switch, wherein the DSP is respectively connected with the serial port chip and the FPGA, and the rear end of the serial port chip is connected with the serial port driving circuit in a cascading manner; the FPGA is also connected with a serial port driving circuit and a control switch and is used for receiving and transmitting signals of the extraction driving circuit, the received and transmitted signals are connected to an interface of the external connector after passing through the control switch, and the FPGA can control the switch; when the power is on, the control switch is closed by default, and the serial port cannot communicate with the outside.
2. A method for detecting the serial port communication reliability of a DSP processor is characterized in that after a system is powered on, a DSP executes a checking program, and the checking program comprises the following steps:
1) sending first serial port test data to the FPGA;
2) after the FPGA carries out verification judgment on the first serial port test data, reading a first judgment result from the FPGA;
3) reporting an error state if the first judgment result is that the judgment fails; if the judgment is successful, controlling the FPGA to send second serial port test data;
4) receiving second serial port test data, carrying out verification judgment, and determining a second judgment result;
5) reporting an error state if the second judgment result is judgment failure; and if the second judgment result is that the judgment is successful, the control switch is turned on through the FPGA, and then the user program is skipped to execute.
3. The method of claim 2, wherein the first serial port test data format is frame header (0x55) + length (0x64) + contents + check + frame trailer (0xAA), and the check is performed in a form of a cumulative sum.
4. A method as claimed in claim 2 or 3, wherein the FPGA receives the test data to calculate a check of length + content and compares it with the received check to form a first decision result and writes it into a result register, waiting for the DSP to read the result.
5. The method of claim 2, wherein the format of the second serial port test data is frame header (0x33) + length (0x64) + contents + check + frame tail (0xCC), and the check is performed in a form of summation.
6. A method according to claim 2 or 5, wherein the DSP receives the test data, calculates a check of length + content and compares it with the received check to form a second decision.
7. The method of claim 2, wherein an error status is reported when the determination fails, and 8 paths are adopted to form 8-bit data representing different errors, wherein the interface is an LED.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| CN102759724A (en) * | 2012-07-19 | 2012-10-31 | 浙江省电力公司电力科学研究院 | Testing method and system for communication reliability of intelligent electric energy meters |
| CN104753613A (en) * | 2015-03-21 | 2015-07-01 | 程慧华 | Serial port communication testing device and testing method |
| CN105093094A (en) * | 2015-09-16 | 2015-11-25 | 中国人民解放军国防科学技术大学 | Automatic chip power-on reliability detection device and detection method |
| WO2016086638A1 (en) * | 2014-12-02 | 2016-06-09 | 中兴通讯股份有限公司 | Link detection method, device, and computer storage medium |
| CN105929811A (en) * | 2016-04-06 | 2016-09-07 | 清华大学 | Protection circuit for program deadlock |
| CN108446193A (en) * | 2018-03-05 | 2018-08-24 | 深圳怡化电脑股份有限公司 | A kind of serial ports test system and method |
| CN109388531A (en) * | 2018-09-05 | 2019-02-26 | 天津市英贝特航天科技有限公司 | Test device and its test method based on dsp board card |
| CN109932975A (en) * | 2019-04-04 | 2019-06-25 | 江西理工大学 | A kind of intelligent controller of permanent magnetism magnetic floating track switch |
| CN110196391A (en) * | 2019-06-27 | 2019-09-03 | 中国兵器工业集团第二一四研究所苏州研发中心 | Digital circuit test device and method based on FPGA and DSP architecture |
-
2019
- 2019-10-31 CN CN201911050300.XA patent/CN110865912B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102567280A (en) * | 2010-12-17 | 2012-07-11 | 西安奇维测控科技有限公司 | Computer hardware platform design method based on DSP (digital signal processor) and FPGA (field programmable gate array) |
| CN102759724A (en) * | 2012-07-19 | 2012-10-31 | 浙江省电力公司电力科学研究院 | Testing method and system for communication reliability of intelligent electric energy meters |
| WO2016086638A1 (en) * | 2014-12-02 | 2016-06-09 | 中兴通讯股份有限公司 | Link detection method, device, and computer storage medium |
| CN104753613A (en) * | 2015-03-21 | 2015-07-01 | 程慧华 | Serial port communication testing device and testing method |
| CN105093094A (en) * | 2015-09-16 | 2015-11-25 | 中国人民解放军国防科学技术大学 | Automatic chip power-on reliability detection device and detection method |
| CN105929811A (en) * | 2016-04-06 | 2016-09-07 | 清华大学 | Protection circuit for program deadlock |
| CN108446193A (en) * | 2018-03-05 | 2018-08-24 | 深圳怡化电脑股份有限公司 | A kind of serial ports test system and method |
| CN109388531A (en) * | 2018-09-05 | 2019-02-26 | 天津市英贝特航天科技有限公司 | Test device and its test method based on dsp board card |
| CN109932975A (en) * | 2019-04-04 | 2019-06-25 | 江西理工大学 | A kind of intelligent controller of permanent magnetism magnetic floating track switch |
| CN110196391A (en) * | 2019-06-27 | 2019-09-03 | 中国兵器工业集团第二一四研究所苏州研发中心 | Digital circuit test device and method based on FPGA and DSP architecture |
Non-Patent Citations (6)
| Title |
|---|
| 唐华: "基于DSP与FPGA的开关磁阻电机控制系统设计与优化", 《电工电气》 * |
| 唐华: "基于DSP与FPGA的开关磁阻电机控制系统设计与优化", 《电工电气》, no. 12, 15 December 2011 (2011-12-15) * |
| 李彦等: "基于FPGA和DSP的微振动传感器信号采集系统设计", 《现代电子技术》 * |
| 李彦等: "基于FPGA和DSP的微振动传感器信号采集系统设计", 《现代电子技术》, no. 20, 15 October 2012 (2012-10-15) * |
| 杨硕等: "通用FPGA算法测试平台", 《微计算机信息》 * |
| 杨硕等: "通用FPGA算法测试平台", 《微计算机信息》, no. 20, 20 July 2006 (2006-07-20) * |
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