CN110865518B

CN110865518B - Method and apparatus for detecting overlay of upper and lower layers of a wafer

Info

Publication number: CN110865518B
Application number: CN201911186817.1A
Authority: CN
Inventors: 孟鸿林; 陈翰; 张辰明; 魏芳
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2019-11-28
Filing date: 2019-11-28
Publication date: 2021-12-14
Anticipated expiration: 2039-11-28
Also published as: CN110865518A

Abstract

The invention provides a method for detecting the upper and lower lamination of wafers, which comprises the steps of scanning a set area on the surface of a first layer of graphic wafer, extracting graphic profile data of a first layer of scanning picture, comparing the graphic profile data with first layer of layout data and storing the graphic profile data; continuing the wafer processing to enable the wafer to have a second layer of graphs, scanning the set area on the surface of the wafer with the second layer of graphs, extracting graph outline data of a second layer of scanning pictures, comparing the graph outline data with second layer of layout data, and storing the comparison data; and comparing the first layer of comparison data with the second layer of comparison data in an overlapping relationship and storing. The equipment provided by the invention comprises a storage module, a rasterization module, a matching module, a generation module, a calculation module and an image acquisition module. Therefore, in the flow wafer photoetching process, the process is not changed and the wafer is not damaged, the obtained graphs of all layers are compared with the designed layout, the layers are subjected to overlay comparison, the alignment precision is detected, and the optical proximity correction is carried out.

Description

Method and apparatus for detecting overlay of upper and lower layers of a wafer

Technical Field

The invention relates to the technical field of pattern test data acquisition such as optical proximity correction in process design of semiconductor device manufacturing, in particular to a method for detecting upper and lower layer overlay of a wafer.

The invention also relates to a device for implementing the method for detecting the upper and lower layer stacking of the wafer.

Background

With the continuous decrease of the lithography feature size (CD), the requirements for the alignment precision and the critical dimension uniformity of the lithography machine are also increasing. The fabrication of integrated circuits typically involves several tens of lithographic steps, and in order to ensure the correspondence of the individual levels, overlay accuracy (overlay) matching the lithographic feature size is required. The difference between the exposure pattern and the actual position, i.e. the pattern position offset, is an important factor affecting the alignment precision of the lithography machine and also an important factor affecting the device.

The overlay accuracy of lithography is one of the key parameters for measuring the lithography process, and refers to the offset between the upper and lower patterns on a Wafer (also called silicon Wafer, or Wafer), and the quality of the overlay accuracy will directly affect the performance of the final product. There are many factors that affect overlay accuracy, including: the method comprises the following steps of a heat treatment process except the photoetching process, the quality of film growth, silicon wafer deformation, the quality of an overlay mark of the photoetching process, a photoetching machine alignment mode, the lens thermal expansion of a photoetching machine, the thermal expansion of a mask plate and the like.

Oxidation induced stacking faults during thermal oxidation in silicon single crystals have a significant impact on the performance of transistors and integrated circuits. Extensive research has been carried out to control and eliminate these effects. Generally, the reaction time of the furnace tube or the temperature of the furnace tube is reduced, and the replacement frequency of the reaction chamber of the furnace tube is increased, which have different limitations, which cannot be tolerated in the production process of the integrated circuit. There are many overlay accuracy compensation methods, and usually, only the linear part is compensated, but the non-linear part cannot be compensated, and once the silicon wafer is deformed, the silicon wafer is at risk of being discarded.

Generally, a silicon wafer has a certain oxygen content and a certain amount of impurities, the mechanical hardness of the silicon wafer is directly determined by the oxygen content, the higher the oxygen content is, the stronger the mechanical strength is, the possibility of deformation of the silicon wafer caused by high temperature is smaller or even unchanged, and oxidation stacking faults in the silicon wafer can be inhibited, so that the alignment precision in-plane uniformity of the silicon wafer is better, but the precipitation amount of the impurities of the silicon wafer is also changed greatly, and the impurities are fatal to an integrated circuit. However, if the oxygen content of the silicon wafer is low, the mechanical hardness of the silicon wafer is reduced accordingly, and the degree of deformation of the silicon wafer is increased, which results in a large deformation of the silicon wafer after the high-temperature process. However, the low oxygen content of the silicon wafer can bring less crystal defects, so the oxygen content of the silicon wafer cannot be too low or too high, and the control of the oxygen content of the silicon wafer to improve the alignment precision has certain limitation.

As an important component of the copper damascene process, cmp is mainly used to maintain the thickness of the metal layer and the flatness of the wafer to accommodate the shrinking photolithography process window. The cmp process and design have important interactions and are heavily dependent on the line width and density of the metal. Redundant patterns are usually added in the design to maintain the uniformity of metal density, however, due to the complexity of the cmp process (the properties of the polishing pad, the interaction between the polishing slurry and the metal/insulating medium, long-range effect and stacking effect, etc.), a hot spot of process risk occurs in the manufacturing process, which affects the yield of the product. Particularly, partial areas of the product have smaller chemical mechanical polishing process windows due to the design of the partial areas, and defects such as metal residues, depressions and corrosion are more easily generated in comparison with other areas during process fluctuation. The defects need to be strictly monitored to ensure the yield of the product devices.

At a 28nm node or a more advanced node, selective germanium-silicon epitaxy is carried out on a source electrode region and a drain electrode region, and compressive stress is introduced into a PFET device so as to improve the carrier mobility of the device and further realize higher current driving capability. The laser annealing technology is mainly used for repairing semiconductor materials damaged by ion implantation, particularly silicon, and the traditional heating annealing technology is that the whole workpiece is placed in a vacuum furnace and is subjected to heat preservation annealing at a certain temperature (300-1200 ℃) for 10-60 min. The laser amplified light is directly focused on the surface of a quenched product to instantly generate high-temperature energy so as to change the characteristics of the product. And heating the semiconductor material at a lower temperature without changing the structural state so as to remove the internal stress. However, higher temperature annealing may cause a change in the crystalline state and may also introduce more stress on the surface of the wafer. In fact, the strained silicon technology introduced at the 28nm node also introduces a large stress, especially a three-dimensional (3D) structure, and it is required to ensure not only the alignment of the contact hole to the gate but also the overlay accuracy with the base at the contact hole level, once the stress is large, the current overlay accuracy correction software can only correct 16 parameters, but more high-order nonlinear functions cannot be corrected effectively. This presents a high challenge to the manufacture of semiconductors.

Meanwhile, the advanced process node has a high requirement on the overlay of the upper and lower patterns, so that a position which has a large influence on the patterns needs to be found out, and the positions are properly adjusted in the correction process, so that the whole photoetching process window can be realized. How to find the layouts and how to correct the layouts need to be found from actual wafer data, and the verification is usually completed on a Critical Dimension Scanning Electron Microscope (CDSEM) by predicting the hot spot positions of the layouts, and if the data volume exceeds 1000 points, several weeks are needed for verification.

Wafer fabrication, packaging, and testing are several steps in a semiconductor manufacturing process. The material for producing the chip is a semiconductor, silicon (Si) is the most widely used material, and silicon element is located at the boundary of a metal element region and a non-metal element region in the periodic table of elements, and is suitable for manufacturing transistors with various sizes due to the property of the semiconductor. In the purification of silicon, silicon material is first put into a quartz furnace. The silicon material is melted by seeding the furnace and then grown around the seed until a single crystal silicon ingot is formed. After the silicon ingot is produced, it is shaped into a cylinder and then cut into pieces, which are called wafers or chips. Only the wafer or chip can actually be used in the chip manufacturing process. Generally, the thinner the wafer is ground, the more finished chips can be made from the same amount of silicon material, and the lower the cost of chip fabrication. After the wafer is subjected to heat treatment, a layer of silicon oxide is generated on the surface of the wafer, then a layer of photoresist is coated on the surface of the wafer, ultraviolet rays irradiate the silicon wafer except for a mask plate shielding area, and the photoresist can be dissolved by a developing solution at a position which is usually irradiated by the ultraviolet rays. In order to avoid the light interference in the areas that need not be exposed, these areas need to be masked. This is a very complex process, with data for each reticle being tens of GB or more. The line width variation at each level needs to be monitored, and typically, electron beam scanning (CDSEM) is used for line width measurement in integrated circuit processes. However, a general integrated circuit process includes Active Area (AA)/polysilicon (Poly)/device and metal line Connection (CT) and other key layers, and the alignment precision of these layers has a critical influence on the yield of the chip. Meanwhile, the data size is large and the process window is small at advanced process nodes, which poses a challenge to Optical Proximity Correction (OPC). The expansion of the photoetching process window and even the expansion of the etching process window are required to meet the requirement of the common optical proximity effect correction.

Moreover, because the existing overlay technology can only be used for detecting the overlay relationship between the pattern profile of the layer and the layout data of the layer, the overlay relationship of the pattern profiles on the wafer between different layers cannot be effectively realized. Although measurement can be achieved by judging the overlay relationship among different layers through slicing, the method is a destructive test, the test wafer cannot continue to flow, other wafers cannot be known, meanwhile, the measurement accuracy depends on the experience of an engineer and the degree of manual fitting, and data may have certain fluctuating errors.

The technical problem to be solved by the invention is as follows: the positions where the upper and lower stacks have a large influence on the pattern are found and appropriately adjusted in the course of OPC correction, so that the entire semiconductor process window can be increased.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a method and an apparatus for detecting an upper layer overlay and a lower layer overlay of a wafer, which aims to find out a position where an upper layer overlay and a lower layer overlay have a large influence on a pattern without damaging a test wafer, detect the accuracy of the upper layer overlay and the lower layer overlay, complete appropriate adjustment in time in a compensation and correction process, reduce process design time, and increase a process window.

In order to achieve the above object, the present invention provides a method for detecting an upper layer stack and a lower layer stack of a wafer, comprising the steps of:

step S1, scanning a set region on the surface of the wafer with the first layer of graphics by using an electronic scanning device, extracting the graphic outline data of the first layer of scanned pictures, performing logic operation and data comparison with the first layer of layout data, and storing the obtained comparison data;

step S2, the wafer continues to process to make the wafer have the second layer of graphics, the electronic scanning device is used to scan the set area on the surface of the wafer with the second layer of graphics, the graphics outline data of the second layer of scanned pictures is extracted to be compared with the second layer of layout data for logic operation and data, and the obtained comparison data is stored;

and step S3, carrying out overlay relation comparison on the first layer comparison data and the second layer comparison data, and storing overlay comparison result data.

Preferably, the electronic scanning device emits an electron beam to scan the surface of the wafer, the electronic scanning device is provided with an imaging module, the imaging resolution of the imaging module is less than or equal to 1nm, and the field scanning capacity is greater than or equal to 10 μm.

Preferably, the method further comprises a preprocessing step, wherein the image of the original layout is preprocessed, the image of the original layout is binarized, the outline is extracted and refined, the image is converted into macroscopic graph information, and layout data are respectively formed in each layer.

Preferably, for each layer, the scanning picture is obtained by taking a picture of an actual figure on the wafer through an electronic scanning electron microscope and storing the picture; rasterizing and dividing a vector outline image of a photographed actual graph photo into at least two grid units, and calculating and storing by using a digital histogram and a gray value of an image to form the graph outline data.

Preferably, the data comparison of the graphic profile data and the layout data comprises the following steps: after the graph on the surface of the wafer is scanned, the gray value of the graph is obtained through calculation, fitting is carried out according to the gray value of the graph and the edge of layout data, fitting coefficients are obtained according to an iterative algorithm of transformation coefficients, gray transformation is carried out according to the fitting coefficients, and finally the obtained gray image is the extracted vector outline image.

Preferably, the logic operation of the graphic outline data and the layout data comprises the following steps: and performing logic judgment of superposition alignment on the set region on the first layer scanned picture, the first layer layout data, the second layer scanned picture and the second layer layout data.

Preferably, the process refers to an integrated circuit process step, and the pattern is a photoresist pattern or an etched pattern.

Preferably, in each grid unit, a local deformation degree value of the scanned picture graph is determined, the shape dissimilarity degree of the scanned picture graph and the layout data is determined by calculating an overlay graph of the scanned picture graph and the layout data, and a contour graph is selected based on the shape dissimilarity degree and the local deformation degree value.

In order to achieve the above object, the present invention further provides an apparatus for detecting an upper and lower layer stack of a wafer, comprising:

the storage module comprises an original layout storage unit, a vector outline map storage unit and a calculation result storage unit;

the rasterization module is used for rasterizing the vector outline image and dividing the vector outline image into at least two grid units; drawing the vector outline by extracting the central line of the vector outline and using a line with the same thickness as the original layout;

the matching module is used for matching each vector contour map with the original layout map by utilizing a logarithm-polar coordinate histogram;

the generating module is used for combining all matched original layouts and vector outline maps to form an overlay map;

and the calculation module is used for calculating the overlay precision among the layers according to the logical relationship among the overlay graphs.

Preferably, the log-polar histogram means,

the wafer is provided with sampling points; the log-polar coordinate window has intervals, and the intervals are uniformly divided in the log-polar coordinate window;

the sampling points have feature vectors, the feature vectors include components, the components are the gray value summation in one interval of the corresponding log-polar coordinate window of the sampling points, and the components are the values of the histogram.

Preferably, the calculation module calculates feature vectors of each sampling point in the overlay image by using the log-polar histogram, and solves the discrete optimization problem by using a simulated annealing model based on the feature vectors.

Preferably, the calculation module includes a gray level adjustment unit, and adjusts the brightness of the graph in the scanning range according to the graph density of the whole original layout, and the comparison between the graph gray level value in the scanning range and the graph gray level value around the scanning range.

Preferably, the calculation module includes a process-pattern density-darkness correspondence database, the calculation module reads the original pattern from the storage module and calculates the pattern density of the original pattern, and the corresponding sensitivity is obtained by combining the processes of each layer.

Preferably, the calculation module screens out the position where the upper and lower stacking pairs between the first layer and the second layer have influence according to the gray level of each sampling point in the graph, and filters out the sampling points with the gray level threshold value of the graph being less than 50%.

Preferably, the matching module performs logic operation according to the original layout, matches each vector profile graph with the original layout graph by using a logarithm-polar coordinate histogram, and reserves sampling points with the matching degree of more than 50%.

Preferably, the matching module further comprises an alignment unit, the alignment unit performs overlay on the contour map acquired on the wafer after amplifying the original layout, more than 80% of the original layout comprises the contour map and enters the matching module for matching, and the amplification factor is-1000- + 1000.

Preferably, the calculation module calculates a comparison and an overlay relationship between one layer of the graph outline on the wafer and each layer of the original layout, and calculates an overlay accuracy of the graph outline between different layers and a relationship between an upper layer coverage and a lower layer coverage, and a coordinate system used in the calculation process is an alignment system based on the wafer, that is, the data of each layer of the layout is aligned with the graph of the wafer on the layer.

In order to achieve the above object, the present invention further provides an apparatus for detecting an upper layer and a lower layer of a wafer, including a picture acquiring module, where the picture acquiring module includes: a high-speed electron gun, an infrared induction device and a large-field scanning device;

the infrared induction device is used for extracting the graphic outline of the first layer covered by the second layer through infrared induction;

the high-speed electron gun emits high-speed high-energy electron beams, the wafer is scanned through the high-speed high-energy electron beams, and the large-field scanning device detects the distribution of electrons on the surface of the wafer to extract the figure outline.

Preferably, a high-reflectivity material is added into the first layer of pattern, and the high-reflectivity material is tungsten, aluminum or copper.

Preferably, the large field scanning device further comprises a reflection electron collecting device, a magnetic material is added into the first layer of pattern, the high-speed electron gun emits emission electrons to the surface of the wafer, the reflection electron collecting device collects an electric field formed by a zero-order reflection signal of the electrons emitted by the large field scanning device on the surface of the wafer and a model zero-order reflection signal, and the electric field signal enters the operation system to extract the pattern profile of the first layer covered by the second layer;

the magnetic material is any one or combination of several of NiFe, Co, Fe or Ni.

Compared with the prior art, the invention provides a method for detecting the upper layer and the lower layer of the wafer, which comprises the following steps: step S1, scanning a set region on the surface of the wafer with the first layer of graphics by using an electronic scanning device, extracting the graphic outline data of the first layer of scanned pictures, performing logic operation and data comparison with the first layer of layout data, and storing the obtained comparison data; step S2, the wafer continues to process to make the wafer have the second layer of graphics, the electronic scanning device is used to scan the set area on the surface of the wafer with the second layer of graphics, the graphics outline data of the second layer of scanned pictures is extracted to be compared with the second layer of layout data for logic operation and data, and the obtained comparison data is stored; and step S3, carrying out overlay relation comparison on the first layer comparison data and the second layer comparison data, and storing overlay comparison result data. Therefore, according to the method for detecting the upper layer and the lower layer of the wafer, in the wafer flowing process, in the photoetching process, the process is not changed, the wafer is not subjected to destructive slicing, the graphs of all layers are subjected to nondestructive scanning, the obtained graphs of all layers are compared with the designed domain, then the overlay comparison is carried out on the graphs manufactured on all layers on the basis of the original domain, the overlay accuracy among all layers can be detected, and the graph adjustment such as optical proximity correction is carried out according to the overlay accuracy.

Compared with the prior art, the invention also provides equipment for detecting the upper layer and the lower layer of the wafer, which comprises the following components: the storage module comprises an original layout storage unit, a vector outline map storage unit and a calculation result storage unit; the rasterization module is used for rasterizing the vector outline image and dividing the vector outline image into at least two grid units; drawing the vector outline by extracting the central line of the vector outline and using a line with the same thickness as the original layout; the matching module is used for matching each vector contour map with the original layout map by utilizing a logarithm-polar coordinate histogram; the generating module is used for combining all matched original layouts and vector outline maps to form an overlay map; and the calculation module is used for calculating the alignment precision between the layers according to the overlay graph. Therefore, according to the device for detecting the upper layer and the lower layer of the wafer, the obtained vector outline of each layer can be compared with the designed layout on the basis of detecting the vector outline of each layer, and the overlay comparison between the patterns manufactured on each layer is carried out on the basis of the original layout, so that the overlay accuracy between the layers can be detected, and the pattern adjustment such as optical proximity correction can be carried out according to the overlay accuracy.

Compared with the prior art, the invention also provides equipment for detecting the upper layer and the lower layer of the wafer, which comprises a picture acquisition module, wherein the picture acquisition module comprises: a high-speed electron gun, an infrared induction device and a large-field scanning device; the infrared induction device is used for extracting the graphic outline of the first layer covered by the second layer through infrared induction; the high-speed electron gun emits high-speed high-energy electron beams, the wafer is scanned through the high-speed high-energy electron beams, and the large-field scanning device detects the distribution of electrons on the surface of the wafer to extract the figure outline. Therefore, the vector contour map can be extracted, the multi-layer graphic contour can be extracted and compared with the original layout, the alignment precision among layers can be detected, and the graphic adjustment such as optical proximity correction can be performed according to the alignment precision.

Drawings

FIG. 1A is a layout of an integrated circuit comprising a stack of Poly layers and CT layers.

Fig. 1B is a photograph of a wafer profile after a stack comprising Poly layers and CT layers is stacked.

Fig. 2A is a graphical outline on a two-layer wafer.

FIG. 2B is a comparison of the outline of the pattern on the wafer in one grid cell of one of the layers with the original layout.

FIG. 2C shows the overlay result of the pattern profiles of different levels on the wafer finally formed by the method of the present invention.

FIG. 3 is a diagram of an embodiment of an apparatus for inspecting a wafer stack according to the present invention.

FIG. 4 is a schematic diagram of a back-scattered electron collection device for obtaining a wafer photograph in an apparatus of the present invention.

Fig. 5A and 5B are schematic diagrams of a method of scanning a front layer (first layer) picture covered with a second layer by an electric field according to the present invention, in which electrons are collected at a magnetic substance and the electric field of the electrons is measured.

FIG. 6A is an overlay of an original layout according to an embodiment of the present invention.

FIG. 6B is a top-down layer pair of images of a wafer showing an embodiment of the method of the present invention.

Fig. 7A is a schematic diagram of a method for rasterizing and dividing grid cells by using a comparison picture of an original layout and a wafer pattern in another embodiment of the method provided by the present invention, wherein a front layer is a device-to-metal line connection part layer (CT), and the method is to detect the front layer by an infrared detection device.

Fig. 7B shows the layout and wafer photo outline after one of the grid cells has been enlarged by a certain factor.

Fig. 7C is a comparison of the final resulting one whole block layout and wafer photo.

Description of the reference numerals

11 Poly (Poly) 12 device to metal line connection layering

21 graphic outline 22 original layout (GDS format)

31 high-speed electron gun 32 condenser front hole

33 condenser 34 final aperture

35 electronic baffle 36 wafer slide holder

37 slide holder telecontrol equipment 38 back scattered electron collection device

39 infrared detector 41 incident electrons

42 sample 43 backscattered electrons

51 wafer 52 electrons

53 field attachment with patterned portion 54 (Carryover)

Design layout of active region 61 photo outline of active region 62

71 grid cell 72 design layout

73 photo outline

Detailed Description

The following describes a preferred embodiment of the present invention in detail with reference to the accompanying drawings. It is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, without affecting the spirit of the invention, using the methods and techniques disclosed above, without departing from the scope of the invention.

Referring to fig. 1A and fig. 1B, fig. 1A is a picture of an original layout (layout design of integrated circuit, layout), which shows a layout diagram of the polysilicon layer (Poly)11 and the device and metal line connection portion layer (CT)12 of the original layout in an overlapping manner; fig. 1B is a top-bottom image of a photo actually produced from a Wafer (Wafer) using the inspection method of the present invention, which also includes a polysilicon layer (Poly) and a device-to-wire connection layer (CT), and the Wafer itself is opaque, so that only the patterned wire Connection (CT)12 of this layer is shown. The embodiment of the method for detecting the upper and lower layer overlay of the wafer provided by the invention mainly comprises the following steps: the original layout data is preprocessed, and after image binarization, outline extraction, thinning and other processing are carried out, image information is converted into macroscopic graph information. Rasterizing the vector outline graph and dividing the vector outline graph into a plurality of grid units, wherein at least one grid unit is provided with a corresponding original layout graph; matching each original layout reference graph with a vector contour graph by utilizing a logarithm-polar coordinate histogram; and calculating all matched vector contour maps and overlay maps of the original layout.

Referring to FIGS. 2A, 2B, and 2C, FIG. 2A shows a pattern profile on a two-layer wafer; FIG. 2B shows the comparison of the pattern profile on the wafer in one grid cell of one layer with the original layout, logic matching, and screening out points with a predetermined value of overlap ratio (above 80%); fig. 2C shows the overlay result of the pattern profiles of different levels on the wafer finally formed by the method of the present invention. The method comprises the following specific steps:

1. and scanning a specific area of the surface of the wafer with the first layer of graph by using an electronic scanning device, extracting a vector outline graph of a scanned picture, comparing the vector outline graph with layout data, performing logical operation, and storing the data.

2. And continuously carrying out subsequent processes on the wafer to enable the wafer to have a second layer of graphs, continuously scanning the region by using an electronic scanning device, extracting the graph outline of the scanned picture, and carrying out logic operation and data comparison on the graph outline and layout data.

3. If there is a third layer pattern or more, the step S2 is repeated. That is, the wafer continues to perform subsequent processes to make the wafer have a third layer of graphics (a new second layer is processed on the second layer and defined as a third layer), the region is continuously scanned by using an electronic scanning device, and the graphic profile of the scanned picture is extracted and is subjected to logic operation and data comparison with layout data.

4. And rasterizing and dividing the vector outline image into a plurality of grid cells, and calculating and storing by using the digital histogram and the gray value of the image.

5. The positions and shapes of the graphics sensitive to the overlay relationship between the 2-layer graphics or between the graphics over 2 layers are determined, and the results are stored in a storage unit.

6. These results are fed back to an automated electronic design end (EDA end), the target values of these patterns are adjusted using EDA software, and usual Optical Proximity Correction (OPC) correction is performed in a subsequent OPC process.

The length measuring instrument adopted by the invention can not only reduce the charged influence on the surface of the wafer and obtain a high-resolution image, but also realize the large-field scanning capability (the scanning area is more than 10um) and higher data processing capability.

Referring to fig. 3, the apparatus for detecting the upper and lower layer stacking of the wafer according to the present invention mainly comprises: a high-speed electron gun 31, a condenser front hole 32, a condenser 33, a final hole 34, an electron baffle 35, a wafer stage 36, a stage moving device 37, a back scattered electron collecting device 38 and an infrared detection device 39. The high-speed electron gun 31 emits a high-speed, high-energy electron beam to the surface of the wafer on the wafer stage 36. The stage moving device 37 is movable in XYZ directions to facilitate block-by-block scanning.

Referring to FIG. 4, the backscattered electron collection device 38 is an important component of a large field scanning device. When a high energy electron beam irradiates the sample, incident electrons 41 undergo diffraction within the sample 42, changing direction and losing a portion of their energy in the case of inelastic scattering. During such elastic and inelastic scattering, some of the incident electrons will escape from the sample surface as backscattered electrons 43 with cumulative scattering angles exceeding 90 degrees.

The infrared detection device 39 detects the shape of the object using the following principle: all objects above absolute zero emit infrared radiation. Generally, when the temperature is lower than 300K, the emissivity of the metal oxide is generally larger than 0.8, and the emissivity of the nonmetallic dielectric material is about 0.9. And detecting the shapes of different materials according to different emissivity of the different materials.

Referring to fig. 5A, electrons 52 are emitted onto a wafer 51 by a high-speed electron gun 31, and a magnetic material is added to a patterned portion 53 of a first layer on the wafer 51. Referring to fig. 5B, the patterned first layer 53 has more electrons 52 attached to it, forming an electric field attachment (Carryover) 54. The principle of adding magnetic material to measure the figure profile of the front layer is that the shape part of the first layer (front layer) has magnetic substance distribution, the magnetic material collects electrons emitted when scanning the first layer, the external electric field can enhance the effect, and after the second layer is covered, the figure conditions of the first layer and the second layer can be measured simultaneously by measuring the condition of the electron collection distribution on the first layer.

Referring to fig. 6A and 6B, an embodiment of a process design for an integrated circuit using the method for detecting a top-to-bottom stack of a wafer according to the present invention is shown. FIG. 6A shows a graph comparing an original layout with a wafer photograph; fig. 6B shows the pattern of the upper and lower overlay of the wafer photograph, with only the active area of wafer photograph 62 taken at the active area AA level. The integrated circuit comprises a polycrystalline silicon layer (Poly), an Active Area (AA), and a device and metal wire connecting part (CT). The design layout 61 of the active region in the original layout overlay is compared with the wafer photo 62 of the active region by logical operation. One technical problem in the illustrated process design is to determine the distribution of process weaknesses for the polysilicon layer (Poly) to the Active Area (AA), and for the device and metal line Connections (CT) to the Active Area (AA). The active region layer (AA) is a so-called first layer (front layer) of the present invention, and the polysilicon layer (Poly) is a so-called second layer (second layer formed on the basis of the first layer) of the present invention; the device and metal line connection portion (CT) is formed by performing a subsequent process on the basis of the polysilicon layer (Poly), and at this time, the device and metal line connection portion (CT) corresponds to a second layer (in the case where the polysilicon layer is defined as a first layer) referred to in the present invention, and stacking of a plurality of layers may be performed by using a common layer as a medium.

First, the integrated circuit process proceeds with the normal process flow. When proceeding to the polysilicon layer (Poly), the electronic scanning device of the present invention, a length measuring instrument with large field scanning capability and high data processing capability, is required. When the polysilicon layer (Poly) is scanned, because the polysilicon layer (Poly) pattern of the layer can be scanned by the layer (second layer), and the pattern of the front active area layer (AA) can also be scanned, the corresponding original layout polysilicon layer (Poly) and active area layer (AA) are composed of 2 layers. And scanning a specific area of the surface of the wafer with the first layer of graph by using an electronic scanning device, extracting a vector outline graph of a scanned picture, comparing the vector outline graph with layout data, performing logical operation, and storing the data. Therefore, when the alignment is realized, logical operation needs to be performed on the outlines of the two layers of layouts respectively, namely, a part for realizing 80% successful graph comparison is realized by only retaining the graph outline of the polysilicon layer (Poly) and comparing the graph outline with the original layout of the polysilicon layer (Poly), and a part for realizing 80% successful graph comparison is realized by only retaining the graph outline of the active area layer (AA) and comparing the graph outline with the original layout of the active area layer (AA).

And then rasterizing the vector outline graph and dividing the vector outline graph into a plurality of grid units, calculating the original layout corresponding to each layer by using the digital histogram and the gray value of the image, comparing the graph outline on the actual wafer with the original layout corresponding to each layer, and storing the graph outline.

These results are fed back to an automated electronic design end (EDA end), the target values of these patterns are adjusted by EDA software, and normal OPC correction is performed in the subsequent OPC processing.

At this time, the subsequent device and metal wire connection part (CT) process is continued on the basis of the polysilicon layer (Poly), and because the CT process covers a thicker oxidation layer which is not light-tight, the electronic scanning device provided by the invention cannot directly detect the figure outline of the lower figure and compare the figure outline with the original layout. The invention provides a method, through adding appropriate magnetic substance while making the polycrystalline silicon layer (Poly), when the scanning detection to CT level, the electronic scanning equipment of the invention is while scanning the surface of the crystal plate, because the lower layer figure contains magnetic substance or metallic substance, and our apparatus is equipped with the high-speed electron gun, the electron distribution on polycrystalline silicon layer (Poly) (front layer of CT layer) of the high-speed electron gun, under the influence of magnetic material and electric field, the electronic scanning equipment that the invention provides can scan to many electron distributions on having magnetic substance. Referring to the figures, the layout design pattern is shown for the combination of polysilicon (Poly) and device and metal line Connections (CT), and the wafer pattern is shown for the scan of the combination of polysilicon (Poly) and device and metal line Connections (CT).

Referring to fig. 7A, 7B and 7C, an embodiment of a process design for an integrated circuit using the method for detecting a top-to-bottom overlay on a wafer according to the present invention is shown. Fig. 7A, 7B, and 7C show the pattern of after-etching detection (AEI) of the device and metal line connection part layer (CT). FIG. 7A is a graph comparing an original layout and a wafer pattern, wherein the original layout and wafer pattern are rasterized and divided into at least two grid cells 71, typically dividing FIG. 7A into 60 grid cells 71; fig. 7B is a diagram showing that after a selected grid cell 71 is amplified by a certain factor (less than or equal to 1000 times), a design layout 72 in a vector diagram format of the layer (first layer) of devices and the metal wire connection part layer (CT) is compared with a picture outline 73 in the vector diagram format; referring to fig. 7C, a comparison result of the whole layout and the wafer photo is finally formed and stored. And a picture of the device and metal line connection part layer (CT) in the wafer is obtained by the following method provided by the present invention. The integrated circuit comprises a second Metal layer (Metal 2, M2 for short), a device and Metal line connection part layer (CT), and a first Metal layer (Metal 1, M1 for short). One technical problem in process design is to determine the process vulnerability profile of the device to metal line connection part layer (CT), the second metal layer (M2) to the first metal layer (M1). The second metal layer (M2) is generated in a subsequent process of the metal line connection part layer (CT) or the first metal layer (M1).

First, the integrated circuit process proceeds with the normal process flow. When proceeding to the second metal layer (M2), the electronic scanning device of the present invention, a large field scanning capability, high data processing capability length gauge, is required. Since this layer can only scan to this layer second metal layer (M2). The electronic scanning device provided by the invention is provided with an infrared sensing device, and can obtain the pattern profile of the front layer metal wire connecting part layer (CT) or the first metal layer (M1) by scanning a wafer. The alignment of the pattern outline and the layout can be obtained according to the optimal matching diagram principle, namely, the original layout is firstly amplified or reduced, the matching is carried out when the original layout can completely cover the pattern outline of the actual wafer, and the overlay processing is carried out when the matching degree is more than 80 percent. And then rasterizing the vector outline graph and dividing the vector outline graph into a plurality of grid units, calculating the original layout corresponding to each layer by using the digital histogram and the gray value of the image, comparing the graph outline on the actual wafer with the original layout corresponding to each layer, and storing the graph outline.

And feeding the results back to an EDA end, adjusting the target values of the graphs by using EDA software, and performing common OPC correction in subsequent OPC treatment.

The above is the method and apparatus for detecting the upper and lower layer stacking of the wafer provided by the present invention.

The invention achieves the following technical effects:

firstly, according to the method for detecting the upper layer and the lower layer of the wafer, in the process of flow, in the process of photoetching technology, the technology is not changed and the wafer is not subjected to destructive slicing, the graphs of each layer are subjected to nondestructive scanning, so that the obtained graphs of each layer are compared with a designed domain, then, the overlay comparison is carried out on the graphs manufactured on each layer on the basis of an original domain, so that the overlay accuracy between each layer can be detected, and the graphs such as optical proximity correction and the like can be adjusted according to the overlay accuracy. The process weakness (the pattern type and the position with poor alignment precision and strong alignment precision sensitivity) can be found, the position of the process weakness and the correction direction also need to be fed back, and the target value can be increased or decreased by the selected pattern, so that a greater degree of freedom is given in the subsequent OPC correction, and a greater process window can be obtained finally.

Secondly, according to the equipment for detecting the upper layer and the lower layer of the wafer, the obtained vector outline of each layer can be compared with the designed layout on the basis of detecting the vector outline of each layer, and the overlay comparison between the patterns manufactured on each layer is carried out on the basis of the original layout, so that the overlay accuracy between the layers can be detected, and the pattern adjustment such as optical proximity correction can be carried out according to the overlay accuracy.

Thirdly, a vector outline graph can be extracted, multi-layer graph outlines can be extracted, and then the multi-layer graph outlines are compared with an original layout, so that the alignment precision among layers is detected, and graph adjustment such as optical proximity correction is carried out according to the alignment precision.

The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting an upper and lower layer stack on a wafer, comprising the steps of:

step S3, comparing the first layer comparison data with the second layer comparison data in an overlay relationship, and storing the overlay comparison result data;

the electronic scanning device comprises an infrared sensing device and a back scattered electron collecting device.

2. The method as claimed in claim 1, wherein the electronic scanning device emits an electron beam to scan the surface of the wafer, and the electronic scanning device has an imaging module with an imaging resolution of 1nm or less and a field scanning capability of 10 μm or more.

3. The method of claim 1, further comprising a preprocessing step of preprocessing the image of the original layout, binarizing the image of the original layout, extracting and refining the contour, converting the image into macroscopic graphic information, each layer forming the layout data, respectively.

4. The method of claim 1, wherein the scanning images are obtained by taking pictures of actual patterns on the wafer by an electronic scanning electron microscope and storing the pictures for each layer; rasterizing and dividing a vector outline image of a photographed actual graph photo into at least two grid units, and calculating and storing by using a digital histogram and a gray value of an image to form the graph outline data.

5. The method of detecting on-wafer and off-wafer stacking as recited in claim 1, wherein the data comparing the layout data to the graphic profile data comprises the steps of: after the graph on the surface of the wafer is scanned, the gray value of the graph is obtained through calculation, fitting is carried out according to the gray value of the graph and the edge of layout data, fitting coefficients are obtained according to an iterative algorithm of transformation coefficients, gray transformation is carried out according to the fitting coefficients, and finally the obtained gray image is the extracted vector outline image.

6. The method of detecting on-wafer and off-wafer stacking as recited in claim 1, wherein the performing a logical operation on the layout data and the graphic profile data comprises the steps of: and performing logic judgment of superposition alignment on the set region on the first layer scanned picture, the first layer layout data, the second layer scanned picture and the second layer layout data.

7. The method of claim 1, wherein the process is an integrated circuit process step, and the pattern is a photoresist pattern or an etched pattern.

8. The method as claimed in claim 4, wherein in each grid cell, determining a local distortion degree value of the scanned picture pattern, calculating the overlay of the scanned picture pattern and the layout data to determine the shape dissimilarity between the scanned picture pattern and the layout data, and selecting the contour map based on the shape dissimilarity and the local distortion degree value.

9. An apparatus for detecting an upper and lower layer stack on a wafer, comprising:

the matching module is used for matching each vector contour map with the original layout map by utilizing the logarithm-polar coordinate histogram;

the calculation module is used for calculating the overlay precision among the layers according to the logical relation among the overlay graphs;

the device for detecting the upper and lower layer stacks of the wafer adopts the method for detecting the upper and lower layer stacks of the wafer as claimed in claim 1 to obtain the scanning pictures of each layer.

10. The apparatus of claim 9, wherein the log-polar histogram indicates the number of stacked layers on the wafer,

11. The apparatus of claim 10, wherein the computing module computes feature vectors for each sampling point in the overlay image using log-polar histograms, and based on the feature vectors, uses a simulated annealing model to solve the discrete optimization problem.

12. The apparatus of claim 9, wherein the computing module comprises a gray scale adjustment unit to adjust the intensity of the pattern within the scan range based on the pattern density of the entire original layout and the comparison of the pattern gray scale values within the scan range with the surrounding pattern gray scale values within the scan range.

13. The apparatus according to claim 12, wherein the calculation module includes a process-pattern density-darkness correspondence database, the calculation module reads the original pattern from the storage module and calculates the pattern density of the original pattern, and the corresponding sensitivity is obtained by combining processes of each layer.

14. The apparatus of claim 12, wherein the computing module filters out the position of the influence of the upper and lower stacking pairs between the first layer and the second layer according to the gray level of each sampling point in the pattern, and filters out the sampling points with the gray level threshold of the pattern less than 50%.

15. The apparatus according to claim 12, wherein the matching module performs a logic operation according to the original layout, matches each vector profile with the original layout pattern using log-polar histogram, and retains the sampling points with a matching degree greater than 50%.

16. The apparatus for detecting the upper and lower layer overlay of the wafer as claimed in claim 15, wherein the matching module further comprises an alignment unit, the alignment unit performs overlay with the outline collected on the wafer after amplifying the original layout, more than 80% of the original layout including the outline enters the matching module for matching, and the amplification factor is-1000 to + 1000.

17. The apparatus according to claim 12, wherein the calculation module calculates the alignment and overlay relationship between the pattern profile of one layer on the wafer and the original layout of each layer, and calculates the overlay accuracy of the pattern profile between different layers and the coverage of the upper and lower layers, and the coordinate system used in the calculation process is a wafer-based alignment system, i.e. the data of the layout of each layer is aligned with the pattern of the wafer of the layer.

18. An apparatus for detecting an overlay on a wafer, comprising a picture capture module, the picture capture module comprising: a high-speed electron gun, an infrared induction device and a large-field scanning device;

the high-speed electron gun emits high-speed high-energy electron beams, the wafer is scanned through the high-speed high-energy electron beams, and the large-field scanning device detects the distribution of electrons on the surface of the wafer to extract a pattern profile;

the device for detecting the upper and lower layer stacks of the wafer adopts the method for detecting the upper and lower layer stacks of the wafer as claimed in any one of claims 1 to 8 to realize the detection of the upper and lower layer stacks of the wafer.

19. The apparatus of claim 18, wherein the first layer pattern incorporates a high reflectivity material, the high reflectivity material being tungsten, aluminum or copper.

20. The apparatus of claim 18, wherein the large field scanning device further comprises a reflection electron collecting device, a magnetic material is added to the pattern of the first layer, the high-speed electron gun emits emission electrons onto the surface of the wafer, the reflection electron collecting device collects an electric field formed by a zero-order reflection signal of the emission electrons on the surface of the wafer and a model zero-order reflection signal, and the electric field signal enters the computing system to extract the pattern profile of the first layer covered by the second layer;

the magnetic material is any one or combination of NiFe, Co, Fe or Ni.