CN110855894A - Image data acquisition method and device - Google Patents
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- CN110855894A CN110855894A CN201911237247.4A CN201911237247A CN110855894A CN 110855894 A CN110855894 A CN 110855894A CN 201911237247 A CN201911237247 A CN 201911237247A CN 110855894 A CN110855894 A CN 110855894A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/66—Remote control of cameras or camera parts, e.g. by remote control devices
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Abstract
The application relates to an image data acquisition method and device, which belong to the technical field of logistics systems and comprise the following steps: performing serial-parallel conversion on image data generated by the linear array camera; performing first-level cache conversion on the image data subjected to serial-parallel conversion to obtain first image data; and performing second-level cache conversion on the first image data to obtain second image data. The problem of relatively poor relatively high consumption of the relatively poor stability of industrial camera operation among the prior art is solved, the effect that can improve industrial camera operation's stability reduces the consumption has been reached. Specifically, through adopting 96 bit's wide data, adopt the clock synchronization who is twice industrial camera's clock frequency to receive simultaneously, guaranteed the stability of camera, reduce the consumption and then reduce the heat dissipation of camera and make the effect that the heat dissipation satisfied the demand.
Description
Technical Field
The application relates to an image data acquisition method and device, and belongs to the technical field of logistics systems.
Background
At present, in the existing logistics sorting system in China, 5-area-array scanning industrial cameras are mostly adopted, when a worker puts a package on a trolley for conveying the package, the worker needs to ensure that a package sheet cannot face downwards, otherwise, the worker cannot be shot by the area-array industrial cameras, and therefore the working efficiency of the worker is reduced. If can utilize two dolly clearance departments in bottom surface to use the linear array camera scanning to shoot, just so can carry out six array codes to improve the efficiency of parcel letter sorting greatly. In this case, the line industrial camera ensures that the scanned image has a sufficiently large field of view (more than 1.10m of the trolley width) and a sufficiently high resolution (generally more than 180 DPI) to capture and normally recognize the bar code on the parcel single, while the effective scanning length of the non-contact sensor used by the line industrial camera is generally short (IT-K1-08240 line sensor is less than 0.06m), which requires that the effective scanning length of the non-contact sensor is enlarged by a sufficiently large factor through the lens.
However, the existing industrial cameras have poor stability and high power consumption.
Disclosure of Invention
The application provides an image data acquisition method and device, which can solve the problem that an industrial camera in the existing scheme is poor in operation stability and high in power consumption. The application provides the following technical scheme:
in a first aspect, an image data acquisition method and apparatus are provided, the method including:
performing serial-parallel conversion on image data generated by the linear array camera;
performing first-level cache conversion on the image data subjected to serial-parallel conversion to obtain first image data;
and performing second-level cache conversion on the first image data to obtain second image data.
Optionally, the performing a first-level cache conversion on the image data after the serial-parallel conversion to obtain first image data includes:
and sequentially writing the odd line data and the even line data which are output by the serial-parallel conversion into a cache to obtain the first image data.
Optionally, the writing the odd line data and the even line data output by the serial-parallel conversion into the buffer in sequence to obtain the first image data includes:
sequentially storing n-bit data of 16 channels of odd-numbered lines in 16 u _ ram _ row _ o;
n-bit data of 16 channels of the even-numbered rows are sequentially stored in 16 u _ ram _ row _ e.
Optionally, the write depth of the u _ ram _ row _ o and the u _ ram _ row _ e is 516 12bits, where the write depth includes 515 valid pixels and one 12-bit invalid data.
Optionally, performing second-level cache conversion on the first image data to obtain second image data includes:
while data is being written into the 16 u _ ram _ row _ e, 48-bit wide image data is simultaneously read in parallel from the 16 u _ ram _ row _ o, to which data has been written in the previous row, starting from address 0 with the read clock, and the read image data is written to the sec _ ram _ o _ inst with the write clock.
Optionally, the performing second-level cache conversion on the first image data to obtain second image data further includes:
while data is being written into the 16 u _ ram _ row _ o, 48-bit wide image data is simultaneously read in parallel from the 16 u _ ram _ row _ e starting with address 0 at the same time with the read clock, and the read image data is written into the sec _ ram _ e _ inst with the write clock.
Optionally, the write depth of the sec _ ram _ o _ inst or the sec _ ram _ e _ inst is 2060 48 bits.
Optionally, the method further includes:
and after second image data are obtained, deleting the invalid data of 516 th 12bit which is written into each channel in each row in the u _ ram _ row _ o and the u _ ram _ row _ e in more last.
Optionally, after the invalid data of 12bits is deleted, the gray values of the pixels in each row are recombined.
Optionally, the reconstructing the gray value of each pixel point in each row includes:
outputting pixel values of 16 pixel points at the ith clock rising edge, wherein i is an integer from 0 to 515, and the pixel value of each pixel point is 8 bits;
the pixel values of 16 invalid pixels are added at the 516 th clock rising edge.
In a second aspect, an image data acquisition apparatus is provided, the apparatus comprising a processor and a memory, the memory having at least one program instruction stored therein, the processor implementing the method according to the first aspect by loading and executing the at least one program instruction.
In a third aspect, there is provided a storage medium having stored therein at least one program instruction which is loaded and executed by a processor to implement the method of the first aspect.
The beneficial effect of this application lies in:
the image acquired by the industrial camera is subjected to first-level cache conversion and second-level cache conversion, so that second image data are obtained, the problem that the stability of operation of the industrial camera in the prior art is poor and the power consumption is high is solved, and the effect that the stability of operation of the industrial camera can be improved and the power consumption is reduced is achieved. Specifically, through adopting 96 bit's wide data, adopt the clock synchronization who is twice industrial camera's clock frequency to receive simultaneously, guaranteed the stability of camera, reduce the consumption and then reduce the heat dissipation of camera and make the effect that the heat dissipation satisfied the demand.
The foregoing description is only an overview of the technical solutions of the present application, and in order to make the technical solutions of the present application more clear and clear, and to implement the technical solutions according to the content of the description, the following detailed description is made with reference to the preferred embodiments of the present application and the accompanying drawings.
Drawings
FIG. 1 is a flow chart of a method of image data acquisition according to the present invention;
FIG. 2 is a schematic diagram of a serial-to-parallel conversion of acquired image data according to the present invention;
FIG. 3 is a diagram illustrating writing even row data according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a second-level cache interface according to an embodiment of the present invention;
fig. 5 and fig. 6 are schematic diagrams of an output sequence when image data is reorganized according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a format for reorganizing image data according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the present application will be described in conjunction with the accompanying drawings and examples. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
Referring to fig. 1, a flowchart of a method of acquiring image data according to an embodiment of the present application is shown, where as shown in fig. 1, the method includes:
optionally, 16 pairs of LVDS (Low-Voltage Differential Signaling) signals corresponding to the 16 channels are subjected to serial-to-parallel conversion, and finally, a pixel gray scale value represented by 12bits is acquired from each channel.
Referring to fig. 2, a schematic diagram of serial-to-parallel conversion of image data is shown. In the figure, DCM1(data communication module) is a combination of ibugdds, BUFIO (I/O port local Clock Buffer) and BUFR (Global Clock Buffer), IDELAY _ VALUE is used to set the delay VALUE of the channel corresponding to IDELAY 2, each channel adopts an asynchronous fifo processing Clock domain crossing design, and simultaneously converts the gray VALUE corresponding to each pixel point from two 6-bit data to a 12-bit data output.
102, performing first-level cache conversion on the image data subjected to serial-parallel conversion to obtain first image data;
and sequentially writing the odd line data and the even line data which are output by the serial-parallel conversion into a cache to obtain the first image data.
The 12-bit data of 16 channels (4 segments in total for sensors, and 4 channels in total for each segment) in the odd-numbered lines output in each MCLK clock cycle in the step 101 are respectively and sequentially stored in u _ ram _ row _ o of 16 sample dual port ram types, so as to prepare for subsequent 12-bit × 4 grouping.
Similarly, 12-bit data of 16 channels (4 segments for the sensor, and 4 channels for the segment) in the even-numbered lines output in each MCLK clock cycle are respectively and sequentially stored in u _ RAM _ row _ e of 16 sample dual port RAM types, so as to prepare for 12-bit × 4 grouping later.
Wherein, the write depth of each of u _ ram _ row _ o and u _ ram _ row _ e is 516 12 bits. The 516 12-bit data consists of 515 12-bit active pixels and 1 12-bit invalid data dark, and the 12-bit invalid data is only integer multiples of 4, namely each channel has only 515 valid pixel points.
For example, please refer to fig. 3, which shows a schematic diagram of storing even rows.
And 103, performing second-level cache conversion on the first image data to obtain second image data.
While writing image data to the 16 u _ RAM _ row _ e in step 102 above, please refer to fig. 4, read 48-bit wide image data simultaneously in parallel from the 16 u _ RAM _ row _ o written with data in the previous row starting with address 0 at the read clock of pix _ clk _ x4(160MHz) and write data1[47:0] to address sec _ RAM _ o _ wr _ addr [11:0] of sec _ RAM _ o _ inst of sampledual RAM type with write clock of pix _ clk _ x4(160 MHz); the write depth of each sec _ ram _ o _ inst is 2060 48 bits, which is the number of pixels in an entire odd-numbered row.
Similarly, while writing image data to the 16 u _ RAM _ row _ o in step 102 above, 48-bit wide image data is simultaneously read in parallel from the 16 u _ RAM _ row _ e starting at address 0 with a read clock of pix _ clk _ x4(160MHz) and data1[47:0] is written to address sec _ RAM _ e _ inst of the sample dual port RAM type at address sec _ RAM _ wr _ addr [11:0] with a write clock of pix _ clk _ x4(160 MHz); the writing depth of each sec _ ram _ e _ inst is 2060 48 bits, namely the number of pixels in an entire odd-numbered row.
It should be noted that the read data may be converted before the data is written into the sec _ ram _ o _ inst or the sec _ ram _ e _ inst. For example, the 8-bit address corresponding to 12bits × 4 data row _ e _ rdata [47:0] is read from u _ ram _ row _ e corresponding to each channel, and the 12-bit address after data conversion corresponding to data1[47:0] is written into sec _ ram _ e _ inst.
After the data writing is performed, the 516 th 12-bit data written by each channel in each row in the u _ ram _ row _ o and the u _ ram _ row _ e are deleted. And meanwhile, recombining the gray values of all the pixel points in one row. Optionally, referring to fig. 5, 4 segments (each segment has 4 channels) output the pixel values (each pixel value is 8 bits) of 16 pixels at the 1 st rising edge of the clock (denoted as time t 1); the 4 segments (each segment has 4 channels) simultaneously output the pixel values (each pixel value is 8 bits) of 16 pixels at the 2 nd clock rising edge (denoted as the time t 2), the t2 th pixel period is … …, and the 4 segments (each segment has 4 channels) simultaneously output the pixel values (each pixel value is 8 bits) of 16 pixels at the 515 th clock rising edge (denoted as the time t 515); in order to facilitate output conversion of each channel (channel) in each subsequent segment by 4 pixels, the pixel values of the invalid pixels are added at the 516 th clock rising edge (denoted as time t 516), as shown in fig. 5, the pixel values of the invalid pixels are discarded after conversion, and the output sequence of each pixel after recombination is shown in fig. 7. Please refer to fig. 6, table 1 and table 2, which show specific conversion processes during data reassembly, and this embodiment is not described herein again.
TABLE 1
TABLE 2
When image output is required, image data output of 96bit width is sequentially read from two sec _ ram _ o and sec _ ram _ e in order using a clock pix _ clk _ x2(80 MHz).
In summary, the first-level cache conversion and the second-level cache conversion are performed on the image acquired by the industrial camera, so that the second image data is obtained, the problem that the stability of the operation of the industrial camera in the prior art is poor and the power consumption is high is solved, and the effects of improving the stability of the operation of the industrial camera and reducing the power consumption are achieved. Specifically, through adopting 96 bit's wide data, adopt the clock synchronization who is twice industrial camera's clock frequency to receive simultaneously, guaranteed the stability of camera, reduce the consumption and then reduce the heat dissipation of camera and make the effect that the heat dissipation satisfied the demand.
The embodiment also provides an image data acquisition device, which comprises a processor and a memory, wherein the memory is stored with at least one program instruction, and the processor is used for realizing the method by loading and executing the at least one program instruction.
The present embodiment also provides a storage medium, in which at least one program instruction is stored, and the at least one program instruction is loaded and executed by a processor to implement the method described above.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (11)
1. A method of image data acquisition, the method comprising:
performing serial-parallel conversion on image data generated by the linear array camera;
performing first-level cache conversion on the image data subjected to serial-parallel conversion to obtain first image data;
and performing second-level cache conversion on the first image data to obtain second image data.
2. The method according to claim 1, wherein performing a first-level cache conversion on the serial-to-parallel converted image data to obtain first image data comprises:
and sequentially writing the odd line data and the even line data which are output by the serial-parallel conversion into a cache to obtain the first image data.
3. The method according to claim 2, wherein the writing of the odd line data and the even line data output by the serial-parallel conversion into the buffer in sequence to obtain the first image data comprises:
sequentially storing n-bit data of 16 channels of odd-numbered lines in 16 u _ ram _ row _ o;
n-bit data of 16 channels of the even-numbered rows are sequentially stored in 16 u _ ram _ row _ e.
4. The method of claim 3, wherein the write depth of the u _ ram _ row _ o and the u _ ram _ row _ e is 516 bits and 12bits, and the write depth comprises 515 valid pixels and one 12bits of invalid data.
5. The method of claim 3, wherein performing a second level cache conversion on the first image data to obtain second image data comprises:
while data is being written into the 16 u _ ram _ row _ e, 48-bit wide image data is simultaneously read in parallel from the 16 u _ ram _ row _ o, to which data has been written in the previous row, starting from address 0 with the read clock, and the read image data is written to the sec _ ram _ o _ inst with the write clock.
6. The method of claim 3, wherein performing a second level cache conversion on the first image data to obtain second image data further comprises:
while data is being written into the 16 u _ ram _ row _ o, 48-bit wide image data is simultaneously read in parallel from the 16 u _ ram _ row _ e starting with address 0 at the same time with the read clock, and the read image data is written into the sec _ ram _ e _ inst with the write clock.
7. The method of claim 5 or 6, wherein the write depth of the sec _ ram _ o _ inst or the sec _ ram _ e _ inst is 2060 48 bits.
8. The method of claim 4, further comprising:
and after second image data are obtained, deleting the invalid data of 516 th 12bit which is written into each channel in each row in the u _ ram _ row _ o and the u _ ram _ row _ e in more last.
9. The method of claim 8,
and after the invalid data of 12bits are deleted, recombining the gray values of all the pixel points in each row.
10. The method of claim 9, wherein the reconstructing the gray values of the pixels in each row comprises:
outputting pixel values of 16 pixel points at the ith clock rising edge, wherein i is an integer from 0 to 515, and the pixel value of each pixel point is 8 bits;
the pixel values of 16 invalid pixels are added at the 516 th clock rising edge.
11. An image data acquisition device, characterized in that the device comprises a processor and a memory, wherein at least one program instruction is stored in the memory, and the processor is used for realizing the method according to any one of claims 1 to 10 by loading and executing the at least one program instruction.
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